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rgu_18xx_43xx.h
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1 /*
2  * @brief LPC18xx/43xx Reset Generator Unit driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __RGU_18XX_43XX_H_
33 #define __RGU_18XX_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef enum CHIP_RGU_RST {
48  RGU_CORE_RST,
49  RGU_PERIPH_RST,
50  RGU_MASTER_RST,
51  RGU_WWDT_RST = 4,
52  RGU_CREG_RST,
53  RGU_BUS_RST = 8,
54  RGU_SCU_RST,
55  RGU_M3_RST = 13,
56  RGU_LCD_RST = 16,
57  RGU_USB0_RST,
58  RGU_USB1_RST,
59  RGU_DMA_RST,
60  RGU_SDIO_RST,
61  RGU_EMC_RST,
62  RGU_ETHERNET_RST,
63  RGU_FLASHA_RST = 25,
64  RGU_EEPROM_RST = 27,
65  RGU_GPIO_RST,
66  RGU_FLASHB_RST,
67  RGU_TIMER0_RST = 32,
68  RGU_TIMER1_RST,
69  RGU_TIMER2_RST,
70  RGU_TIMER3_RST,
71  RGU_RITIMER_RST,
72  RGU_SCT_RST,
73  RGU_MOTOCONPWM_RST,
74  RGU_QEI_RST,
75  RGU_ADC0_RST,
76  RGU_ADC1_RST,
77  RGU_DAC_RST,
78  RGU_UART0_RST = 44,
79  RGU_UART1_RST,
80  RGU_UART2_RST,
81  RGU_UART3_RST,
82  RGU_I2C0_RST,
83  RGU_I2C1_RST,
84  RGU_SSP0_RST,
85  RGU_SSP1_RST,
86  RGU_I2S_RST,
87  RGU_SPIFI_RST,
88  RGU_CAN1_RST,
89  RGU_CAN0_RST,
90 #ifdef CHIP_LPC43XX
91  RGU_M0APP_RST,
92  RGU_SGPIO_RST,
93  RGU_SPI_RST,
94 #endif
95  RGU_LAST_RST = 63,
96 } CHIP_RGU_RST_T;
97 
101 typedef struct {
102  __I uint32_t RESERVED0[64];
103  __O uint32_t RESET_CTRL0;
104  __O uint32_t RESET_CTRL1;
105  __I uint32_t RESERVED1[2];
106  __IO uint32_t RESET_STATUS0;
107  __IO uint32_t RESET_STATUS1;
108  __IO uint32_t RESET_STATUS2;
109  __IO uint32_t RESET_STATUS3;
110  __I uint32_t RESERVED2[12];
111  __I uint32_t RESET_ACTIVE_STATUS0;
112  __I uint32_t RESET_ACTIVE_STATUS1;
113  __I uint32_t RESERVED3[170];
114  __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];
115 } LPC_RGU_T;
116 
122 void Chip_RGU_TriggerReset(CHIP_RGU_RST_T ResetNumber);
123 
129 bool Chip_RGU_InReset(CHIP_RGU_RST_T ResetNumber);
130 
139 void Chip_RGU_ClearReset(CHIP_RGU_RST_T ResetNumber);
140 
145 #ifdef __cplusplus
146 }
147 #endif
148 
149 #endif /* __RGU_18XX_43XX_H_ */