sdmmc_001.h

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/*
 * @brief SD/SDIO (MCI) registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __SDMMC_001_H_
#define __SDMMC_001_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {    
 __IO uint32_t  CTRL;  
 __IO uint32_t  PWREN;  
 __IO uint32_t  CLKDIV;  
 __IO uint32_t  CLKSRC;  
 __IO uint32_t  CLKENA;  
 __IO uint32_t  TMOUT;  
 __IO uint32_t  CTYPE;  
 __IO uint32_t  BLKSIZ;  
 __IO uint32_t  BYTCNT;  
 __IO uint32_t  INTMASK;  
 __IO uint32_t  CMDARG;  
 __IO uint32_t  CMD;   
 __I  uint32_t  RESP0;  
 __I  uint32_t  RESP1;  
 __I  uint32_t  RESP2;  
 __I  uint32_t  RESP3;  
 __I  uint32_t  MINTSTS;  
 __IO uint32_t  RINTSTS;  
 __I  uint32_t  STATUS;  
 __IO uint32_t  FIFOTH;  
 __I  uint32_t  CDETECT;  
 __I  uint32_t  WRTPRT;  
 __IO uint32_t  GPIO;  
 __I  uint32_t  TCBCNT;  
 __I  uint32_t  TBBCNT;  
 __IO uint32_t  DEBNCE;  
 __IO uint32_t  USRID;  
 __I  uint32_t  VERID;  
 __I  uint32_t  RESERVED0;
 __IO uint32_t  UHS_REG;  
 __IO uint32_t  RST_N;  
 __I  uint32_t  RESERVED1;
 __IO uint32_t  BMOD;  
 __O  uint32_t  PLDMND;  
 __IO uint32_t  DBADDR;  
 __IO uint32_t  IDSTS;  
 __IO uint32_t  IDINTEN;  
 __I  uint32_t  DSCADDR;  
 __I  uint32_t  BUFADDR;  
} IP_SDMMC_001_T;

#define MCI_DMADES0_OWN         (1UL << 31)  
#define MCI_DMADES0_CES         (1 << 30)  
#define MCI_DMADES0_ER          (1 << 5)  
#define MCI_DMADES0_CH          (1 << 4)  
#define MCI_DMADES0_FS          (1 << 3)  
#define MCI_DMADES0_LD          (1 << 2)  
#define MCI_DMADES0_DIC         (1 << 1)  
#define MCI_DMADES1_BS1(x)      (x)    
#define MCI_DMADES1_BS2(x)      ((x) << 13)  
#define MCI_DMADES1_MAXTR       4096   
#define MCI_CTRL_USE_INT_DMAC   (1 << 25)  
#define MCI_CTRL_CARDV_MASK     (0x7 << 16)  
#define MCI_CTRL_CEATA_INT_EN   (1 << 11)  
#define MCI_CTRL_SEND_AS_CCSD   (1 << 10)  
#define MCI_CTRL_SEND_CCSD      (1 << 9)  
#define MCI_CTRL_ABRT_READ_DATA (1 << 8)  
#define MCI_CTRL_SEND_IRQ_RESP  (1 << 7)  
#define MCI_CTRL_READ_WAIT      (1 << 6)  
#define MCI_CTRL_INT_ENABLE     (1 << 4)  
#define MCI_CTRL_DMA_RESET      (1 << 2)  
#define MCI_CTRL_FIFO_RESET     (1 << 1)  
#define MCI_CTRL_RESET          (1 << 0)  
#define MCI_POWER_ENABLE        0x1    
#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) 
#define MCI_CLKSRC_CLKDIV0      0
#define MCI_CLKSRC_CLKDIV1      1
#define MCI_CLKSRC_CLKDIV2      2
#define MCI_CLKSRC_CLKDIV3      3
#define MCI_CLK_SOURCE(clksrc)  (clksrc)  
#define MCI_CLKEN_LOW_PWR       (1 << 16)  
#define MCI_CLKEN_ENABLE        (1 << 0)  
#define MCI_TMOUT_DATA(clks)    ((clks) << 8) 
#define MCI_TMOUT_DATA_MSK      0xFFFFFF00
#define MCI_TMOUT_RESP(clks)    ((clks) & 0xFF) 
#define MCI_TMOUT_RESP_MSK      0xFF

#define MCI_CTYPE_8BIT          (1 << 16)  
#define MCI_CTYPE_4BIT          (1 << 0)  
#define MCI_INT_SDIO            (1 << 16)  
#define MCI_INT_EBE             (1 << 15)  
#define MCI_INT_ACD             (1 << 14)  
#define MCI_INT_SBE             (1 << 13)  
#define MCI_INT_HLE             (1 << 12)  
#define MCI_INT_FRUN            (1 << 11)  
#define MCI_INT_HTO             (1 << 10)  
#define MCI_INT_DTO             (1 << 9)  
#define MCI_INT_RTO             (1 << 8)  
#define MCI_INT_DCRC            (1 << 7)  
#define MCI_INT_RCRC            (1 << 6)  
#define MCI_INT_RXDR            (1 << 5)  
#define MCI_INT_TXDR            (1 << 4)  
#define MCI_INT_DATA_OVER       (1 << 3)  
#define MCI_INT_CMD_DONE        (1 << 2)  
#define MCI_INT_RESP_ERR        (1 << 1)  
#define MCI_INT_CD              (1 << 0)  
#define MCI_CMD_START           (1UL << 31)  
#define MCI_CMD_VOLT_SWITCH     (1 << 28)  
#define MCI_CMD_BOOT_MODE       (1 << 27)  
#define MCI_CMD_DISABLE_BOOT    (1 << 26)  
#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25)  
#define MCI_CMD_ENABLE_BOOT     (1 << 24)  
#define MCI_CMD_CCS_EXP         (1 << 23)  
#define MCI_CMD_CEATA_RD        (1 << 22)  
#define MCI_CMD_UPD_CLK         (1 << 21)  
#define MCI_CMD_INIT            (1 << 15)  
#define MCI_CMD_STOP            (1 << 14)  
#define MCI_CMD_PRV_DAT_WAIT    (1 << 13)  
#define MCI_CMD_SEND_STOP       (1 << 12)  
#define MCI_CMD_STRM_MODE       (1 << 11)  
#define MCI_CMD_DAT_WR          (1 << 10)  
#define MCI_CMD_DAT_EXP         (1 << 9)  
#define MCI_CMD_RESP_CRC        (1 << 8)  
#define MCI_CMD_RESP_LONG       (1 << 7)  
#define MCI_CMD_RESP_EXP        (1 << 6)  
#define MCI_CMD_INDX(n)         ((n) & 0x1F)

#define MCI_STS_GET_FCNT(x)     (((x) >> 17) & 0x1FF)

#define MCI_FIFOTH_TX_WM(x)     ((x) & 0xFFF)
#define MCI_FIFOTH_RX_WM(x)     (((x) & 0xFFF) << 16)
#define MCI_FIFOTH_DMA_MTS_1    (0UL << 28)
#define MCI_FIFOTH_DMA_MTS_4    (1UL << 28)
#define MCI_FIFOTH_DMA_MTS_8    (2UL << 28)
#define MCI_FIFOTH_DMA_MTS_16   (3UL << 28)
#define MCI_FIFOTH_DMA_MTS_32   (4UL << 28)
#define MCI_FIFOTH_DMA_MTS_64   (5UL << 28)
#define MCI_FIFOTH_DMA_MTS_128  (6UL << 28)
#define MCI_FIFOTH_DMA_MTS_256  (7UL << 28)

#define MCI_BMOD_PBL1           (0 << 8)  
#define MCI_BMOD_PBL4           (1 << 8)  
#define MCI_BMOD_PBL8           (2 << 8)  
#define MCI_BMOD_PBL16          (3 << 8)  
#define MCI_BMOD_PBL32          (4 << 8)  
#define MCI_BMOD_PBL64          (5 << 8)  
#define MCI_BMOD_PBL128         (6 << 8)  
#define MCI_BMOD_PBL256         (7 << 8)  
#define MCI_BMOD_DE             (1 << 7)  
#define MCI_BMOD_DSL(len)       ((len) << 2) 
#define MCI_BMOD_FB             (1 << 1)  
#define MCI_BMOD_SWR            (1 << 0)  
#define SD_FIFO_SZ              32    
typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);

typedef int32_t (*PSCHECK_FUNC_T)(void);

typedef void (*PS_POWER_FUNC_T)(int32_t enable);

typedef struct {
 volatile uint32_t des0;      
 volatile uint32_t des1;      
 volatile uint32_t des2;      
 volatile uint32_t des3;      
} pSDMMC_DMA_T;

typedef struct _sdif_device {
 /* MCI_IRQ_CB_FUNC_T irq_cb; */
 pSDMMC_DMA_T mci_dma_dd[1 + (0x100000 / MCI_DMADES1_MAXTR)];
 /* uint32_t sdio_clk_rate; */
 /* uint32_t sdif_slot_clk_rate; */
 /* int32_t clock_enabled; */
} sdif_device;

void IP_SDMMC_Init(IP_SDMMC_001_T *pSDMMC);

void IP_SDMMC_DeInit(IP_SDMMC_001_T *pSDMMC);

void IP_SDMMC_SetBlkSize(IP_SDMMC_001_T *pSDMMC, uint32_t bytes);

void IP_SDMMC_Reset(IP_SDMMC_001_T *pSDMMC, int32_t reset);

STATIC INLINE void IP_SDMMC_PowerOn(IP_SDMMC_001_T *pSDMMC)
{
 pSDMMC->PWREN = 1;
}

STATIC INLINE void IP_SDMMC_PowerOff(IP_SDMMC_001_T *pSDMMC)
{
 pSDMMC->PWREN = 0;
}

STATIC INLINE int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_T *pSDMMC)
{
 return (pSDMMC->WRTPRT & 1);
}

STATIC INLINE int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_T *pSDMMC)
{
 return (pSDMMC->CDETECT & 1);
}

int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_T *pSDMMC, uint32_t cmd, uint32_t arg);

void IP_SDMMC_GetResponse(IP_SDMMC_001_T *pSDMMC, uint32_t *resp);

void IP_SDMMC_SetClock(IP_SDMMC_001_T *pSDMMC, uint32_t clk_rate, uint32_t speed);

void IP_SDMMC_SetCardType(IP_SDMMC_001_T *pSDMMC, uint32_t ctype);

void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_T *pSDMMC);

uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_T *pSDMMC);

void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_T *pSDMMC, uint32_t iVal);

void IP_SDMMC_SetIntMask(IP_SDMMC_001_T *pSDMMC, uint32_t iVal);

void IP_SDMMC_DmaSetup(IP_SDMMC_001_T *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size);

void IP_SDMMC_SetBlkSizeByteCnt(IP_SDMMC_001_T *pSDMMC, uint32_t blk_size);

void IP_SDMMC_SetByteCnt(IP_SDMMC_001_T *pSDMMC, uint32_t bytes);

#ifdef __cplusplus
}
#endif

#endif /* __SDMMC_001_H_ */