spi_001.h

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/*
 * @brief SPI registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __SPI_001_H_
#define __SPI_001_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {     
 __IO uint32_t  CR;    
 __I  uint32_t  SR;    
 __IO uint32_t  DR;    
 __IO uint32_t  CCR;    
 __I  uint32_t  RESERVED0[3];
 __IO uint32_t  INT;    
} IP_SPI_001_T;

/*
 * Macro defines for SPI Control register
 */
/* SPI CFG Register BitMask */
#define SPI_CR_BITMASK       ((uint32_t) 0xFFC)

#define SPI_CR_BIT_EN         ((uint32_t) (1 << 2))

#define SPI_CR_BITS_MASK      ((uint32_t) 0xF00)

#define SPI_CR_BITS(n)        ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */

#define SPI_CR_CPHA_FIRST     ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
#define SPI_CR_CPHA_SECOND    ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/

#define SPI_CR_CPOL_LO        ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
#define SPI_CR_CPOL_HI        ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/

#define SPI_CR_SLAVE_EN       ((uint32_t) 0)

#define SPI_CR_MASTER_EN      ((uint32_t) (1 << 5))

#define SPI_CR_MSB_FIRST_EN   ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/

#define SPI_CR_LSB_FIRST_EN   ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/

#define SPI_CR_INT_EN         ((uint32_t) (1 << 7))

/*
 * Macro defines for SPI Status register
 */
#define SPI_SR_BITMASK        ((uint32_t) 0xF8)

#define SPI_SR_ABRT           ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
/* Mode fault Flag */
#define SPI_SR_MODF           ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */

#define SPI_SR_ROVR           ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */

#define SPI_SR_WCOL           ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */

#define SPI_SR_SPIF           ((uint32_t) (1 << 7))  /* When 1, this bit indicates when a SPI data transfer is complete.. */

#define SPI_SR_ERROR          (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
/*
 * Macro defines for SPI Test Control Register register
 */
/*Enable SPI Test Mode */
#define SPI_TCR_TEST(n)       ((uint32_t) ((n & 0x3F) << 1))

/*
 * Macro defines for SPI Interrupt register
 */
#define SPI_INT_SPIF          ((uint32_t) (1 << 0))

#define SPI_DR_DATA(n)        ((uint32_t) ((n) & 0xFFFF))

typedef enum IP_SPI_MODE {
 SPI_MODE_MASTER = SPI_CR_MASTER_EN,   /* Master Mode */
 SPI_MODE_SLAVE = SPI_CR_SLAVE_EN,   /* Slave Mode */
} IP_SPI_MODE_T;

typedef enum IP_SPI_CLOCK_MODE {
 SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST,  
 SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST,  
 SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, 
 SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, 
 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,
 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,
 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,
 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,
} IP_SPI_CLOCK_MODE_T;

typedef enum IP_SPI_DATA_ORDER {
 SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN,   /* Standard Order */
 SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN,   /* Reverse Order */
} IP_SPI_DATA_ORDER_T;

/*
 * @brief Number of bits per frame
 */
typedef enum IP_SPI_BITS {
 SPI_BITS_8 = SPI_CR_BITS(8),  
 SPI_BITS_9 = SPI_CR_BITS(9),  
 SPI_BITS_10 = SPI_CR_BITS(10),  
 SPI_BITS_11 = SPI_CR_BITS(11),  
 SPI_BITS_12 = SPI_CR_BITS(12),  
 SPI_BITS_13 = SPI_CR_BITS(13),  
 SPI_BITS_14 = SPI_CR_BITS(14),  
 SPI_BITS_15 = SPI_CR_BITS(15),  
 SPI_BITS_16 = SPI_CR_BITS(16),  
} IP_SPI_BITS_T;

STATIC INLINE uint32_t IP_SPI_GetStatus(IP_SPI_001_T *pSPI)
{
 return pSPI->SR;
}

STATIC INLINE void IP_SPI_IntEnable(IP_SPI_001_T *pSPI)
{
 pSPI->CR |= SPI_CR_INT_EN;
}

STATIC INLINE void IP_SPI_IntDisable(IP_SPI_001_T *pSPI)
{
 pSPI->CR &= ~SPI_CR_INT_EN;
}

STATIC INLINE uint32_t IP_SPI_GetIntStatus(IP_SPI_001_T *pSPI)
{
 return pSPI->INT;
}

STATIC INLINE void IP_SPI_ClearIntStatus(IP_SPI_001_T *pSPI, uint32_t mask)
{
 pSPI->INT = mask;
}

STATIC INLINE void IP_SPI_SendFrame(IP_SPI_001_T *pSPI, uint16_t data)
{
 pSPI->DR = SPI_DR_DATA(data);
}

STATIC INLINE uint16_t IP_SPI_ReceiveFrame(IP_SPI_001_T *pSPI)
{
 return SPI_DR_DATA(pSPI->DR);
}

STATIC INLINE void IP_SPI_SetClockCounter(IP_SPI_001_T *pSPI, uint32_t counter)
{
 pSPI->CCR = counter;
}

STATIC INLINE void IP_SPI_SetFormat(IP_SPI_001_T *pSPI, IP_SPI_BITS_T bits,
         IP_SPI_CLOCK_MODE_T clockMode, IP_SPI_DATA_ORDER_T order)
{
 pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | bits | clockMode | order;
}

STATIC INLINE IP_SPI_BITS_T IP_SPI_GetDataSize(IP_SPI_001_T *pSPI)
{
 return (pSPI->CR & SPI_CR_BIT_EN) ? ((IP_SPI_BITS_T) (pSPI->CR & SPI_CR_BITS_MASK)) : SPI_BITS_8;
}

STATIC INLINE IP_SPI_CLOCK_MODE_T IP_SPI_GetClockMode(IP_SPI_001_T *pSPI)
{
 return (IP_SPI_CLOCK_MODE_T) (pSPI->CR & (3 << 3));
}

STATIC INLINE void IP_SPI_SetMode(IP_SPI_001_T *pSPI, IP_SPI_MODE_T mode)
{
 pSPI->CR = (pSPI->CR & (~(1 << 5))) | mode;
}

STATIC INLINE IP_SPI_MODE_T IP_SPI_GetMode(IP_SPI_001_T *pSPI)
{
 return (IP_SPI_MODE_T) (pSPI->CR & (1 << 5));
}

#ifdef __cplusplus
}
#endif

#endif /* __SPI_001_H_ */