spi_002.h

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/*
 * @brief SPI registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __SPI_002_H_
#define __SPI_002_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {     
 __IO uint32_t  CFG;    
 __IO uint32_t  DLY;    
 __IO uint32_t  STAT;   
 __IO uint32_t  INTENSET;  
 __O  uint32_t  INTENCLR;  
 __I  uint32_t  RXDAT;   
 __IO uint32_t  TXDATCTL;  
 __IO uint32_t  TXDAT;   
 __IO uint32_t  TXCTRL;   
 __IO uint32_t  DIV;    
 __I  uint32_t  INTSTAT;   
} IP_SPI_002_T;

/* SPI CFG Register BitMask */
#define SPI_CFG_BITMASK     ((uint32_t) 0x1BD)

#define SPI_CFG_SPI_EN      ((uint32_t) (1 << 0))

#define SPI_CFG_SLAVE_EN   ((uint32_t) 0)

#define SPI_CFG_MASTER_EN   ((uint32_t) (1 << 2))

#define SPI_CFG_MSB_FIRST_EN   ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/

#define SPI_CFG_LSB_FIRST_EN   ((uint32_t) (1 << 3))/*Data will be transmitted and received in reverse order (LSB first).*/

#define SPI_CFG_CPHA_FIRST   ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
#define SPI_CFG_CPHA_SECOND  ((uint32_t) (1 << 4)) /*Change data on the first edge, Capture data on the following edge*/

#define SPI_CFG_CPOL_LO     ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
#define SPI_CFG_CPOL_HI     ((uint32_t) (1 << 5)) /* The rest state of the clock (between frames) is high.*/

#define SPI_CFG_LBM_EN      ((uint32_t) (1 << 7))

#define SPI_CFG_SPOL_LO     ((uint32_t) (0))  /* SSEL is active Low */
#define SPI_CFG_SPOL_HI     ((uint32_t) (1 << 8)) /* SSEL is active High */

#define  SPI_DLY_BITMASK        ((uint32_t) 0xFFFF)

#define  SPI_DLY_PRE_DELAY(n)        ((uint32_t) ((n) & 0x0F))    /* Time Unit: SPI clock time */

#define  SPI_DLY_POST_DELAY(n)       ((uint32_t) (((n) & 0x0F) << 4))  /* Time Unit: SPI clock time */

#define  SPI_DLY_FRAME_DELAY(n)      ((uint32_t) (((n) & 0x0F) << 8))  /* Time Unit: SPI clock time */

#define  SPI_DLY_TRANSFER_DELAY(n)   ((uint32_t) (((n) & 0x0F) << 12)) /* Time Unit: SPI clock time */

/* SPI STAT Register BitMask */
#define SPI_STAT_BITMASK        ((uint32_t) 0x1FF)
/* Receiver Ready Flag */
#define SPI_STAT_RXRDY          ((uint32_t) (1 << 0)) /* Data is ready for read */
/* Transmitter Ready Flag */
#define SPI_STAT_TXRDY          ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */
/* Receiver Overrun interrupt flag */
#define SPI_STAT_RXOV           ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */
/* Transmitter Underrun interrupt flag (In Slave Mode only) */
#define SPI_STAT_TXUR           ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */
/* Slave Select Assert */
#define SPI_STAT_SSA            ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */
/* Slave Select Deassert */
#define SPI_STAT_SSD            ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */
/* Stalled status flag */
#define SPI_STAT_STALLED        ((uint32_t) (1 << 6)) /* SPI is currently in a stall condition. */
/* End Transfer flag. */
#define SPI_STAT_EOT            ((uint32_t) (1 << 7)) /* The current frame is the last frame of the current  transfer. */
/* Idle status flag. */
#define SPI_STAT_LE         ((uint32_t) (1 << 8)) /* SPI master function is fully idle. */

/* Clear RXOV Flag */
#define SPI_STAT_CLR_RXOV       ((uint32_t) (1 << 2))
/* Clear TXUR Flag */
#define SPI_STAT_CLR_TXUR       ((uint32_t) (1 << 3))
/* Clear SSA Flag */
#define SPI_STAT_CLR_SSA        ((uint32_t) (1 << 4))
/* Clear SSD Flag */
#define SPI_STAT_CLR_SSD        ((uint32_t) (1 << 5))
/*Force an end to the current transfer */
#define SPI_STAT_FORCE_EOT      ((uint32_t) (1 << 7))

/* SPI INTENSET Register BitMask */
#define SPI_INTENSET_BITMASK    ((uint32_t) 0x3F)

#define SPI_INTENSET_RXDYEN     ((uint32_t) (1 << 0))

#define SPI_INTENSET_TXDYEN     ((uint32_t) (1 << 1))

#define SPI_INTENSET_RXOVEN     ((uint32_t) (1 << 2))

#define SPI_INTENSET_TXUREN     ((uint32_t) (1 << 3))

#define SPI_INTENSET_SSAEN      ((uint32_t) (1 << 2))

#define SPI_INTENSET_SSDEN      ((uint32_t) (1 << 2))

/* SPI INTENCLR Register BitMask */
#define SPI_INTENCLR_BITMASK    ((uint32_t) 0x3F)

#define SPI_INTENCLR_RXDYEN     ((uint32_t) (1 << 0))

#define SPI_INTENCLR_TXDYEN     ((uint32_t) (1 << 1))

#define SPI_INTENCLR_RXOVEN     ((uint32_t) (1 << 2))

#define SPI_INTENCLR_TXUREN     ((uint32_t) (1 << 3))

#define SPI_INTENCLR_SSAEN      ((uint32_t) (1 << 2))

#define SPI_INTENCLR_SSDEN      ((uint32_t) (1 << 2))

/* SPI RXDAT Register BitMask */
#define SPI_RXDAT_BITMASK       ((uint32_t) 0x11FFFF)

#define SPI_RXDAT_DATA(n)       ((uint32_t) ((n) & 0xFFFF))

#define SPI_RXDAT_RXSSELN_ACTIVE    ((uint32_t) 0)  /* SSEL is in active state */
#define SPI_RXDAT_RXSSELN_INACTIVE  ((uint32_t) (1 << 16)) /* SSEL is in inactive state */

#define SPI_RXDAT_SOT           ((uint32_t) (1 << 20)) /* This is the first frame received after SSEL is asserted */

/* SPI TXDATCTL Register BitMask */
#define SPI_TXDATCTL_BITMASK    ((uint32_t) 0xF71FFFF)
/* SPI Transmit Data */
#define SPI_TXDATCTL_DATA(n)    ((uint32_t) ((n) & 0xFFFF))
/*Assert/Deassert SSL pin*/
#define SPI_TXDATCTL_ASSERT_SSEL    ((uint32_t) 0)
#define SPI_TXDATCTL_DEASSERT_SSEL  ((uint32_t) (1 << 16))

#define SPI_TXDATCTL_EOT            ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */

#define SPI_TXDATCTL_EOF            ((uint32_t) (1 << 21)) /* This is the last part of the current frame */

#define SPI_TXDATCTL_RXIGNORE       ((uint32_t) (1 << 22)) /* Received data is ignored */

#define SPI_TXDATCTL_FLEN(n)        ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */

/* SPI Transmit Data */
#define SPI_TXDAT_DATA(n)   ((uint32_t) ((n) & 0xFFFF))

/* SPI TXDATCTL Register BitMask */
#define SPI_TXCTL_BITMASK   ((uint32_t) 0xF71FF00)
/*Assert/Deassert SSL pin*/
#define SPI_TXCTL_ASSERT_SSEL   ((uint32_t) 0)
#define SPI_TXCTL_DEASSERT_SSEL ((uint32_t) (1 << 16))

#define SPI_TXCTL_EOT           ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */

#define SPI_TXCTL_EOF           ((uint32_t) (1 << 21)) /* This is the last part of the current frame */

#define SPI_TXCTL_RXIGNORE      ((uint32_t) (1 << 22)) /* Received data is ignored */

#define SPI_TXCTL_FLEN(n)       ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */

#define SPI_DIV_VAL(n)          ((uint32_t) ((n) & 0xFFFF)) /* SPI_CLK = PCLK/(DIV_VAL+1)*/

/* SPI INTSTAT Register Bitmask */
#define SPI_INTSTAT_BITMASK     ((uint32_t) 0x3F)
/* Receiver Ready Flag */
#define SPI_INTSTAT_RXRDY           ((uint32_t) (1 << 0)) /* Data is ready for read */
/* Transmitter Ready Flag */
#define SPI_INTSTAT_TXRDY           ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */
/* Receiver Overrun interrupt flag */
#define SPI_INTSTAT_RXOV            ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */
/* Transmitter Underrun interrupt flag (In Slave Mode only) */
#define SPI_INTSTAT_TXUR            ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */
/* Slave Select Assert */
#define SPI_INTSTAT_SSA         ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */
/* Slave Select Deassert */
#define SPI_INTSTAT_SSD         ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */

typedef enum IP_SPI_MODE {
 SPI_MODE_MASTER = SPI_CFG_MASTER_EN,  /* Master Mode */
 SPI_MODE_SLAVE = SPI_CFG_SLAVE_EN,   /* Slave Mode */
} IP_SPI_MODE_T;

typedef enum IP_SPI_CLOCK_MODE {
 SPI_CLOCK_CPHA0_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST,  
 SPI_CLOCK_CPHA0_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST,  
 SPI_CLOCK_CPHA1_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND,   
 SPI_CLOCK_CPHA1_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND,   
 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,
 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,
 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,
 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,
} IP_SPI_CLOCK_MODE_T;

typedef enum IP_SPI_DATA_ORDER {
 SPI_DATA_MSB_FIRST = SPI_CFG_MSB_FIRST_EN,   /* Standard Order */
 SPI_DATA_LSB_FIRST = SPI_CFG_LSB_FIRST_EN,   /* Reverse Order */
} IP_SPI_DATA_ORDER_T;

typedef enum IP_SPI_SSEL_POL {
 SPI_SSEL_ACTIVE_LO = SPI_CFG_SPOL_LO,   /* SSEL is active Low*/
 SPI_SSEL_ACTIVE_HI = SPI_CFG_SPOL_HI,   /* SSEL is active  High */
} IP_SPI_SSEL_POL_T;

typedef struct {
 IP_SPI_MODE_T             Mode;   /* Mode Select */
 IP_SPI_CLOCK_MODE_T       ClockMode;  /* CPHA CPOL Select */
 IP_SPI_DATA_ORDER_T       DataOrder;  /* MSB/LSB First */
 IP_SPI_SSEL_POL_T         SSELPol;  /* SSEL Polarity Select */
 uint16_t                ClkDiv;   /* SPI Clock Divider Value */
} IP_SPI_CONFIG_T;

typedef struct {
 uint8_t     PreDelay;    /* Pre-delay value in SPI clock time */
 uint8_t     PostDelay;    /* Post-delay value in SPI clock time */
 uint8_t     FrameDelay;    /* Delay value between frames of a transfer in SPI clock time */
 uint8_t     TransferDelay;   /* Delay value between transfers in SPI clock time */
} IP_SPI_DELAY_CONFIG_T;

STATIC INLINE void IP_SPI_Enable(IP_SPI_002_T *pSPI)
{
 pSPI->CFG |= SPI_CFG_SPI_EN;
}

STATIC INLINE void IP_SPI_Disable(IP_SPI_002_T *pSPI)
{
 pSPI->CFG &= (~SPI_CFG_SPI_EN) & SPI_CFG_BITMASK;
}

STATIC INLINE void IP_SPI_DeInit(IP_SPI_002_T *pSPI)
{
 IP_SPI_Disable(pSPI);
}

STATIC INLINE void IP_SPI_EnableLoopBack(IP_SPI_002_T *pSPI)
{
 pSPI->CFG |= SPI_CFG_LBM_EN;
}

STATIC INLINE void IP_SPI_DisableLoopBack(IP_SPI_002_T *pSPI)
{
 pSPI->CFG &= (~SPI_CFG_LBM_EN) & SPI_CFG_BITMASK;
}

STATIC INLINE uint32_t IP_SPI_GetStatus(IP_SPI_002_T *pSPI)
{
 return pSPI->STAT;
}

STATIC INLINE void IP_SPI_ForceEOT(IP_SPI_002_T *pSPI)
{
 pSPI->STAT |= SPI_STAT_FORCE_EOT;
}

STATIC INLINE void IP_SPI_ClearStatus(IP_SPI_002_T *pSPI, uint32_t Flag)
{
 pSPI->STAT |= Flag;
}

STATIC INLINE void IP_SPI_IntEnable(IP_SPI_002_T *pSPI, uint32_t IntEnMsk)
{
 pSPI->INTENSET |= IntEnMsk;
}

STATIC INLINE void IP_SPI_IntDisable(IP_SPI_002_T *pSPI, uint32_t IntDisMsk)
{
 pSPI->INTENCLR |= IntDisMsk;
}

STATIC INLINE uint32_t IP_SPI_GetIntStatus(IP_SPI_002_T *pSPI)
{
 return pSPI->INTSTAT;
}

STATIC INLINE void IP_SPI_SendFrame(IP_SPI_002_T *pSPI, uint16_t data)
{
 pSPI->TXDAT = SPI_TXDAT_DATA(data);
}

STATIC INLINE void IP_SPI_SetControlInfo(IP_SPI_002_T *pSPI, uint8_t Flen, uint32_t Flag)
{
 pSPI->TXCTRL = Flag | SPI_TXDATCTL_FLEN(Flen - 1);
}

STATIC INLINE void IP_SPI_SendFrameAndControl(IP_SPI_002_T *pSPI, uint16_t TxData, uint8_t Flen, uint32_t Flag)
{
 pSPI->TXDATCTL = Flag | SPI_TXDATCTL_FLEN(Flen - 1) | SPI_TXDATCTL_DATA(TxData);
}

STATIC INLINE uint16_t IP_SPI_ReceiveFrame(IP_SPI_002_T *pSPI)
{
 return SPI_RXDAT_DATA(pSPI->RXDAT);
}

void IP_SPI_Init(IP_SPI_002_T *pSPI, IP_SPI_CONFIG_T *pConfig);

void IP_SPI_DelayConfig(IP_SPI_002_T *pSPI, IP_SPI_DELAY_CONFIG_T *pConfig);

#ifdef __cplusplus
}
#endif

#endif /* __SPI_002_H_ */