IP_I2S_001_T Struct Reference

Detailed Description

I2S register block structure.

Definition at line 50 of file i2s_001.h.

#include "i2s_001.h"

Data Fields
__IO uint32_t	DAO
__IO uint32_t	DAI
__O uint32_t	TXFIFO
__I uint32_t	RXFIFO
__I uint32_t	STATE
__IO uint32_t	DMA1
__IO uint32_t	DMA2
__IO uint32_t	IRQ
__IO uint32_t	TXRATE
__IO uint32_t	RXRATE
__IO uint32_t	TXBITRATE
__IO uint32_t	RXBITRATE
__IO uint32_t	TXMODE
__IO uint32_t	RXMODE

Field Documentation

__IO uint32_t DAI

I2S Digital Audio Input Register. Contains control bits for the I2S receive channel

Definition at line 52 of file i2s_001.h.

__IO uint32_t DAO

< I2S Structure I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel

Definition at line 51 of file i2s_001.h.

__IO uint32_t DMA1

I2S DMA Configuration Register 1. Contains control information for DMA request 1

Definition at line 56 of file i2s_001.h.

__IO uint32_t DMA2

I2S DMA Configuration Register 2. Contains control information for DMA request 2

Definition at line 57 of file i2s_001.h.

__IO uint32_t IRQ

I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated

Definition at line 58 of file i2s_001.h.

__IO uint32_t RXBITRATE

I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock

Definition at line 62 of file i2s_001.h.

__I uint32_t RXFIFO

I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO

Definition at line 54 of file i2s_001.h.

__IO uint32_t RXMODE

I2S Receive mode control

Definition at line 64 of file i2s_001.h.

__IO uint32_t RXRATE

I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK

Definition at line 60 of file i2s_001.h.

__I uint32_t STATE

I2S Status Feedback Register. Contains status information about the I2S interface

Definition at line 55 of file i2s_001.h.

__IO uint32_t TXBITRATE

I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock

Definition at line 61 of file i2s_001.h.

__O uint32_t TXFIFO

I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO

Definition at line 53 of file i2s_001.h.

__IO uint32_t TXMODE

I2S Transmit mode control

Definition at line 63 of file i2s_001.h.

__IO uint32_t TXRATE

I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK

Definition at line 59 of file i2s_001.h.

---

The documentation for this struct was generated from the following file:

• C:/nxp/v1.03/lpcopen_v1.03/lpcopen/software/lpc_core/lpc_ip/i2s_001.h