Detailed Description

Power Management Unit register block structure.

LPC8xx Power Management Unit register block structure.

Definition at line 47 of file pmu_11xx.h.

#include "pmu_11xx.h"

Field Documentation

__IO uint32_t DPDCTRL

Offset: 0x014 Deep power-down control register (R/W)

Definition at line 53 of file pmu_8xx.h.

__IO uint32_t GPREG[4]

Power GP register

Definition at line 49 of file pmu_11xx.h.

__IO uint32_t GPREG0

Offset: 0x004 General purpose Register 0 (R/W)

Definition at line 49 of file pmu_8xx.h.

__IO uint32_t GPREG1

Offset: 0x008 General purpose Register 1 (R/W)

Definition at line 50 of file pmu_8xx.h.

__IO uint32_t GPREG2

Offset: 0x00C General purpose Register 2 (R/W)

Definition at line 51 of file pmu_8xx.h.

__IO uint32_t GPREG3

Offset: 0x010 General purpose Register 3 (R/W)

Definition at line 52 of file pmu_8xx.h.

__IO uint32_t PCON

< PMU Structure Power control register

Offset: 0x000 Power control Register (R/W)

Definition at line 48 of file pmu_11xx.h.

The documentation for this struct was generated from the following files:

C:/nxp/v1.03/lpcopen_v1.03/lpcopen/software/lpc_core/lpc_chip/chip_11xx/pmu_11xx.h
C:/nxp/v1.03/lpcopen_v1.03/lpcopen/software/lpc_core/lpc_chip/chip_8xx/pmu_8xx.h