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LPCOpen Platform
v1.03
LPCOpen Platform for NXP LPC Microcontrollers
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LPC11XX System Control block structure.
LPC8XX System Control and Clock register block structure.
LPC17XX/40XX Clock and Power register block structure.
LPC13XX System Control block structure.
Definition at line 47 of file sysctl_11xx.h.
#include "sysctl_11xx.h"
| __IO uint32_t BODCTRL |
Brown Out Detect register
Offset: 0x150 BOD control (R/W)
Definition at line 90 of file sysctl_11xx.h.
| __IO uint32_t CANSLEEPCLR |
Offset: 0x110 (R/W) CAN Sleep Clear Register
Definition at line 87 of file sysctl_17xx_40xx.h.
| __IO uint32_t CANWAKEFLAGS |
Offset: 0x114 (R/W) CAN Wake-up Flags Register
Definition at line 88 of file sysctl_17xx_40xx.h.
| __IO uint32_t CCLKSEL |
Offset: 0x104 (R/W) CPU Clock Selection Register
Definition at line 84 of file sysctl_17xx_40xx.h.
| __IO uint32_t CLKOUTCFG |
Offset: 0x1C8 (R/W) Clock Output Configuration Register
Definition at line 118 of file sysctl_17xx_40xx.h.
| __IO uint32_t CLKOUTDIV |
Clock out divider register, not on LPC1102/04
Clock out divider register
Offset: 0x0E8 CLKOUT clock divider (R/W)
Definition at line 86 of file sysctl_11xx.h.
| __IO uint32_t CLKOUTSEL |
Clock out source select register, not on LPC1102/04
Clock out source select register
Offset: 0x0E0 CLKOUT clock source select (R/W)
Definition at line 84 of file sysctl_11xx.h.
| __IO uint32_t CLKOUTUEN |
Clock out source update enable register, not on LPC1102/04
Clock out source update enable register, not on LPC1311/13/42/43 only
Offset: 0x0E4 CLKOUT clock source update enable (R/W)
Definition at line 85 of file sysctl_11xx.h.
| __IO uint32_t CLKSRCSEL |
Offset: 0x10C (R/W) Clock Source Select Register
Definition at line 86 of file sysctl_17xx_40xx.h.
| __I uint32_t DEVICEID |
| __IO uint32_t DMAREQSEL |
Offset: 0x1C4 (R/W) DMA Request Select Register
Definition at line 117 of file sysctl_17xx_40xx.h.
| __IO uint32_t EMCCAL |
Offset: 0x1E0 (R/W) Calibration of programmable delays
Definition at line 125 of file sysctl_17xx_40xx.h.
| __IO uint32_t EMCCLKSEL |
Offset: 0x100 (R/W) External Memory Controller Clock Selection Register
Definition at line 82 of file sysctl_17xx_40xx.h.
| __IO uint32_t EMCDLYCTL |
Offset: 0x1DC (R/W) SDRAM programmable delays
Definition at line 124 of file sysctl_17xx_40xx.h.
| __IO uint32_t EXTINT |
Offset: 0x140 (R/W) External Interrupt Flag Register
Definition at line 90 of file sysctl_17xx_40xx.h.
| __IO uint32_t EXTMODE |
Offset: 0x148 (R/W) External Interrupt Mode Register
Definition at line 92 of file sysctl_17xx_40xx.h.
| __IO uint32_t EXTPOLAR |
Offset: 0x14C (R/W) External Interrupt Polarity Register
Definition at line 93 of file sysctl_17xx_40xx.h.
| __IO uint32_t EXTTRACECMD |
Offset: 0x0FC External trace buffer command register
Definition at line 121 of file syscon_8xx.h.
| __IO uint32_t FLASHCFG |
Offset: 0x000 (R/W) Flash Accelerator Configuration Register
Definition at line 67 of file sysctl_17xx_40xx.h.
| __IO uint32_t IOCONCLKDIV[7] |
Offset: 0x134 Peripheral clock x to the IOCON block for programmable glitch filter
Definition at line 124 of file syscon_8xx.h.
| __IO uint32_t IRCCTRL |
IRC control register, not on LPC11UXX and LPC11EXX
IRC control register
Definition at line 57 of file sysctl_11xx.h.
| __IO uint32_t IRQLATENCY |
IRQ delay register, on LPC11UXX and LPC11EXX only
Offset: 0x170 IRQ delay
Definition at line 93 of file sysctl_11xx.h.
| __IO uint32_t LCD_CFG |
Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register
Definition at line 113 of file sysctl_17xx_40xx.h.
| __IO uint32_t LFOSCCTRL |
LF oscillator control, LPC11AXX only
Definition at line 58 of file sysctl_11xx.h.
| __IO uint32_t MAINCLKSEL |
Main clock source select register
Offset: 0x070 Main clock source select (R/W)
Definition at line 66 of file sysctl_11xx.h.
| __IO uint32_t MAINCLKUEN |
Main clock source update enable register
Offset: 0x074 Main clock source update enable (R/W)
Definition at line 67 of file sysctl_11xx.h.
| __IO uint32_t MEMMAP |
Offset: 0x000 (R/W) Flash Accelerator Configuration Register
Definition at line 69 of file sysctl_17xx_40xx.h.
| __IO uint32_t NMISRC |
NMI source control register,some parts only
Offset: 0x174 NMI Source Control
Definition at line 94 of file sysctl_11xx.h.
| __IO uint32_t PBOOST |
Offset: 0x1B0 (R/W) Power Boost control register
Definition at line 111 of file sysctl_17xx_40xx.h.
| __IO uint32_t PCLKSEL |
Offset: 0x1A8 (R/W) Peripheral Clock Selection Register
Definition at line 109 of file sysctl_17xx_40xx.h.
| __IO uint32_t PCON |
Offset: 0x0C0 (R/W) Power Control Register
Definition at line 72 of file sysctl_17xx_40xx.h.
| __IO uint32_t PCONP |
Offset: 0x0C4 (R/W) Power Control for Peripherals Register
Definition at line 73 of file sysctl_17xx_40xx.h.
| __IO uint32_t PCONP1 |
Offset: 0x0C8 (R/W) Power Control 1 for Peripherals Register
Definition at line 80 of file sysctl_17xx_40xx.h.
| __IO uint32_t PDAWAKECFG |
Offset: 0x234 Power-down states after wake-up (R/W)
Definition at line 137 of file syscon_8xx.h.
| __IO uint32_t PDRUNCFG |
Power configuration register
Offset: 0x238 Power-down configuration Register (R/W)
Definition at line 108 of file sysctl_11xx.h.
| __IO uint32_t PDSLEEPCFG |
Power down states in deep sleep mode register, not on LPC11AXX
Power down states in deep sleep mode register
Offset: 0x230 Power-down states in Deep-sleep mode (R/W)
Definition at line 106 of file sysctl_11xx.h.
| __IO uint32_t PDWAKECFG |
Power down states in wake up from deep sleep register, not on LPC11AXX
Power down states in wake up from deep sleep register
Definition at line 107 of file sysctl_11xx.h.
| __IO uint32_t PINTSEL |
GPIO pin interrupt select register 0-7, not on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX
Offset: 0x178 GPIO Pin Interrupt Select register 0
Definition at line 95 of file sysctl_11xx.h.
| __I uint32_t PIOPORCAP |
POR captured PIO status registers, index 1 on LPC1102/04
POR captured PIO status registers
Definition at line 88 of file sysctl_11xx.h.
| __IO uint32_t PIOPORCAP0 |
Offset: 0x100 POR captured PIO status 0 (R/ )
Definition at line 122 of file syscon_8xx.h.
| SYSCTL_PLL_REGS_T PLL[SYSCTL_USB_PLL+1] |
Offset: 0x080: PLL0 and PLL1
Definition at line 71 of file sysctl_17xx_40xx.h.
| __IO uint32_t PRESETCTRL |
Peripheral reset Control register
Offset: 0x004 Peripheral reset control (R/W)
Definition at line 49 of file sysctl_11xx.h.
| uint32_t RESERVED0 |
Definition at line 68 of file sysctl_17xx_40xx.h.
| uint32_t RESERVED1 |
Definition at line 54 of file sysctl_11xx.h.
| uint32_t RESERVED1[2] |
Definition at line 70 of file sysctl_17xx_40xx.h.
| uint32_t RESERVED10 |
Definition at line 89 of file sysctl_11xx.h.
| uint32_t RESERVED10[6] |
Definition at line 114 of file sysctl_17xx_40xx.h.
| uint32_t RESERVED11 |
Definition at line 92 of file sysctl_11xx.h.
| uint32_t RESERVED11[27] |
Definition at line 123 of file sysctl_17xx_40xx.h.
| __I uint32_t RESERVED12[24] |
Definition at line 98 of file sysctl_11xx.h.
| uint32_t RESERVED12[3] |
Definition at line 133 of file syscon_8xx.h.
| __I uint32_t RESERVED13 |
Definition at line 103 of file sysctl_11xx.h.
| uint32_t RESERVED13[6] |
Definition at line 135 of file syscon_8xx.h.
| __I uint32_t RESERVED14 |
Definition at line 105 of file sysctl_11xx.h.
| uint32_t RESERVED14[110] |
Definition at line 139 of file syscon_8xx.h.
| __I uint32_t RESERVED15 |
Definition at line 109 of file sysctl_11xx.h.
| __I uint32_t RESERVED16[42] |
Definition at line 149 of file sysctl_13xx.h.
| __I uint32_t RESERVED17[4] |
Definition at line 151 of file sysctl_13xx.h.
| uint32_t RESERVED2 |
Definition at line 60 of file sysctl_11xx.h.
| uint32_t RESERVED2[3] |
Definition at line 81 of file sysctl_17xx_40xx.h.
| __I uint32_t RESERVED20[110] |
Definition at line 156 of file sysctl_13xx.h.
| uint32_t RESERVED3 |
Definition at line 65 of file sysctl_11xx.h.
| uint32_t RESERVED3[10] |
Definition at line 89 of file sysctl_17xx_40xx.h.
| uint32_t RESERVED4 |
Definition at line 69 of file sysctl_11xx.h.
| uint32_t RESERVED4[1] |
Definition at line 91 of file sysctl_17xx_40xx.h.
| uint32_t RESERVED5 |
Definition at line 71 of file sysctl_11xx.h.
| uint32_t RESERVED5[4] |
Definition at line 94 of file sysctl_17xx_40xx.h.
| __I uint32_t RESERVED6[8] |
Definition at line 75 of file sysctl_11xx.h.
| uint32_t RESERVED6[18] |
Definition at line 113 of file syscon_8xx.h.
| __I uint32_t RESERVED6A |
Definition at line 98 of file sysctl_13xx.h.
| __I uint32_t RESERVED7 |
Definition at line 79 of file sysctl_11xx.h.
| __IO uint32_t RESERVED7 |
Definition at line 104 of file sysctl_17xx_40xx.h.
| uint32_t RESERVED7 |
Definition at line 117 of file syscon_8xx.h.
| __I uint32_t RESERVED8 |
Definition at line 83 of file sysctl_11xx.h.
| uint32_t RESERVED8[1] |
Definition at line 120 of file syscon_8xx.h.
| uint32_t RESERVED9 |
Definition at line 87 of file sysctl_11xx.h.
| uint32_t RESERVED9[12] |
Definition at line 110 of file sysctl_17xx_40xx.h.
| __IO uint32_t RSID |
Offset: 0x180 (R/W) Reset Source Identification Register
Definition at line 95 of file sysctl_17xx_40xx.h.
| __IO uint32_t RSTCON[2] |
Offset: 0x1CC (R/W) RESET Control0/1 Registers
Definition at line 122 of file sysctl_17xx_40xx.h.
| __IO uint32_t SCS |
Offset: 0x1A0 (R/W) System Controls and Status Register
Definition at line 103 of file sysctl_17xx_40xx.h.
| __IO uint32_t SPIFICLKSEL |
Definition at line 112 of file sysctl_17xx_40xx.h.
| __IO uint32_t SSP0CLKDIV |
SSP0 clock divider register
Definition at line 72 of file sysctl_11xx.h.
| __IO uint32_t SSP1CLKDIV |
SSP1 clock divider register, not on CHIP_LPC110X, CHIP_LPC11XXLV
SSP1 clock divider register
Definition at line 74 of file sysctl_11xx.h.
| __IO uint32_t STARTAPRP0 |
Start loigc 0 interrupt wake up enable register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX
Definition at line 99 of file sysctl_11xx.h.
| __IO uint32_t STARTERP0 |
Start loigc signal enable register 0, not on LPC11AXX
Offset: 0x204 Start logic signal enable Register 0 (R/W)
Definition at line 100 of file sysctl_11xx.h.
| __IO uint32_t STARTERP1 |
Start logic 1 interrupt wake up enable register 1, on LPC11UXX and LPC11EXX only
Offset: 0x214 Start logic signal enable Register 0 (R/W)
Definition at line 104 of file sysctl_11xx.h.
| LPC_SYSCTL_STARTST_T STARTLOGIC[2] |
Definition at line 150 of file sysctl_13xx.h.
| __IO uint32_t STARTRSRP0CLR |
Start loigc reset register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX
Definition at line 101 of file sysctl_11xx.h.
| __IO uint32_t STARTSRP0 |
Start loigc status register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX
Definition at line 102 of file sysctl_11xx.h.
| __IO uint32_t SYSAHBCLKCTRL |
System clock control register
System Clock control register
Offset: 0x080 System AHB clock control (R/W)
Definition at line 70 of file sysctl_11xx.h.
| __IO uint32_t SYSAHBCLKDIV |
System Clock divider register
Offset: 0x078 System AHB clock divider (R/W)
Definition at line 68 of file sysctl_11xx.h.
| __IO uint32_t SYSMEMREMAP |
< SYSCTL Structure System Memory remap register
Offset: 0x000 System memory remap (R/W)
Definition at line 48 of file sysctl_11xx.h.
| __IO uint32_t SYSOSCCTRL |
System Oscillator control register
Offset: 0x020 System oscillator control (R/W)
Definition at line 55 of file sysctl_11xx.h.
| __IO uint32_t SYSPLLCLKSEL |
System PLL clock source select register
Offset: 0x040 System PLL clock source select (R/W)
Definition at line 61 of file sysctl_11xx.h.
| __IO uint32_t SYSPLLCLKUEN |
System PLL clock source update enable register
Offset: 0x044 System PLL clock source update enable (R/W)
Definition at line 62 of file sysctl_11xx.h.
| __IO uint32_t SYSPLLCTRL |
System PLL control register
Offset: 0x008 System PLL control (R/W)
Definition at line 50 of file sysctl_11xx.h.
| __I uint32_t SYSPLLSTAT |
System PLL status register
Definition at line 51 of file sysctl_11xx.h.
| __IO uint32_t SYSPLLSTAT |
Offset: 0x00C System PLL status (R/W )
Definition at line 96 of file syscon_8xx.h.
| __IO uint32_t SYSRSTSTAT |
System Reset Status register
Offset: 0x030 System reset status Register (R/W )
Definition at line 59 of file sysctl_11xx.h.
| __IO uint32_t SYSTCKCAL |
System tick counter calibration register
Offset: 0x154 System tick counter calibration (R/W)
Definition at line 91 of file sysctl_11xx.h.
| __IO uint32_t SYSTICKCLKDIV |
SYSTICK clock divider register
Definition at line 106 of file sysctl_13xx.h.
| __IO uint32_t TRACECLKDIV |
ARM trace clock divider register
Definition at line 105 of file sysctl_13xx.h.
| __IO uint32_t UARTCLKDIV |
Offset: 0x094 UART clock divider (R/W)
Definition at line 112 of file syscon_8xx.h.
| __IO uint32_t UARTFRGDIV |
Offset: 0x0F0 UART fractional divider SUB(R/W)
Definition at line 118 of file syscon_8xx.h.
| __IO uint32_t UARTFRGMULT |
Offset: 0x0F4 UART fractional divider ADD(R/W)
Definition at line 119 of file syscon_8xx.h.
| __IO uint32_t USARTCLKDIV |
UART clock divider register
Definition at line 73 of file sysctl_11xx.h.
| __IO uint32_t USBCLKCTRL |
USB clock control register, LPC11UXX only
Definition at line 96 of file sysctl_11xx.h.
| __IO uint32_t USBCLKDIV |
USB clock source divider register, LPC11UXX only
USB clock source divider register, LPC134x only
Definition at line 78 of file sysctl_11xx.h.
| __IO uint32_t USBCLKSEL |
USB clock source select register, LPC11UXX only
USB clock source select register, LPC134x only
Offset: 0x108 (R/W) USB Clock Selection Register
Definition at line 76 of file sysctl_11xx.h.
| __I uint32_t USBCLKST |
USB clock status register, LPC11UXX only
Definition at line 97 of file sysctl_11xx.h.
| __IO uint32_t USBCLKUEN |
USB clock source update enable register, LPC11UXX only
USB clock source update enable register, LPC1342/43 only
Definition at line 77 of file sysctl_11xx.h.
| __IO uint32_t USBIntSt |
Offset: 0x1C0 (R/W) USB Interrupt Status Register
Definition at line 116 of file sysctl_17xx_40xx.h.
| __IO uint32_t USBPLLCLKSEL |
USB PLL clock source select register, LPC11UXX only
USB PLL clock source select register, LPC134x only
Definition at line 63 of file sysctl_11xx.h.
| __IO uint32_t USBPLLCLKUEN |
USB PLL clock source update enable register, LPC11UXX only
USB PLL clock source update enable register, LPC1342/43 only
Definition at line 64 of file sysctl_11xx.h.
| __IO uint32_t USBPLLCTRL |
USB PLL control register, LPC11UXX only
USB PLL control register, LPC134x only
Definition at line 52 of file sysctl_11xx.h.
| __I uint32_t USBPLLSTAT |
USB PLL status register, LPC11UXX only
USB PLL status register, LPC134x only
Definition at line 53 of file sysctl_11xx.h.
| __IO uint32_t WDTCLKDIV |
WDT clock divider register, some parts only
Definition at line 82 of file sysctl_11xx.h.
| __IO uint32_t WDTCLKSEL |
WDT clock source select register, some parts only
Definition at line 80 of file sysctl_11xx.h.
| __IO uint32_t WDTCLKUEN |
WDT clock source update enable register, some parts only
Definition at line 81 of file sysctl_11xx.h.
| __IO uint32_t WDTOSCCTRL |
Watchdog Oscillator control register
Offset: 0x024 Watchdog oscillator control (R/W)
Definition at line 56 of file sysctl_11xx.h.