sysctl_17xx_40xx.h

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/*
 * @brief LPC17xx/40xx System and Control driver
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef _SYSCTL_17XX_40XX_H_
#define _SYSCTL_17XX_40XX_H_

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {
 __IO uint32_t PLLCON;     
 __IO uint32_t PLLCFG;     
 __I  uint32_t PLLSTAT;     
 __O  uint32_t PLLFEED;     
 uint32_t RESERVED1[4];
} SYSCTL_PLL_REGS_T;

typedef enum {
 SYSCTL_MAIN_PLL,   
 SYSCTL_USB_PLL,    
} CHIP_SYSCTL_PLL_T;

typedef struct {
 __IO uint32_t FLASHCFG;     
 uint32_t RESERVED0[15];
 __IO uint32_t MEMMAP;     
 uint32_t RESERVED1[15];
 SYSCTL_PLL_REGS_T PLL[SYSCTL_USB_PLL + 1];  
 __IO uint32_t PCON;      
 __IO uint32_t PCONP;     
#if defined(CHIP_LPC175X_6X)
 uint32_t RESERVED2[15];
#elif defined(CHIP_LPC177X_8X)
 uint32_t RESERVED2[14];
 __IO uint32_t EMCCLKSEL;    
#else
 __IO uint32_t PCONP1;     
 uint32_t RESERVED2[13];
 __IO uint32_t EMCCLKSEL;    
#endif
 __IO uint32_t CCLKSEL;     
 __IO uint32_t USBCLKSEL;    
 __IO uint32_t CLKSRCSEL;    
 __IO uint32_t CANSLEEPCLR;    
 __IO uint32_t CANWAKEFLAGS;    
 uint32_t RESERVED3[10];
 __IO uint32_t EXTINT;     
 uint32_t RESERVED4;
 __IO uint32_t EXTMODE;     
 __IO uint32_t EXTPOLAR;     
 uint32_t RESERVED5[12];
 __IO uint32_t RSID;      
#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC407X_8X)
 uint32_t RESERVED6[7];
#elif defined(CHIP_LPC177X_8X)
 uint32_t RESERVED6;
 uint32_t MATRIXARB;
 uint32_t RESERVED6A[5];
#endif
 __IO uint32_t SCS;      
 __IO uint32_t RESERVED7;
#if defined(CHIP_LPC175X_6X)
 __IO uint32_t PCLKSEL[2];    
 uint32_t RESERVED8[4];
#else
 __IO uint32_t PCLKSEL;    
 uint32_t RESERVED9;
 __IO uint32_t PBOOST;     
 __IO uint32_t SPIFICLKSEL;
 __IO uint32_t LCD_CFG;     
 uint32_t RESERVED10;
#endif
 __IO uint32_t USBIntSt;     
 __IO uint32_t DMAREQSEL;    
 __IO uint32_t CLKOUTCFG;    
#if defined(CHIP_LPC175X_6X)
 uint32_t RESERVED11[6];
#else
 __IO uint32_t RSTCON[2];    
 uint32_t RESERVED11[2];
 __IO uint32_t EMCDLYCTL;    
 __IO uint32_t EMCCAL;     
#endif
} LPC_SYSCTL_T;

typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
 REMAP_BOOT_LOADER_MODE, 
 REMAP_USER_FLASH_MODE 
} CHIP_SYSCTL_BOOT_MODE_REMAP_T;

STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
{
 LPC_SYSCTL->MEMMAP = (uint32_t) remap;
}

#define SYSCTL_RST_POR    (1 << 0) 
#define SYSCTL_RST_EXTRST (1 << 1) 
#define SYSCTL_RST_WDT    (1 << 2) 
#define SYSCTL_RST_BOD    (1 << 3) 
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X)
#define SYSCTL_RST_SYSRST (1 << 4) 
#define SYSCTL_RST_LOCKUP (1 << 5) 
#endif

STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
{
 return LPC_SYSCTL->RSID;
}

STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
{
 LPC_SYSCTL->RSID = reset;
}

STATIC INLINE void Chip_SYSCTL_EnableBOD(void)
{
 LPC_SYSCTL->PCON |= (1 << 3);
}

STATIC INLINE void Chip_SYSCTL_DisableBOD(void)
{
 LPC_SYSCTL->PCON &= ~(1 << 3);
}

STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
{
 LPC_SYSCTL->PCON |= (1 << 4);
}

STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
{
 LPC_SYSCTL->PCON &= ~(1 << 4);
}

STATIC INLINE void Chip_SYSCTL_EnableBODRPM(void)
{
 LPC_SYSCTL->PCON |= (1 << 5);
}

STATIC INLINE void Chip_SYSCTL_DisableBODRPM(void)
{
 LPC_SYSCTL->PCON &= ~(1 << 5);
}

#define SYSCTL_PD_SMFLAG (1 << 8) 
#define SYSCTL_PD_DSFLAG (1 << 9) 
#define SYSCTL_PD_PDFLAG (1 << 10) 
#define SYSCTL_PD_DPDFLAG (1 << 11) 
uint32_t Chip_SYSCTL_GetClrSleepFlags(uint32_t flags);

#if !defined(CHIP_LPC175X_6X)

STATIC INLINE void Chip_SYSCTL_EnableBoost(void)
{
 LPC_SYSCTL->PBOOST = 0x3;
}

STATIC INLINE void Chip_SYSCTL_DisableBoost(void)
{
 LPC_SYSCTL->PBOOST = 0x0;
}

#endif

#if !defined(CHIP_LPC175X_6X)

typedef enum {
 SYSCTL_RESET_LCD,     
 SYSCTL_RESET_TIMER0,   
 SYSCTL_RESET_TIMER1,   
 SYSCTL_RESET_UART0,    
 SYSCTL_RESET_UART1,    
 SYSCTL_RESET_PWM0,    
 SYSCTL_RESET_PWM1,    
 SYSCTL_RESET_I2C0,    
 SYSCTL_RESET_UART4,    
 SYSCTL_RESET_RTC,     
 SYSCTL_RESET_SSP1,    
 SYSCTL_RESET_EMC,     
 SYSCTL_RESET_ADC,     
 SYSCTL_RESET_CAN1,    
 SYSCTL_RESET_CAN2,    
 SYSCTL_RESET_GPIO,    
 SYSCTL_RESET_SPIFI,    
 SYSCTL_RESET_MCPWM,    
 SYSCTL_RESET_QEI,     
 SYSCTL_RESET_I2C1,    
 SYSCTL_RESET_SSP2,    
 SYSCTL_RESET_SSP0,    
 SYSCTL_RESET_TIMER2,   
 SYSCTL_RESET_TIMER3,   
 SYSCTL_RESET_UART2,    
 SYSCTL_RESET_UART3,    
 SYSCTL_RESET_I2C2,    
 SYSCTL_RESET_I2S,     
 SYSCTL_RESET_PCSDC,    
 SYSCTL_RESET_GPDMA,    
 SYSCTL_RESET_ENET,    
 SYSCTL_RESET_USB,     
 SYSCTL_RESET_IOCON,    
 SYSCTL_RESET_DAC,     
 SYSCTL_RESET_CANACC,   
} CHIP_SYSCTL_RESET_T;

void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_RESET_T periph);

#endif

#ifdef __cplusplus
}
#endif

#endif /* _SYSCTL_17XX_40XX_H_ */