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sysinit_hitex_eva_18504350.c
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1 /*
2  * Copyright(C) NXP Semiconductors, 2012
3  * All rights reserved.
4  *
5  * Software that is described herein is for illustrative purposes only
6  * which provides customers with programming information regarding the
7  * LPC products. This software is supplied "AS IS" without any warranties of
8  * any kind, and NXP Semiconductors and its licensor disclaim any and
9  * all warranties, express or implied, including all implied warranties of
10  * merchantability, fitness for a particular purpose and non-infringement of
11  * intellectual property rights. NXP Semiconductors assumes no responsibility
12  * or liability for the use of the software, conveys no license or rights under any
13  * patent, copyright, mask work right, or any other intellectual property rights in
14  * or to any products. NXP Semiconductors reserves the right to make changes
15  * in the software without notification. NXP Semiconductors also makes no
16  * representation or warranty that such application will be suitable for the
17  * specified use without further testing or modification.
18  *
19  * Permission to use, copy, modify, and distribute this software and its
20  * documentation is hereby granted, under NXP Semiconductors' and its
21  * licensor's relevant copyrights in the software, without fee, provided that it
22  * is used in conjunction with NXP Semiconductors microcontrollers. This
23  * copyright, permission, and disclaimer notice must appear in all copies of
24  * this code.
25  */
26 
27 #include "board.h"
28 
56 #ifndef CORE_M0
57 /* SCR pin definitions for pin muxing */
58 typedef struct {
59  uint8_t pingrp; /* Pin group */
60  uint8_t pinnum; /* Pin number */
61  uint16_t modefunc; /* Pin mode and function for SCU */
62 } PINMUX_GRP_T;
63 
64 /* Structure for initial base clock states */
65 struct CLK_BASE_STATES {
66  CHIP_CGU_BASE_CLK_T clk; /* Base clock */
67  CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
68  bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
69  bool powerdn; /* Set to true if the base clock is initially powered down */
70 };
71 
72 /* Initial base clock states are mostly on */
73 STATIC const struct CLK_BASE_STATES InitClkStates[] = {
74  {CLK_BASE_SAFE, CLKIN_IRC, true, false},
75  {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
76  {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
77  {CLK_BASE_USB0, CLKIN_USBPLL, true, true},
78 #if defined(CHIP_LPC43XX)
79  {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
80  {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
81  {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
82 #endif
83  {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
84 #if defined(USE_RMII)
85  {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
86 #else
87  {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
88 #endif
89  {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
90  {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
91  {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
92  {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
93  {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
94  {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
95  {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
96  {CLK_BASE_OUT, CLKINPUT_PD, true, false},
97  {CLK_BASE_APLL, CLKINPUT_PD, true, false},
98  {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
99  {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false},
100 
101  /* Clocks derived from dividers */
102  {CLK_BASE_LCD, CLKIN_IDIVC, true, false},
103  {CLK_BASE_USB1, CLKIN_IDIVD, true, true}
104 };
105 
106 /* SPIFI high speed pin mode setup */
107 STATIC const PINMUX_GRP_T spifipinmuxing[] = {
108  {0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI CLK */
109  {0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D3 */
110  {0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D2 */
111  {0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D1 */
112  {0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D0 */
113  {0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)} /* SPIFI CS/SSEL */
114 };
115 
116 /* USB PLL pre-initialized setup values for 480MHz output rate */
117 static const CGU_USBAUDIO_PLL_SETUP_T usbPLLSetup = {
118  0x0000601D, /* Default control with main osc input, PLL disabled */
119  0x06167FFA, /* M-divider value for 480MHz output from 12MHz input */
120  0x00000000, /* N-divider value */
121  0x00000000 /* Not applicable for USB PLL */
122 };
123 
124 /* Audio PLL pre-initialized setup values for FIXME output rate */
125 // static const CGU_USBAUDIO_PLL_SETUP_T audioPLLSetup = {
126 // 0x0000601D, /* Default control with main osc input, PLL disabled */
127 // 0x06167FFA, /* M-divider value for FIXME output from 12MHz input */
128 // 0x00000000, /* N-divider value */
129 // 0x00000000 /* FIXME */
130 // };
131 
132 /* Setup system clocking */
133 STATIC void SystemSetupClocking(void)
134 {
135  int i;
136 
137  /* Switch main system clocking to crystal */
138  Chip_Clock_EnableCrystal();
139  Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
140 
141  /* Setup PLL for 100MHz and switch main system clocking */
142  Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
143  Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
144 
145  /* Setup PLL for maximum clock */
146  Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
147 
148  /* Setup system base clocks and initial states. This won't enable and
149  disable individual clocks, but sets up the base clock sources for
150  each individual peripheral clock. */
151  for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
152  Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
153  InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
154  }
155 
156  /* Reset and enable 32Khz oscillator */
157  LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
158  LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
159 
160  /* SPIFI pin setup is done prior to setting up system clocking */
161  for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
162  Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
163  spifipinmuxing[i].modefunc);
164  }
165 
166  /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
167  Divide rate is based on CPU speed and speed of SPI FLASH part. */
168 #if (MAX_CLOCK_FREQ > 180000000)
169  Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
170 #else
171  Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
172 #endif
173  Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
174 
175  /* Attach main PLL clock to divider C with a divider of 2 */
176  Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
177 
178  /* Setup default USB PLL state for a 480MHz output and attach */
179  Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
180 
181  /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
182  chained to make a divide by 8 function. Connect the output of
183  divider D to the USB1 base clock. */
184  Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
185  Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
186  Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
187 
188  /* Setup default audio PLL state for a FIXME output */
189  // Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME
190 }
191 
192 STATIC const PINMUX_GRP_T pinmuxing[] = {
193 #if defined(USE_RMII)
194  /* RMII pin group */
195  {0x1, 19,
196  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
197  {0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
198  {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
199  {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
200  {0x1, 17,
201  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
202  {0xC, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
203  {0x1, 16,
204  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
205  {0x1, 15,
206  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
207  {0x0, 0,
208  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
209 #else
210  /* MII pin group */
211  {0x1, 19, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC0)},
212  {0x0, 1, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC6)},
213  {0x1, 18, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC3)},
214  {0x1, 20, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC3)},
215  {0x1, 17, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3)},
216  {0xC, 1, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC3)},
217  {0x1, 16, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7)},
218  {0x1, 15, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3)},
219  {0x0, 0, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2)},
220  {0x9, 4, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC5)},
221  {0x9, 5, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC5)},
222  {0xC, 0, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3)},
223  {0x9, 0, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC5)},
224  {0x9, 1, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC5)},
225  {0x9, 6, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC5)},
226  {0x9, 3, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC5)},
227  {0x9, 2, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC5)},
228  {0xC, 8, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)},
229 #endif
230  /* External data lines D0 .. D15 */
231  {0x1, 7,
232  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
233  {0x1, 8,
234  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
235  {0x1, 9,
236  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
237  {0x1, 10,
238  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
239  {0x1, 11,
240  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
241  {0x1, 12,
242  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
243  {0x1, 13,
244  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
245  {0x1, 14,
246  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
247  {0x5, 4,
248  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
249  {0x5, 5,
250  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
251  {0x5, 6,
252  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
253  {0x5, 7,
254  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
255  {0x5, 0,
256  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
257  {0x5, 1,
258  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
259  {0x5, 2,
260  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
261  {0x5, 3,
262  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
263  /* Address lines A0 .. A23 */
264  {0x2, 9,
265  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
266  {0x2, 10,
267  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
268  {0x2, 11,
269  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
270  {0x2, 12,
271  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
272  {0x2, 13,
273  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
274  {0x1, 0,
275  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
276  {0x1, 1,
277  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
278  {0x1, 2,
279  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
280  {0x2, 8,
281  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
282  {0x2, 7,
283  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
284  {0x2, 6,
285  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
286  {0x2, 2,
287  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
288  {0x2, 1,
289  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
290  {0x2, 0,
291  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
292  {0x6, 8,
293  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
294  {0x6, 7,
295  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
296  {0xD, 16,
297  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
298  {0xD, 15,
299  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
300  {0xE, 0,
301  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
302  {0xE, 1,
303  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
304  {0xE, 2,
305  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
306  {0xE, 3,
307  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
308  {0xE, 4,
309  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
310  {0xA, 4,
311  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
312  /* EMC control signals */
313  {0x1, 4,
314  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
315  {0x6, 6,
316  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
317  {0xD, 13,
318  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
319  {0xD, 10,
320  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
321  {0x6, 9,
322  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
323  {0x1, 6,
324  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
325  {0x6, 4,
326  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
327  {0x6, 5,
328  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
329  {0x6, 11,
330  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
331  {0x6, 12,
332  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
333  {0x6, 10,
334  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
335  {0xD, 0,
336  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
337  {0xE, 13,
338  (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
339  {0x1, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
340  {0x1, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
341  {0x6, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
342  {0x1, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
343  /* LCD interface, 24bpp */
344  {0x7, 7, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
345  {0x4, 7, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC0)},
346  {0x4, 5, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
347  {0x4, 6, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
348  {0x7, 6, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
349  {0x4, 1, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
350  {0x4, 4, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
351  {0x4, 2, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
352  {0x8, 7, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
353  {0x8, 6, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
354  {0x8, 5, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
355  {0x8, 4, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
356  {0x7, 5, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
357  {0x4, 8, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
358  {0x4, 10, (SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
359  {0x4, 9, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
360  {0x8, 3, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
361  {0xB, 6, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
362  {0xB, 5, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
363  {0xB, 4, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
364  {0x7, 4, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
365  {0x7, 2, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
366  {0x7, 1, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
367  {0xB, 3, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
368  {0xB, 2, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
369  {0xB, 1, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
370  {0xB, 0, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC2)},
371  {0x7, 0, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC3)},
372  {0x4, 4, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC0)},
373  {0x7, 3, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC0)},
374  {0x4, 1, ( SCU_MODE_MODE_INACT | SCU_MODE_FUNC0)},
375  /* Board LEDs */
376  {0x8, 1, ( SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},
377  {0xE, 6, ( SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC4)}, /* GPIO7.6, green */
378  {0xE, 8, ( SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC4)}, /* GPIO7.8, blue */
379  {0xE, 5, ( SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC4)}, /* GPIO7.5, red */
380  /* Board ADC */
381  {0xF, 9, ( SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC7)},
382  /* I2S */
383  {0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
384  {0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
385  {0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
386  {0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
387  {0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
388  {0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
389  /* CCAN */
390  {0x3, 2, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC2)}, /* PE.3 CAN TD1 | SCU_MODE_FUNC1) */
391  {0x3, 1, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2)}, /* PE.2 CAN RD1 | SCU_MODE_FUNC1) */
392 };
393 
394 /* Pin clock mux values, re-used structure, value in first index is meaningless */
395 STATIC const PINMUX_GRP_T pinclockmuxing[] = {
396  {0, 0, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
397  {0, 1, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
398  {0, 2, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
399  {0, 3, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
400 };
401 
402 /* Sets up system pin muxing */
403 STATIC void SystemSetupMuxing(void)
404 {
405  int i;
406 
407  /* Setup system level pin muxing */
408  for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
409  Chip_SCU_PinMuxSet(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
410  pinmuxing[i].modefunc);
411  }
412  /* Clock pins only, group field not used */
413  for (i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) {
414  Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
415  }
416 }
417 
418 /* EMC clock delay */
419 #define CLK0_DELAY 7
420 
421 /* Hitex SDRAM timing and chip Config */
422 STATIC const IP_EMC_DYN_CONFIG_T IS42S16400_config = {
423  EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */
424  0x01, /* Command Delayed */
425  EMC_NANOSECOND(20),
426  EMC_NANOSECOND(60),
427  EMC_NANOSECOND(63),
428  EMC_CLOCK(0x05),
429  EMC_CLOCK(0x05),
430  EMC_CLOCK(0x04),
431  EMC_NANOSECOND(63),
432  EMC_NANOSECOND(63),
433  EMC_NANOSECOND(63),
434  EMC_NANOSECOND(14),
435  EMC_CLOCK(0x02),
436  {
437  {
438  EMC_ADDRESS_DYCS0, /* Hitex Board uses DYCS0 for SDRAM */
439  3, /* RAS */
440 
441  EMC_DYN_MODE_WBMODE_PROGRAMMED |
442  EMC_DYN_MODE_OPMODE_STANDARD |
443  EMC_DYN_MODE_CAS_3 |
444  EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
445  EMC_DYN_MODE_BURST_LEN_8,
446 
447  EMC_DYN_CONFIG_DATA_BUS_16 |
448  EMC_DYN_CONFIG_LPSDRAM |
449  EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS |
450  EMC_DYN_CONFIG_MD_SDRAM
451  },
452  {0, 0, 0, 0},
453  {0, 0, 0, 0},
454  {0, 0, 0, 0}
455  }
456 };
457 
458 /* Hitex Static RAM timing and chip Config */
459 STATIC const IP_EMC_STATIC_CONFIG_T IS62WV25616_config = {
460  2,
461  EMC_STATIC_CONFIG_MEM_WIDTH_16 |
462  EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
463  EMC_STATIC_CONFIG_BLS_HIGH /* |
464  EMC_CONFIG_BUFFER_ENABLE*/,
465 
466  EMC_NANOSECOND(0),
467  EMC_NANOSECOND(30),
468  EMC_NANOSECOND(90),
469  EMC_NANOSECOND(55),
470  EMC_NANOSECOND(55),
471  EMC_NANOSECOND(55)
472 };
473 
474 /* Hitex NorFlash timing and chip Config */
475 STATIC const IP_EMC_STATIC_CONFIG_T SST39VF320_config = {
476  0,
477  EMC_STATIC_CONFIG_MEM_WIDTH_16 |
478  EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
479  EMC_STATIC_CONFIG_BLS_HIGH /* |
480  EMC_CONFIG_BUFFER_ENABLE*/,
481 
482  EMC_NANOSECOND(0),
483  EMC_NANOSECOND(35),
484  EMC_NANOSECOND(70),
485  EMC_NANOSECOND(70),
486  EMC_NANOSECOND(40),
487  EMC_CLOCK(4)
488 };
489 
490 /* Setup external memories */
491 STATIC void SystemSetupMemory(void)
492 {
493  /* Setup EMC Delays */
494  /* Move all clock delays together */
495  LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
496 
497  /* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking)
498  and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies
499  less than 120MHz, a divider of 1 or 2 is ok. */
500  Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
501  LPC_CREG->CREG6 |= (1 << 16);
502 
503  /* Enable EMC clock */
504  Chip_Clock_Enable(CLK_MX_EMC);
505 
506  /* Init EMC Controller -Enable-LE mode */
507  Chip_EMC_Init(1, 0);
508  /* Init EMC Dynamic Controller */
509  Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &IS42S16400_config);
510  /* Init EMC Static Controller CS2 */
511  Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &IS62WV25616_config);
512  /* Init EMC Static Controller CS0 */
513  Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &SST39VF320_config);
514 
515  /* Enable Buffer for External Flash */
516  LPC_EMC->STATICCONFIG0 |= 1 << 19;
517 }
518 
519 #endif
520 
528 void SystemInit(void)
529 {
530 #if defined(CORE_M3) || defined(CORE_M4)
531  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
532 
533 #if defined(__IAR_SYSTEMS_ICC__)
534  extern void *__vector_table;
535 
536  *pSCB_VTOR = (unsigned int) &__vector_table;
537 #elif defined(__CODE_RED)
538  extern void *g_pfnVectors;
539 
540  *pSCB_VTOR = (unsigned int) &g_pfnVectors;
541 #elif defined(__ARMCC_VERSION)
542  extern void *__Vectors;
543 
544  *pSCB_VTOR = (unsigned int) &__Vectors;
545 #endif
546 
547 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
548  fpuInit();
549 #endif
550 
551  /* Setup system clocking and memory. This is done early to allow the
552  application and tools to clear memory and use scatter loading to
553  external memory. */
554  SystemSetupClocking();
555  SystemSetupMuxing();
556  SystemSetupMemory();
557 #endif
558 }
559