usart_004.h

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/*
 * @brief UART/USART Registers and control functions
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */

#ifndef __USART_004_H_
#define __USART_004_H_

#include "sys_config.h"
#include "cmsis.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {       
 union {
  __IO uint32_t  DLL;     
  __O  uint32_t  THR;     
  __I  uint32_t  RBR;     
 };

 union {
  __IO uint32_t IER;     
  __IO uint32_t DLM;     
 };

 union {
  __O  uint32_t FCR;     
  __I  uint32_t IIR;     
 };

 __IO uint32_t LCR;      
 __IO uint32_t MCR;      
 __I  uint32_t LSR;      
 __I  uint32_t MSR;      
 __IO uint32_t SCR;      
 __IO uint32_t ACR;      
 __IO uint32_t ICR;      
 __IO uint32_t FDR;      
 __IO uint32_t OSR;      
 __IO uint32_t TER1;      
 uint32_t  RESERVED0[3];
 __IO uint32_t HDEN;      
 __I  uint32_t RESERVED1[1];
 __IO uint32_t SCICTRL;     
 __IO uint32_t RS485CTRL;    
 __IO uint32_t RS485ADRMATCH;   
 __IO uint32_t RS485DLY;     
 union {
  __IO uint32_t SYNCCTRL;    
  __I  uint32_t FIFOLVL;    
 };

 __IO uint32_t TER2;      
} IP_USART_001_T;

#define UART_RBR_MASKBIT    (0xFF)  
void IP_UART_Init(IP_USART_001_T *pUART);

STATIC INLINE void IP_UART_DeInit(IP_USART_001_T *pUART) {}

STATIC INLINE void IP_UART_SendByte(IP_USART_001_T *pUART, const uint8_t data)
{
 pUART->THR = (uint32_t) data;
}

STATIC INLINE uint8_t IP_UART_ReadByte(IP_USART_001_T *pUART)
{
 return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
}

#define UART_IER_RBRINT      (1 << 0) 
#define UART_IER_THREINT     (1 << 1) 
#define UART_IER_RLSINT      (1 << 2) 
#define UART_IER_MSINT       (1 << 3) 
#define UART_IER_CTSINT      (1 << 7) 
#define UART_IER_ABEOINT     (1 << 8) 
#define UART_IER_ABTOINT     (1 << 9) 
#define UART_IER_BITMASK     (0x307)  
#define UART1_IER_BITMASK    (0x38F)  
STATIC INLINE void IP_UART_IntEnable(IP_USART_001_T *pUART, uint32_t intMask)
{
 pUART->IER |= intMask;
}

STATIC INLINE void IP_UART_IntDisable(IP_USART_001_T *pUART, uint32_t intMask)
{
 pUART->IER &= ~intMask;
}

#define UART_IIR_INTSTAT_PEND   (1 << 0) 
#define UART_IIR_INTID_RLS      (3 << 1) 
#define UART_IIR_INTID_RDA      (2 << 1) 
#define UART_IIR_INTID_CTI      (6 << 1) 
#define UART_IIR_INTID_THRE     (1 << 1) 
#define UART_IIR_INTID_MODEM    (0 << 1) 
#define UART_IIR_INTID_MASK     (7 << 1) 
#define UART_IIR_FIFO_EN        (3 << 6) 
#define UART_IIR_ABEO_INT       (1 << 8) 
#define UART_IIR_ABTO_INT       (1 << 9) 
#define UART_IIR_BITMASK        (0x3CF)  
STATIC INLINE uint32_t IP_UART_ReadIntIDReg(IP_USART_001_T *pUART)
{
 return pUART->IIR;
}

#define UART_FCR_FIFO_EN        (1 << 0) 
#define UART_FCR_RX_RS          (1 << 1) 
#define UART_FCR_TX_RS          (1 << 2) 
#define UART_FCR_DMAMODE_SEL    (1 << 3) 
#define UART_FCR_TRG_LEV0       (0)   
#define UART_FCR_TRG_LEV1       (1 << 6) 
#define UART_FCR_TRG_LEV2       (2 << 6) 
#define UART_FCR_TRG_LEV3       (3 << 6) 
#define UART_FCR_BITMASK        (0xCF)  
#define UART_TX_FIFO_SIZE       (16)

STATIC INLINE void IP_UART_SetupFIFOS(IP_USART_001_T *pUART, uint32_t fcr)
{
 pUART->FCR = fcr;
}

#define UART_LCR_WLEN5          (0)    
#define UART_LCR_WLEN6          (1 << 0)  
#define UART_LCR_WLEN7          (2 << 0)  
#define UART_LCR_WLEN8          (3 << 0)  
#define UART_LCR_SBS_1BIT       (0 << 2)  
#define UART_LCR_SBS_2BIT       (1 << 2)  
#define UART_LCR_PARITY_EN      (1 << 3)  
#define UART_LCR_PARITY_DIS     (0 << 3)  
#define UART_LCR_PARITY_ODD     (0)    
#define UART_LCR_PARITY_EVEN    (1 << 4)  
#define UART_LCR_PARITY_F_1     (2 << 4)  
#define UART_LCR_PARITY_F_0     (3 << 4)  
#define UART_LCR_BREAK_EN       (1 << 6)  
#define UART_LCR_DLAB_EN        (1 << 7)  
#define UART_LCR_BITMASK        (0xFF)   
STATIC INLINE void IP_UART_SetMode(IP_USART_001_T *pUART, uint32_t lcr)
{
 pUART->LCR = lcr;
}

STATIC INLINE void IP_UART_EnableDivisorAccess(IP_USART_001_T *pUART)
{
 pUART->LCR |= UART_LCR_DLAB_EN;
}

STATIC INLINE void IP_UART_DisableDivisorAccess(IP_USART_001_T *pUART)
{
 pUART->LCR &= ~UART_LCR_DLAB_EN;
}

#define UART_DLL_MASKBIT    (0xFF)  
#define UART_DLM_MASKBIT    (0xFF)  
STATIC INLINE void IP_UART_SetDivisorLatches(IP_USART_001_T *pUART, uint8_t dll, uint8_t dlm)
{
 pUART->DLL = (uint32_t) dll;
 pUART->DLM = (uint32_t) dlm;
}

#define UART_MCR_DTR_CTRL       (1 << 0)  
#define UART_MCR_RTS_CTRL       (1 << 1)  
#define UART_MCR_LOOPB_EN       (1 << 4)  
#define UART_MCR_AUTO_RTS_EN    (1 << 6)  
#define UART_MCR_AUTO_CTS_EN    (1 << 7)  
#define UART_MCR_BITMASK        (0x0F3)   
STATIC INLINE uint32_t IP_UART_ReadModemControl(IP_USART_001_T *pUART)
{
 return pUART->MCR;
}

STATIC INLINE void IP_UART_SetModemControl(IP_USART_001_T *pUART, uint32_t mcr)
{
 pUART->MCR |= mcr;
}

STATIC INLINE void IP_UART_ClearModemControl(IP_USART_001_T *pUART, uint32_t mcr)
{
 pUART->MCR &= ~mcr;
}

#define UART_LSR_RDR        (1 << 0) 
#define UART_LSR_OE         (1 << 1) 
#define UART_LSR_PE         (1 << 2) 
#define UART_LSR_FE         (1 << 3) 
#define UART_LSR_BI         (1 << 4) 
#define UART_LSR_THRE       (1 << 5) 
#define UART_LSR_TEMT       (1 << 6) 
#define UART_LSR_RXFE       (1 << 7) 
#define UART_LSR_BITMASK    (0xFF)  
STATIC INLINE uint32_t IP_UART_ReadLineStatus(IP_USART_001_T *pUART)
{
 return pUART->LSR;
}

#define UART_MSR_DELTA_CTS      (1 << 0) 
#define UART_MSR_DELTA_DSR      (1 << 1) 
#define UART_MSR_LO2HI_RI       (1 << 2) 
#define UART_MSR_DELTA_DCD      (1 << 3) 
#define UART_MSR_CTS            (1 << 4) 
#define UART_MSR_DSR            (1 << 5) 
#define UART_MSR_RI             (1 << 6) 
#define UART_MSR_DCD            (1 << 7) 
#define UART_MSR_BITMASK        (0xFF)  
STATIC INLINE uint32_t IP_UART_ReadModemStatus(IP_USART_001_T *pUART)
{
 return pUART->MSR;
}

STATIC INLINE void IP_UART_SetScratch(IP_USART_001_T *pUART, uint8_t data)
{
 pUART->SCR = (uint32_t) data;
}

STATIC INLINE uint8_t IP_UART_ReadScratch(IP_USART_001_T *pUART)
{
 return (uint8_t) (pUART->SCR & 0xFF);
}

#define UART_ACR_START              (1 << 0) 
#define UART_ACR_MODE               (1 << 1) 
#define UART_ACR_AUTO_RESTART       (1 << 2) 
#define UART_ACR_ABEOINT_CLR        (1 << 8) 
#define UART_ACR_ABTOINT_CLR        (1 << 9) 
#define UART_ACR_BITMASK            (0x307)  
STATIC INLINE void IP_UART_SetAutoBaudReg(IP_USART_001_T *pUART, uint32_t acr)
{
 pUART->ACR |= acr;
}

STATIC INLINE void IP_UART_ClearAutoBaudReg(IP_USART_001_T *pUART, uint32_t acr)
{
 pUART->ACR &= ~acr;
}

STATIC INLINE void IP_UART_TXEnable(IP_USART_001_T *pUART)
{
 pUART->TER1 = (1 << 7);
}

STATIC INLINE void IP_UART_TXDisable(IP_USART_001_T *pUART)
{
 pUART->TER1 = 0;
}

#define UART_RS485CTRL_NMM_EN       (1 << 0) 
#define UART_RS485CTRL_RX_DIS       (1 << 1) 
#define UART_RS485CTRL_AADEN        (1 << 2) 
#define UART_RS485CTRL_SEL_DTR      (1 << 3) 
#define UART_RS485CTRL_DCTRL_EN     (1 << 4) 
#define UART_RS485CTRL_OINV_1       (1 << 5) 
#define UART_RS485CTRL_BITMASK      (0x3F)  
STATIC INLINE void IP_UART_SetRS485Flags(IP_USART_001_T *pUART, uint32_t ctrl)
{
 pUART->RS485CTRL |= ctrl;
}

STATIC INLINE void IP_UART_ClearRS485Flags(IP_USART_001_T *pUART, uint32_t ctrl)
{
 pUART->RS485CTRL &= ~ctrl;
}

STATIC INLINE void IP_UART_SetRS485Addr(IP_USART_001_T *pUART, uint8_t addr)
{
 pUART->RS485ADRMATCH = (uint32_t) addr;
}

STATIC INLINE uint8_t IP_UART_GetRS485Addr(IP_USART_001_T *pUART)
{
 return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
}

STATIC INLINE void IP_UART_SetRS485Delay(IP_USART_001_T *pUART, uint8_t dly)
{
 pUART->RS485DLY = (uint32_t) dly;
}

STATIC INLINE uint8_t IP_UART_GetRS485Delay(IP_USART_001_T *pUART)
{
 return (uint8_t) (pUART->RS485DLY & 0xFF);
}

uint32_t IP_UART_SetBaud(IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk);

#if 0 // FIXME
// FIXME
// FDR handled at chip layer
// OSR not ready
// TER1 not ready
// HDEN handled at chip layer
// SCICTRL handled at chip layer
// TER2 handled at chip layer

#define UART_ICR_IRDAEN         ((uint32_t) (1 << 0))   
#define UART_ICR_IRDAINV        ((uint32_t) (1 << 1))   
#define UART_ICR_FIXPULSE_EN    ((uint32_t) (1 << 2))   
#define UART_ICR_PULSEDIV(n)    ((uint32_t) ((n & 0x07) << 3)) 
#define UART_ICR_BITMASK        ((uint32_t) (0x3F))    
#define UART_HDEN_HDEN          ((uint32_t) (1 << 0))   
#define UART_SCICTRL_SCIEN      ((uint32_t) (1 << 0))    
#define UART_SCICTRL_NACKDIS    ((uint32_t) (1 << 1))    
#define UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2))    
#define UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5))  
#define UART_SCICTRL_GUARDTIME(n)   ((uint32_t) ((n & 0xFF) << 8)) 
#define UART_FDR_DIVADDVAL(n)   ((uint32_t) (n & 0x0F))   
#define UART_FDR_MULVAL(n)      ((uint32_t) ((n << 4) & 0xF0)) 
#define UART_FDR_BITMASK        ((uint32_t) (0xFF))    
#define UART_TER1_TXEN          ((uint8_t) (1 << 7))  
#define UART_TER1_BITMASK       ((uint8_t) (0x80))   
#define UART_TER2_TXEN      ((uint8_t) (1 << 0))   
#define UART_TER2_BITMASK   ((uint8_t) (0x01))    
#define UART_SYNCCTRL_SYNC      ((uint32_t) (1 << 0))   
#define UART_SYNCCTRL_CSRC_MASTER   ((uint32_t) (1 << 1))  
#define UART_SYNCCTRL_FES       ((uint32_t) (1 << 2))   
#define UART_SYNCCTRL_TSBYPASS  ((uint32_t) (1 << 3))   
#define UART_SYNCCTRL_CSCEN     ((uint32_t) (1 << 4))   
#define UART_SYNCCTRL_STARTSTOPDISABLE  ((uint32_t) (1 << 5)) 
#define UART_SYNCCTRL_CCCLR     ((uint32_t) (1 << 6))   
#endif

#ifdef __cplusplus
}
#endif

#endif /* __USART_004_H_ */