M'Board Notes 23 Feb 18 0 Adv Ckts quote arrived. Purch quan 15, 5 day turnaround. 22 Feb 18 1 Adv Ckts quote 21 Feb 18 1 Dimension a hole to board edge 1 Update drill chart 1 Renumber 1 Power Trace Widths 20 Feb 18 1 ICs with pads w/ via'S -- tent/filled U12 U14 U15 U16 U34 U39 U40 U41 XR20M1280 QFN50P500X500X100-33T380X380N U28 USB2514B 36_QFN U31 LTC3226EUD 16_QFN U37 ISL4221E 16_QFN 14 Feb 18 1 Use NCP Hi Side Sw for 3V3_ISO sequencing 13 Feb 18 ! Silego SLG59M1448V PDF page 5: To ensure glitch-free power-up under all conditions, apply VDD first, followed by VD after VDD exceeds 1 V. Then allow VD to reach 90% of its max value before toggling the ON pin from Low-to-High. Likewise, power-down in reverse order. NCP45524, -5 PDF page 10: The NCP4552x devices will function with any power sequence, but the output turn-on delay performance may vary from what is specified. To achieve the specified performance, there are two recommended power sequences: 1) VCC ? VIN ? VEN 2) VIN ? VCC ? VEN 1 Incorporate ECOs since design review into the PCB. 1 Change interconnect connector to next larger size, add grounds 12 Feb 18 The big problem I see with this design is that the enable for the fet can be pulled high by the 5v supply while the 3.3v_4100 supply is still below he threshold voltage. If you power the switch from 3.3v you might be able to get away with the circuit as drawn since the reset chip powers up at 1v while the switch powers up at 3v. But you’re counting on some specific power up behavior which might be temperature dependent. Remember the power up for the 3v3_4100 rail won’t happen until 140ms or more after 5v goes on. I would approach this design using a reset chip with a push pull output such as an LM809, TPS3839, or STM809. A pull down on the output will provide the bias necessary to keep the fet disabled when 3.3v is below 1v. The data sheets identify 100k as a reasonable value for this pull down so the quiescent current won’t be too bad. And I’d power the reset part and switch from 3.3v_4100. --> TPS3839 has lowest current draw, but on pg 12 a troubling note appears: 8.4.3 Below Power-On Reset (VDD < V(POR) When the voltage on VDD is lower than the power-on reset voltage (V(POR)), the RESET output is undefined. Do not rely on the RESET output for proper device function under this condition. Therefore, going with the STM809T and a 100k pulldown. 10 Feb 18 1 You might look on page 11 of the ts-4100 schematic. The 3.3V 2A regulator design features an enable based on the ST1001S voltage supervisor I mentioned in my last email. The power supply sequencing is a bit more fully featured than what we need, since are actually cascaded behind this enable, but it is good for illustrating the basic design. 1 http://www.st.com/content/ccc/resource/technical/document/datasheet/5b/13/c4/98/4a/b3/41/72/CD00017849.pdf/files/CD00017849.pdf/jcr:content/translations/en.CD00017849.pdf This might be a better option than the maxim part. It has s guaranteed turn on delay. It’s the same part used on the 4100 for supply sequencing 9 Feb 18 1 SLG59M1448 == 2.5a switch from the slg59 line. 3000 available at digikey 1 The attached schematic illustratess how I would approach supervising the 3V3_ISO and keeping it off until 3V3_4100 comes up. As I said in the meeting, I would switch it locally on the CPU board, rather than turning the 3V3_ISO converter on and off. There are various N channel FET switches which can accomplish this - I copied one similar to what the TS-4100 uses for switching power to the ethernet phy's, but there are others. The SLG59M1618 can handle up to 2.0A of current with 19 mohms of on resistance, and it has controllable slew. The MAX6377 supervisor chip has an open drain output which is pulled low until the monitored voltage rail exceeds the threshold voltage (3.08V, others can be purchased). As long as the monitored voltage is below the threshold voltage, the switch is disabled. Again, by keeping all the rail supervision and sequencing on the CPU board, I think we'll simplify working with the CPU board, and avoid having enable lines or 3V3_4100 power rails going back and forth. -> SLG59M1618 not in stock. Using NCP45525-H. Adding PFON signal to HiSideSw EN 8 Feb 18 Preliminary Final Design Review 1 Enet AC signal terminations ... remove if not found in a reference design Left in place, note added: LABEL: DO NOT LOAD ON BILL OF MATERIALS 1 Route the LED connections to the jacks 1 Add pull ups to all PDIS_UART to 3V3_4100 Added 330k to all PDIS_UART signals on TS4100 sheet 1 SPI UARTS: add pull up resistors on PDIS_UART signals Added 330k: Uart 0 to GPIO4 Uart 1 Uart 2 Uart 3 Uart 4 Uart 5 Uart 6 to GPIO4 Uart 7 to GPIO4 1 ISL4221E: revisit the Enable/Disable pins Once more, with Feeling 1 Ensure that MIC2026 can be controlled by 3V3 level signals Datasheet pg 3: Ven low to hi max 2.4V Ven hi to lo 1.45V CN1-4 on TS-8550 datasheet pg 9 Same - Same on CpuBoard sch 1 FRWV: recheck Hi Side Sw Logic FET Q7 goes away, R182 goes away, R183 ? Add 100k pull down to U18-2 EN input R11 Bleed resistor goes away 1 FRWV: Soft Start cap goes on SR to Gnd, milliseconds duration, Calc's on page 10 of NCP45525-H datasheet Sketched in a 10uF cap (6.3V 0805 X7R) which should give a slew rate of 2.4 to 3.8 Volts / Sec 1 MM2-T: Recheck Tx In and Rx Out pin assignments 1 MM2-T: Recheck the handshake lines 1 MM2-T: Q7 goes away on SPI_UART_PDIS_N; pull-down resistor value TBD Prolly R183 1.0M goes away too Maybe U18 becomes the " -L " version ( Not In Stock ) Experiment to check "EN" pin on Hi Side Switch 1 GNSS_5_CLICK becomes 3V3_ISO power 1 Add note "External Interrupt" to signal GNSS_5_EXI label 1 ADD HIGH SIDE SWITCH ON CPU BOARD to control 3V3_ISO based on signals 3V3_4100 and CPON 1 SBD Warrior Mounting Holes should be floating Indeed they are; verified on pcb 1 Native UARTs: add pull up resistors on PDIS_UART signals 1 Confirm any changes to the schematic from the Prototype board RTS_B signals not connected thru a jumper to either RTS_B or GPS_SERIAL_TX Pullup resistors to 3V3+4100 on PDIS_UARTx lines ( shown on TS4100 sheet ) Removed redundant ISO_GND Test Point Removed HI Side Switches for 3V3, +12V_ISO and 5V2A 1 XTAL Osc for UARTS now 1.8432 MHz 1 Clock buffer is " way overkill " ... maybe go back to the original buffer Clock buffer is once again: 74HC7014D 1 SPI UARTS: check pin 32 -- OK to float 47k pullup on pin 32 shown to +VCC_CORE on schematic XR20M1280 Evaluation Board Emailed tech support 12 Feb 2018 1310 hours Response: no pullups required 12 Feb 2018 1515 x maybe use XTAL2 to feed downstream UARTS ? An upstream UART failure would incapacitate all downstream UARTs 1 Supercap Sheet: K 1 TS4100 Sheet: prolly K 1 VN100: bring 3V3 up to the " Firmware Update Header " Added 3V3_4100 to pin 5 J18 1 Parosci: Change over to a Native UART. Maybe. Put this on the Bottom of The Stack. Parosci now on Native UART5 ( was Serial 4), only TX and RX are utilized This was the closest Native UART to the Parosci on the PCB SPI_UART_7 is now connected to Serial 4 6 Feb 18 1 SPI - UART OSC: I would Recommend a 1.8432Mhz crystal. This gives us a top rate of over 1mbps. A tcxo is a bit Overkill for a baud rate generator anything rated to 100ppm should be ok. Scanning various ones at digikey we should also be able drop the power to 3ma or so. 1 Compare current drawn using individual xtals on SPI Uarts vs Single fanned out xtal as now drawn Its a wash 5 Feb 18 1 FREEWAVE: SPI_UART_PDIS_N is not active low, it's active high to turn the switch on. This itself is not a problem (just confusing nomenclature) but the other PDIS_ lines are active low. So now we would need to have a different software driver or driver options from the other SPI UARTs to run this. Better to have them all work the same way. So maybe replace the switch with an NCP45525-L. -L HiSideSw not available ... using an N-FET to invert enable signal 1 Update JTAG connnector J23 Samtec FTSH-105-01-F-DV-K DGK SAM8796-ND 1 SPI UART Osc Clock buffer prolly 2 slow ...replace w 2 ea LMV112 1 SPI UART termination resistors prolly not needed 1 Feb 18 Technologic systems schematic design review: Here are Engineering's comments about the baseboard schematic: 1) The RTC battery has no series resistor nor a safety diode. UL will make you redesign it, if you ever try to get a UL certification. 1 Add 1k series resistor as per TS-8551 schematic 2) I am not sure why R142 thru R149 are on the schematic? 1 Ethernet Ports AC signal termination not needed ? Left the resistors and caps on the schematic, will annotate as Do Not Load on the Bill of Materials 3) I am not sure what is sourcing the 3V3_ISO power rail, but it is important that it be gated off when the 3V3_4100 power rail is less than 2.8V. This could be accomplished with a precision reset IC such as the STM1001SWX or an analog comparator. 1 Recheck each IC directly connected to the TS4100 1 Recheck the 3V3_4100 power budget 19 Jan 18 1 Interconnect ESD protection 1 Gnd test points at 4 corners s/b TP_040 TP 929 1006 1007 974 1 Fiducials for pick and place 0 Renumber reference designations 1 Spoke width: .008" ( Global Dynamic Shape Paramaters ... Thermal relief connects ) 1 Silk Board Name MBARI LOGO Copyright Part number s/n box 1 Mount holes connected to Earth Ground ( chassis ) 0 PCB thickness, cu wt Ethernet / usb impedances based on .063" 1 oz Cu 1 Layers identified in clear " window " area 1 Silk screen " tick " marks every 10 pins on CPU signals connector 1 Fuses at Interface Connector 1 Add test point for 3V3_4100 at upper left corner 10 Jan 18 1 Diff pairs for ethernet lines 100 Ohms ? Match lengths within 100 mils ? Issues: enet traces s/b on top layer RJ45s s/b at bottom edge of board Moved two serial assemblies and the two RJ45s 1 Diff pairs for USB lines 90 Ohms ( +/- 10% ) 1 SPI Clk and Data s/b 50 ohm lines, identical lengths 4 Jan 18 1 Also, looking over the schematic, the jumper selectable RTS/GPS TX is only implemented on one port. Lets go ahead and route GPS_TX to each header so we can reconfigure RTS as needed to be GPS data. 1 The GNSS5 board has an external interrupt pin on it (labelled EXI, its on pin 16 of the header). This is an input pin which we might want to utilize for timing applications in the future. Can you route this pin to a connector? Maybe the expansion connector if there is a pin we can repurpose from a ground? thanks Re-assigned Interconnect pin 3 from ISO_GND to GNSS_5_EXI, added a test point. 21 Dec 17 1 PAROSCI NEEDS ISOLATOR AND RS232 LINE DRIVER Just Rx and Tx ... ck Analog Devices 1 Smaller test points 1 J344 look for 1 mm connector Went with 50 mil ribbon connector 17 Dec 17 1 Clean up header of unused CPU signals x Remove unnecessary test points on TS4100 sheet Kept them all, even sprinkled in a few more. 1 GPS MODULE, USE SERIAL CONNECTION, NOT I2C Deleted Ser IF 11 11 Dec 17 Motherboard splits into two boards PowerBoardRev1 Switched Power ( 24V 12V 5V 3V3 ) DC/DC Converters 1 PPS Triggers PIC Drop Wt Env Sense Trig / 1PPS on a single 8 pin connector Thru Hole DC/DC converter (smaller) Low voltage switches now use TPS25944A CpuBoardRev1 Isolated Serial I/O CPU Supercap FREEWAVE GPS Receiver Ethernet USB Parosci and DC/DC converter ( TDR2-1212WISM ) Board Outline 6.375 X 5.525 Interconnect to PowerBoard NEED: GPS device info Iridium device connections info SBD9603B01 1 TS8551 CPU JTAG sheet 3 of 10 1 TS8551 Host USB Power Switch sheet 4 of 10 1 TS8551 USB OTG Micro AB sheet 4 of 10 x TS8551 Host USB sheet 4 of 10 NEED TO RECONCILE TS-8550 VS TS-8551 x TS8551 Rechargable Lithium Battery sheet 4 of 10 1 TS8551 LEDS sheet 6 of 10 1 TS8551 Jumpers sheet 7 of 10 1 sIGNAL PDIS_UART5 NEEDS CPU CONNECTION 1 ETHERNET LEDS SIGNALS NEED PHYSICAL LEDS 1 ADD IN FOOTPRINTS FOR TS SUPERCAP COMPONENTS ... LABEL DO NOT LOAD TS8551 sheet 7 of 10 14 Dec 17 Made request for transistor part numbers 1 Route SD_BOOT# and BOOT_MODE_0 to appropriate switches to control boot behavior 1 Confirm CN1/19 function (U-BOOT# in TS-8551 schematic) and implement proper jumpering for boot to u-boot 1 Set up dedicated kearfott serial port with isolated GPS serial TX on handshake line and TX/RX for control SER0_NATIVE_UART_IF_1 1 JTAG_FPGA CONNECTIONS GO WHERE ? Route to " cpu unused pin " header 1 I2C4_SCL / SDA GO WHERE ? header 1 ECSPI3_MISO / MOSI / SCL GO WHERE ? header 1 Buffer the PPS line 1 Interconnect bulk caps on voltages added 47u caps to each 1 TS8551 Boot Switch sheet 8 of 10 1 TS8551 NO_SCAP_CHRG# U-BOOT# RED_LED# GREEN_LED# sheet 10 of 10 1 Kearfott serial connection ( implemented on all serial circuits ) RTS into Isolator gets fed from a three terminal jumper to allow input choice: Native serial RTS ---or--- GPS Transmit ( for Kearfott, this is a secondary recieve input for NMEA strings ) 1 Schematic change: I2c expanders to enable all power switching ( 24 12 5 3V3 ) 0 Plated thru holes for good ground connection 1 Interconnect between Pwr and CPU OldMotherBoard ( backup ) A problem to watch out for with named nets ... cut and paste can make unintentional copper connections ! 27 Nov 17 1 Change console J285 to 4 pin harwin 1 Change J287 to 14 pin harwin 1 Change RJ45s to 8 pin harwins 25 Nov 17 X Several boards, stacked - Bus In, Bus Out, Switched Bus - DC/DC Converters - CPU, Isolated Serial - RF, GPS, Novatechs - Acoustic Comms 22 Nov 17 1 K3 pinout ? 1 uChip XLP changes per Erik's red line 0 Check that all stby batts get measured by ADCs 14 Nov 17 1 Use the BOM from Eval kit for ADUM5412 1 Update VN100 footprint 1 Review VN100 Hardware Integration Manual 0 Diodes D107 D109 D113 D117 D121, fp " wll_2_1 " are quite small " 0201 " Change to DGK: 732-9950-1-ND, fp " diode_sma " 1 Serial/Power schematic has issues: 1 Cap fp " C_1812 " is wrong 1 Isolated gnd plane should extend all the way from under the adum to the line driver. Right now there's a funny split between the plane under the adum and the isolated plane under the connector and sp330 1 Lines s/b swapped between ADUM and SP330 per red - line sch RX/CTS ( Corrected pin placement on the schematic part ) 1 ADUM bypassing needs attention. See pg 26 of the 5412 doc pdf. 1 Hi Side Sw wiring changes per red - line sch 1 Silkscreen issue in test point labeling. 1 Bleed resistors s/b tied between bleed and Vout, not bleed and gnd. 1 Isolated gnd plane islands s/b tied together 1 Silkscreens for Harwins causing confusion top/bottom1 0 Update HARWIN connector footprints 1 Update HIROSE connector 1 Update TRACO_TMR_1SM 12 Oct 17 1 Sw Bus fuses too big 5 Amp Slow Blow 507-1194-1-ND 1206 smt 1 Lose the center mt hole on the pcb MT7 1 Purchase pcb mount Harwin connectors x Search out harwin website for availability of female connectors HRH is accomplishing this task 10 OCT 17 0 PC104 STYLE CONNECTOR OF UNUSED GPIO TO MEZZANINE BOARD HEIGHT ISSUE 0 PLACE FREEWAVE ON BOTTOM OF M'BOARD 0 SMA/MCX ADAPTER MOUNT L OR U BRACKET 0 CLUSTER RF COMPONENTS INTO ONE AREA FOR COAX DRESSING 2 Oct 17 1 Iso Pwr switches and connectors part of comms sch control HS switches from spare GPIO 1 SER 0 R 1 SER 1 R 1 SER 2 R 1 SER 3 R 1 SER 4 R 1 SER 5 R 1 SER 6 R 1 SER 7 R 1 SER 8 R 1 SER 9 R 1 SER 10 R 1 SER 11 R 1 DELETE ISO_SW_PWR SHEETS AFTERWARDS 1 4 pin signal mix tek pwr connectors A BUS B BUS GND 1 Shield 2 Bus Gnd 3 Bus Gnd 4 24V 0 Tether In connector uniquely keyed 0 Power schottky diode at low current power supply Not on M'Board 29 Sept 17 1 Looking over this schematic. Not clear why the PIC is powered by 3V3_4100 net, and not the 3V3_TRIG_FILTERED net. The way things are set up the trigger pulses are buffered by a 74HC7014 which is powered by 3V3_TRIG_FILTERED, so the trigger won't work until that net is powered. I suggest we power this circuit from 3V3_TRIG_FILTERED. 27 Sept 17 1 Combine Trig Outputs onto ONE connector for each fanout 1 Combine 1PPS Outputs onto ONE connector for each fanout 1 RS232 Xorb on Trig Fanout is wrong ... need 12V Xorbs 26 Sept 17 1 Lets use this for the SBD warrior: https://www.digikey.com/product-detail/en/conec/164A17309X/626-1803-ND/3838205 Match the pinouts to whats in the SBD warrior datasheet. There are some digital I/O and analog inputs that we can think about routing !! Board thickness shall be 0.090" 0 Call Harwin: re minimum buy policy 0 Call Indtek re: buying policy ( them vs us ) 1 Comms connector: M80-5101442 1 Iso_Sw_Pwr: M80-5101042 Harwin J-Tek connectors 04 06 08 10 12 14 20 26 34 42 50 1 Go thru all the sheets, change to available connectors as needed. 25 Sept 17 1 Comms IF circuit: eliminate TTL Comms Smaller connector Eliminate buffers Re-do "cable chart" I think we are going to have a problem with the isolated serial interface when operating in TTL mode. The transceiver chip will still be driving the R2OUT and R1OUT lines, so the buffers won't be able to switch these lines. Similarly, when operating in 232/485 mode, the buffers will be driving the lines against the transceiver chip, with similar problems. We might be able to add some tri-state buffers to alleviate this, or some form of multiplexer. Maybe the TTL requirement is something we eliminate from the general isolated design, and have a few dedicated ports (like for the SBD warrior) where needed. 21 Sept 17 0 Keep connectors on extended edges, save room in the middle for daughter board 1 Console comms on a DB9 if possible 1 J2 J15 J17 need to be Harwin J-Tek connectors --> J2 done 20 Sept 17 1 Attempt to bring in board outline dxf X Possibly change Trig uCntlr to 20 pin PIC 16 LF 1828 same as low pwr shutdown PIC ---> WILL BE A PIC 18 19 Sept 17 1 Layout a Serial IF " room " of one channel 1 No more serial comms Daughter board ? Ten serial IF ports w/ ISO power on M'Board 1 1PPS buffer chip needs to be powered by 3V3_4100 1 Need a connector for Parosci comms and power ---> SPI UART 7 0 Mount an SMA adapter to MMCX ( or whatever ) for the Freewave 0 Daughter board for ACST modem, etc, set up dimensions to be " inside " rows of connectors 0 Stack up of 6 or 8 layers. Plane layers Isolation areas. Cross section to HRH ---> Proposal: Top Components and Signal routing In 1 Split Ground Cu Pours In 2 Signal routing In 3 Signal routing In 4 Signal routing In 5 Signal routing In 6 Split Power Cu Pours Bot Components and Signal routing 18 Sept 17 1 UARTS must be powered by 3V3_4100 1 Freewave iface dio buffer chips must be powered by 3V3-4100 1 Console RS232 now non-isolated use any 3V3 rated chip 1 Env Sensing must be powered by 3V3_4100 1 Trig uCntlr must be powered by 3V3_4100 1 Trig uCntlr comms now I2c 1 VN100 now powered by 3V3_1400 ? also bring 3V3_4100 to upper boards stack -thru connector (TBD ) 13 Sept 17 ? New serial comms DAUGHTER, switched bus and switched power board Horizontal mounting -HRH to do schematic and pcb layout of "daughter" board -DRT to do motherboard -HRH to define stack-thru connectors 1 All vertical mount jackscrew Harwins ? Lose the 2 added SPI Uarts = 6 SPI Uarts only --> First verify spreadsheet "M_BOARD_SERIAL_CHANNELS.xls" ? SPI Uarts remain on the motherboard ? Power switching control ... use an I2c I/O expander instead of GPIO lines 12 Sept 17 X Separate comms boards 4 boards of 3 channels each 90 degree Harwin Jack Screw connectors 1 TTL lines need transient prot 1 Add a harwin connector ot all unsued comms pins on VN100 1 VN100 now SPI bus comms 1 Add HV cap to comms channel 1 Smaller prot diodes: TPD2e007. "dck" footprint. ** THE NEWEST COMMS_IF IS IN SCH: ONE_COMMS_IF ? Update to M'board 11 Sept 17 1 Top Priority ... layout one comms if channel for sizing info 1 " NEW " homogenous part for drivers: NC7W16 8 sEPT 17 1 Freewave sch: RX and TX are swapped 1 Connect up CD and DTR lines from UART to Freewave 1 VN100 sch: RX and TX are swapped ? maybe use SPI Bus directly instead of a SPI UART ? 1 XLP pic ... find Erik's email re: I2c pull down resistors --> it wasn't an email; it was a schematic sketch. 0 Why not run I2c Isolator directly off 3V3_BUS ( lose the LDO regulator ) 1 ADC issue: SBD_BATT is relative to ISO_GND _NOT_ BUS_GND Same issue with NOVATECH_BATT_PLUSO --> add an I2c ADC on the ISO_GND side, connect to ISO_SDA and ISO_SCL 1 3V3_ISO DC/DC converter sequencing issue re: TS4100: 3V3_ISO _MUST_ come up after 3V3_4100 _AND_ 3V3_ISO _MUST_ shut down before 3V3_4100 --> Using opto isolator to Enable/Shutdown 3V3 converter with Supercap signal PFON 1 Tally up 3V3_4100 current draws 1 SUPERCAP_V_OUT should only run the TS4100: Go thru everywhere it's used and see if 5V_SUPERCAP_FEED can be used instead --CONSOLE_RS232 1 I2c Isolator on uCHIP_XLP s/b 3V3_4100 not 5V 1 Don't pull up I2c lines on the ENV_SENSING sheet 7 Sept 17 1 3V3 ISO _MUST_ come up after TS4100 3V3 1 Change serial port connectors to 20 pin version, lose the 2 pin header 1 Make the serial port connectors Surface Mount 20 pin version, be sure to use the " staples " for connector strain relief 1 Change the Isolated Switched power connectors to Surface Mount 12 pin Harwins w " staples " for connector strain relief HRH starting to consider secondary board for comms 1 Change PDIS signals (comms1 etc) to match UARTn Numbers 2 Sept 17 1 Re: hs sw for 3v3/5v/12v rails NCP45524 Given the size of these maybe we can have a switch bank for each connector. It is hot 1 Serial Comms prot diodes: 1655-1702-1-ND 0 PDIS_CONSOLE How to implement ? Prolly DON'T implement ! 31 Aug 17 1 Route Freewave to UART2 1 FREEWAVE PDIS SIGNAL 1 Route Trigger comms to I2c or SPI UART SPI UART 7 1 Route SBD_WARRIOR to SPI UART_0 1 Route VN100 to UART3/UART_A Implement VN100 shut down 1 Add another SPI UART Actually, added two. 6 and 7. 0 Freewave and SBD_WARRIOR make sure room for Connector 0 Keep Power and Comms connectors close on PCB 1 BOARD SIZE 7.75" x 7.75" All on One Board ? Really ? 27 Aug 17 ? Hierarchical ? 0 IF more non-interrupt GPIO is needed, look for an extender on the NXP website 22 AUG 17 REMAINING ISSUES: 1 All GPIO needs to be powered by 3V3 from the TS4100 -Isolated GPIO 1 3V3 from the Traco powers ONLY stuff which is not on TS4100 GPIO 1 All components should be Surface Mount if at all possible 1 TS-4100 PIN MAPPING Signals which utilize interrupts cannot go thru FPGA Everything else should go thru FPGA 0 Is there any problem with piping the OSC line into two UARTs directly? 0 Possible OR ing FET at Tether Input 1 Unused GPIOs from CN1 and CN2 ... bring out to a header 1 DOUBLE CHECK ETHERNET PINOUTS 1 Comms_1 thru Comms_9 will be a copy of Comms_0 with signal names changed AFTER final approval of Comms_0 1 Isolation for SWITCHED BUS Hi Side Switches 1 Use a TPS3613-01 in place of schottky diodes for XLP PIC pwr 16 Aug 17 1 AHRS I am leaning towards the vectornav vn100: http://www.vectornav.com/products/vn-100 If it can fit on the motherboard then we can put a footprint down for the SMD version. Otherwise I was thinking about trying to install the rugged version in the dvl case 11 Aug 17 1 CN2/39 and CN2/79 should be connected to each other so that the CAM DIO signals on CN2 are at 3.3V levels 1 MM2 s/b TTL i'face. 1 Lets assume an MM2-T module. 5V input power. Outputs are 3.3V TTL, inputs can probably be 3.3V TTL although the manual describes these as 5V TTL. Header definition and footprint are given in the integration guide. 1 RTS/CTS MM2 handshake 1 Add a dedicated connection on the motherboard to connect to the freewave MM2 module. It can go to one of the SPI UARTS. The MM2 connection doesnt need to be isolated Comms_11 renamed to Comms_Frwv_MM2 1 I'd like to add TTL RTS and CTS to the connector, though, and lose two of the ground connections. So its still an 18pin connector, but two fewer grounds. 1 buffer the RTS and CTS signals. 10 Aug 17 1 Change serial comms connector to 18 pin Harwin 8 Aug 17 1 You don't need a second level shifter. RTS_3V3_0 routes to DE_IO (U154/pin 19). In RS232 mode, pin 19 drives the T2 Out (U154/Pin 7). Thus, J233/Pin 6 is RS232 TX and J233/Pin 5 is RTS. CTS routes from J233/pin 4 to U154/Pin 17. In RS232 mode, this is the R1 Input. U154/Pin 8 then routes to U346/pin 20. The key thing is that the pin functions on J233 change depending on whether RS232, RS422, or RS485 are selected. Here is what I get for the pinout of J233: Pin 1 All GPIO needs to be powered by 3V3 from the TS4100 1 3V3 from the Traco powers ONLY stuff which is not on TS4100 GPIO 1 All components should be Surface Mount if at all possible 1 Bus FWD and Tailcone Fuse s/b 15A *** CHANGED TETHER FUSE TO 15A ALSO *** 1 USBL connect to a Switched Bus Connector 5A 1 Gulpers fuse 5A F7115CT-ND ( COPY F8 ) 1 All Sw Bus Fuses 5A F7115CT-ND 1 Comms channels implement RTS / CTS use ADUM5412 isolator p/s 1 Fix the " different filters" issue on 5V dc/dc outputs 1 12V instruments dc/dc doesnt go anywhere Renamed bus and off sheet connector to +12V_ISO 1 10V dc/dc output rtn ties to iso gnd on pg 23 1 Burn Wire output needs to go to a connector 1 pressure switch needs a connector ? uChip XLP add buffer and linear 1 Novatech/SBD Warrior backup batts gnd s/b ISO GND 1 Console RS232 ... USE ADUM3251 instead of MAX3250 1 Switched Bus use lower current HS Switches for all except TailCone 5A H/S SWITCHES ... VN750PSTR-E 5.5-36V 6A 60mOhm 8-SOIC 1 Switched Bus ... where do the i_mon nets go ? THEY BE GONE ( DELETED ) 1 Motherboard power connectors Use 4 signal connector for sense lines on TETHER 952-1247-ND HARWIN_MIX_TEK_2N4 1 RF jacks not needed on m/board 1 Env Sensing ... pull up I2C lines w 3.3k to 3v3 ? Trig Fanout ... 4 pin 2x2 Harwin connections 1 DC/DC 3V3 ... L19 check for saturation why different output pi filters ? 1 Stby Pwr Acomms 24V USBL use Bus Power connect to Sw Bus Connector 3 Auv 17 1 Look for burnwire relay with lower drop out voltage --> Relay ( DGK PB385-ND ) release voltage is 1.2VDC 2 Aug 17 1 Can Energy Sales put connectors on battery packs ? SHO' 'NUFF ! 1 Aug 17 1 TS-4100 PIN MAPPING Signals which utilize interrupts cannot go thru FPGA Everything else should go thru FPGA 1 Use a native port for Freewave comms channel Implement RTS / CTS handshaking Specification changed to SPI UART on 11 Aug 17 1 Add transorbs on comms external world pins 1 Add a ferrite bead on comms isolator dc power input 31 July 17 1 HRH: This might also be worth considering: http://www.ti.com/lit/ds/symlink/isow7841.pdf 29 July 17 HRH Notes: 1 The prime power for the novatechs doesn't seem to connect to the 10V power converter. The SBD should really run off 12V, rather than 10V. This can be accomplished by using a DPDT relay, and using one pole to switch novatech power, and the other to switch SBD power. 1 Novatech and SBD power need to end up on connectors somewhere. ETR Notes: general: 1 can we rename SUPERCAP_V_IN to 5V_MAIN or something less confusing? Changed name to 5V_SUPERCAP_FEED page 2: 1 R249 probably superfluous, only used in ref design so you don't short the enable pin when the enable jumper is set to off 1 PFON, CAPGOOD and RST pins need pullup if connected to microcontroller (can possibly use internal mc pin pullup) page 3: 1 check logic of 3.3/5V selection switch by R440 and R349. The ADUM can only generate 5V when it is powerded by 5V but currently it's only powered by the 3.3V line. It could make sense to run the ADUM off 5V all the time and maybe when it is coded to 3.3V the ADUM left side becomes 3.3V too (needs to be checked) 1 instead of forwarding the SHTDN signal just to the SP330, can't we just turn off the ADUM to save the power for it too? 1 the ADUM6401CRIZ does not have a soft start feature, it seems that it can draw 300-500mA on startup. We have multiple of those so not sure if we have an issue overloading the 3.3V line. Another reason to hook them up to the shutdown circuit of the UART so they don't get all started in parallel page 15: 1 is there a reason that the output filters for the two 5V 2A DCDCs is different? ? the TRACO DCDC sink up to 10mA through the on/off pin when off, seems high page 17: 1 Novatec DCDC has no output filter. Intentional? page 18: 1 is burn wire current limited by wire itself? 1 especially at high currents when we burn the wire the battery voltage might sink below the 19V required for triggering the relay even though there is still 1/3 or more of battery cap left --> Relay ( DGK PB385-ND ) release voltage is 1.2VDC page 19: 1 capacitors c382 and C381 might be on wrong side of diode or not necessary at all 1 scaled_bus should be hooked up to I2C voltage meter as discussed: run PIC off 3.3V bus if vehicle is on 1 I wouldn't run the voltage dividers for the scaled_* measuring inputs so close to the max voltage the meter can read (e.g. scaled_24v_bat is 2.95V for 24V) With new batteries the voltage will be higher than 24V and we also want to see if the bus has over voltage. Maybe set it so that we still have at least 25% headroom (24V -> 2.5V) page 20: 1 remove term resistors/caps. They were only for testing but weren't necessary even with the wonky layout I did on the proto board 0 Is there any problem with piping the OSC line into two UARTs directly? page 23: 1 typo at ETH_RXM (close to R38) which might mean that nets are not connected where is the AC termination network coming from? page 24: 1 same thing as above with relay (k3): I'd use one which has a lower voltage to get triggered otherwise it might not trigger while the battery still has enough energy left RELAYS: K1 ACOMMS BACKUP coil from ELEC+ ( bus pwr ) K2 DROP WEIGHT coil from ELEC+ --or-- 24V Backup Batt *** relay drop out issue *** K3 Novatech/SBD coil from 10V_ISO ( derived from bus pwr ) K4 Latching Relay Novatech SBD On-Off control K5 Latching Relay Acomms pwr On-Off Control QUESTION: Is the signal DROP_WT_PIC_CMD constantly on or does it pulse ? 1 enable_novatech should not just come from the TS4100 but also triggered by the mechanical switch page 25: 1 check if SN74HC14 is fast enough to switch 15MHz. Looking at the datasheet the transition time could be around 50ns for 3.3V but the period for 15MHz is 67ns Replaced with 74HC7015D,118 page 33: 1 check the numbers for the dual amps, it seems that for most of them the A side is a different IC than then B side (e.g. U292A and U291B) 1 for the dual amps it seems like GND (pin 3) is connected to Vdd at pin 3 of the harwin connector ? maybe use different gender harwin for trigger in and trigger out ?? 1PPS FANOUT PAGE ??? page 34: 1 check numbering on multi amps U303 and U302, they seem to be the same IC 1 change communication of PIC from RS232 to I2C page 35: 1 more dual amp mixups (U305 vs. U306, U308 vs U309) page 36: 1 where is DVL_ON_N and 5V_ISO_ON_N going? Be careful putting 36V on that if it powers the gate of a FET page 38: 1 CN2:26 could get connected to GND ? typo at CPU Reset? (3V3_ISOL); would mean the net is not connected page 39: 1 if the reed switch on J4 is open, MAGNET_EN_ACOMMS is floating J4 no mo' ;-) Enabled by TS4100; one reed switch enables Loc Aids $ Acomms 28 July 17 1 Yeah, I was thinking there should be ADUMs which have an enable feature. This would solve both problems. We could also put a bigger cap in front of them to help out with the inrush. Erik 1 WE might consider another part from Analog Devices: http://www.analog.com/media/en/technical-documentation/data-sheets/ADuM5410-5411-5412.pdf This isolator is part of the same family, but has an integral enable switch. Curiously, the inrush note in the datasheet for the adum6401 is missing. Hmm. 1 ADuM5411BRSZ This is an almost identical part to the one I sent a note about earlier, but its available at digikey. 27 July 17 1 ADUMs have huge initial current draw ... possibly use a HS Sw or PFET 26 July 17 0 Possible OR ing FET at Tether Input 25 July 17 1 Pin 36 of CN1 is the v_bat pin. It needs to be hooked up to the 3.3V coin cell. 1 In the schematic, make the TS4100 a PART, not TWO CONNECTORS CN1 1/100 CN2 1/100 1 Duplicated circuit: 3V3 ps sheet Trig MicroCntlr 1 Add a coin cell for TS4100 Real Time Clock 1 One common connector for back up batteries 8S1P ( 2x 4S1P in a pack ) 1. 6V Strobe 2. 6V RDF 3. 12V SBD 4. 24V Acst Modem / Burnwire CONNECTOR TBD. Energy Sales says they will attach connectors. MicroFit3 WM10677-ND 24 July 2017 1 I have been playing around with MVC internal layouts of the standby batteries, and thinking about different battery configurations. My thought at this point is to have a common battery pack design made up of 8 C cells, wired as 2 4S1P packs. So, each pack would have 4 leads coming out (plus and minus for each 4S1P group). We can then mount 4 of these groups, 1 on each side of the MVC motherboard. For the novatech beacons, this would provide a seperate 4S1P group for the strobe and for the RDF. For the SBD beacon, we would wire the two 4S1P groups in series for an 8S1P pack (12V) to run the SBD warrior. For the acoustic modem & burnwire, we would wire the two remaining packs in series, for a 16S1P configuration. What I like about this is it gets us to a common battery configuration for all the backup supplies in the MVC, so we don't have to stock seperate packs. 1 Coin Cell powers XLP Pic thru Reed Switch 1 Novatech relay coil power should be coming from a prime power rail NOT a backup battery 1 SBD is running too close to it's 7V brownout Voltage 1 SEPARATE BATTS RUN NOVATECH / SBD Run 1 connector to 9V Stby Battery Run 1 connector to 12V Stby Battery "K3" ... 1 relay contact runs Novatech ... 1 relay contact runs SBD Warrior 1 ONE reed switch enables everything Turns on/off burn wire thru software 1 A Serial Connector powers the SBD Warrior 0 Unused GPIOs from CN1 and CN2 ... bring out to a header 1 Ethernet LEDs on jacks get run thru zero Ohm resistors so they can be disabled 1 DOUBLE CHECK ETHERNET PINOUTS 1 Not clear why there is a reed switch for the acoustic modem power when there is also a latching relay. Putting the magnet in just allows the GPIO to turn on the relay, it won't turn it off. It would probably make more sense to have one reed switch that the XLP monitors, and it turns off the latching relays if it sees the switch go to the correct state. Latching relays: STBY PWR Novatech SBD Warrior ? It would be really nice to have the big 24V standby battery run the SBD warrior as well as the acoustic modem in the event of power failure. The problem is that the SBD warrier needs to be powered from the isolated ground rail since it is connected thru the antenna splitter to the DG16. Hmm. Maybe you have a better idea. A good alternative would be to switch to C cell packs instead of D's, or have two D cell packs maybe. I will think it over. 1 Remember to modify the supercap_vin used to power the coils - this rail is on the isolated side, and the other side of the coil is switched to bus ground. Also, both coils are tied together. 1 I am not seeing where the power switching is derived from. Does it come from the TS4100 or the XLP? 1 There is an opto-isolated signal for turning on the 10V power called EN_10V which looks like it goes to nowhere 1 I don't think the relay circuit is going to work. Both the close coil and the open coil are being switched at the same time 1 Sniff out net ELEC+ Added another current sense circuit on PWR Connectors sheet to monitor ELEC+ current 1 Next to the last sheet of the PDF document you sent me. Supercap_V_IN is going to the plus side of the latching relay, and the other side is tied to bus ground. It should be tied to ISO ground Changed all the relay control components to isolated reference 1 Change J99, J100, J101, J102, J103, J104, J105, J106 to M80-5T10205M1-02-331-00-000 (vertical entry, mixed signal, 2 20A power contacts and 2 24AWG signal contacts). These are 2mm pitch high power mixed signal high current (20A/contact for the power contact). They are about the same dimensions as the datamate L-Tek. They save a lot of board space over the positronics connectors. I recommend using one of the signal pins for the shield termination, with the other pin connected to the power ground (for use with a serial port). 1 Add another 6 bus power connectors. This provides a total of 12 bus power connections for devices, 1 for the tether coming in, and 1 for the unswitched bus going out. 1 Add another 6 isolated power connectors. Currently, we have J107, J108, J109, J110, J111, and J112. Add another 6 for a total of 12. We might also consider makeing these connectors female rather than male to avoid any confusion. 1 Change the serial I/O connector from a 12 pin to a 14 pin harwin with the TTL level serial present on this connector. This gets rid of a connector, and makes the serial I/O connector different from the isolated power connector. 1 The above changes will provide 2 raw bus connections for tether and bus out, 12 raw bus power connections for auxiliary uses, 12 serial I/O connections, and 12 isolated power connections for auxiliary. These can be arranged on the board as shown in the attached figure. We can make strain reliefs which mount into the board so we can minimize connector strain on the harwins. We can switch these if board space and I/O allow, or just have them unswitched and fused. 1 Its probably a good idea to keep all of the connectors on this board vertical entry. The ethernet jacks in the current BOM are horizontal entry. Looking things over at digikey, it looks like we'll have to use a single port magjack for this application. Its probably worth it though. 1 Ethernet 1 USB 1 Why not use a 14 pin connector for the serial I/O, with TTL as well as RS232 and RS485, on the connector? Save on having a second connector X We should use a different gender of connector for the bus in and bus out connectors 20 July 2017 1 Check for transient suppression on isolated side of serial port chips 8kV / 15kV PROTECTION 1 Supercap power fail line to main cpu PFD pull up Cap good What's up w the diode + PFI pin ... use a pullup to Vout 1 EN_CHG_CMD should come from the TS-4100 * Really * ? How would the TS-4100 get started without supercap power ? How about having the uChip XLP enable the supercap circuit ? ? Stacked power connectors to all boards 1 Power Board ... DC/DC Burnwire Switching 2 CPU Logic Board Comms Freewave SBD Warrior 3 Timing/Trig maybe 4 "Mounting Board" Acoustic XCVR GPS etc 1 Backup Batteries location TBD X TRY ONE BOARD LAYOUT FIRST 1 STBY batt packs connectors go to main board 1 Fuse SMB_Block to each power output connector 0 NOT ON BOTTOM OF Board X GENDERIZE Power In / Power Out ( Bus/Tailcone) 13 July 2017 1 Choose SM vs TH Harwins pwr/comms 1 Strobe / RDF connections 1 Pressure switch connection 1 Drop Wt connections 27 June 17 1 Update DC/DC Converter sheets w/ Traco's 1 DC_DC_10V TEN 20-2421WIN 1 DC_DC_12V TEN 30-2412WIN 1 TDR 2-2412WISM 1 DC_DC_5V THD 10-2411WIN 1 DC_DC_3V3 Recom 78C3.3_1.0 1 TRIG_1PPS TMR 1-2411SM 1 Trig_1PPS schematic sheets 22 June 17 1 Add a 3V3 ADC on the "Bus" side Reads Batts and Bus 1 Pressure goes on the ISO side 1 Temp/Humid goes on the ISO side 1 I2c isolator "Bus" side gets powered by 3V3_BUS ( not 3V_LITHIUM ) 1 Review PIC Output - FET - DC/DC Enable lines 1 What do the PIC pins do at RESET ? Pins are outputs initially. Advice: use pull down resistors ( 1M pull downs on each p/s enable FET ) 1 Look at Harwin Hi-rel Hi-Current connectors 10 amps per contact ( too wimpy ) 21 June 17 1 Use same form factor board as MAUV P/S PCB ( not smaller ) 1 Larger mounting screws 1 Connector scheme row of power connectors row of comms connectors each penetrator fans out to pwr and comms connector 20 June 17 1 Traco 6-side shield case should not be connected to an electrical pin 1 DVL/Kearfott power 22 AWG ... Harwin OK 1 Tailcone power ... use Positronic Mix Density 1 Provide a " shield pin " on all Switched Bus connectors 12 June 2017 1 Switched power: change connector to 12-pin 1,2 12V 3,4 3V3 5,6 5V Delete the jumper pins Add a secondary 12-pin connector on each set of three switch arrays Also on power switching 1 6 each "bus" switches: 1 DVL/Kearfott 1 TailCone 1 Gulpers 1 Three Spares 1 USB use MIC2026 protection on USB connectors Do "feed-thru" design on protection diodes 1 Power Board: check out Calex again Same height DC/DC converters, mount on board bottom w heat sinks Thru pins OK, Surface Mount preferred Look for low wattage DC/DC w enable line for Parosci 2 June 2017 Power Arch BD: 1 missing AV Track Acst Beacon Pwr ( 24V ?? ) 1 missing DVL Kearfott Pwr 1 missing TailCone Pwr Comms: 1 Add TTL capability to each channel 1 Be able to disconnect XCVR Freewave MM2-T 5V PWR 3V3 TTL DG14 RS232 AHRS 3DM-GX4-45 PWR 3V3 TO 5V / 5.2 TO 36V RS232 SBD Warrior PWR 7-28V 3V3 TTL 1 On DC/DC converters, see if a FET is needed for the enable lines 1 DC/DC converters: see about using same vendor for all converters surface mount if possible TRC Elex Cosel ( SM ) converters 5v 12v TI 10v ( TH ) Mechanical Arch: TRY A SINGLE BOARD ARCH FIRST ! ? Power Board with switching ? Logic Board ? I/O Board ? Standard Edge Connectors Possibly Samtec DWM micro board stacker 0.050" pitch ( cat pg 197 ) Mates w SLM or SMS ( pg 202 ) 0 All signals from the 2x 100 pin TS4100 connectors 1 Maybe same form factor as MAUV Pwr Board ( circular board not needed ) 1 Separate RESET Line to CPU ... reed switch w/ debounce ckt CPU 1 route console TxRx to a connector 1 route USB to real USB connectors 1 I2C 1 LEDs 0 Unused GPIOs to a header for Future Use SPI Uarts 1 One clock module feeds all Baud Rate Generators Drop Weight Cmd 1 Shall go to a separate PIC ... not the TS4100 ... use the XLP PIC 1 Reed Switch Control to TS4100 ... 2 inputs Trigger and 1 PPS should be isolated 1 Trigger to Bus and DVL / Kearfott 1 1 PPS Bus and Kearfott share same ground 1 Non-isolated ( ? ) 1 PPS to TS4100 1 Two spare channels for Future Use Trigger and 1 PPS 1 Rise time ~ 250 nSec OK 1 Use a latching relay in place of the TPS2491 1 Map the GPIO usage 1 Look for a single Low Voltage High Side switch that works from 3V3 to 12V On Semi NCP45560IMNTWG-H 0.5V to 13.5V 24A 3.2 mOhms 12-VFDFN w/pad On Semi FPF2700MX 2.8V to 36V 2A 88.0 mOhms 8-SOIC