S:/ALLEGRO_PARAMETERS/SixLayerTechFile.tcf physical 16.6 drawing opFlags dictionaryExtensions crossSection electricalConstraints physicalConstraints spacingConstraints sameNetSpacingConstraints properties mil 4 DRAWING_EXTENTS 34000.0000,22000.0000 DRAWING_LOWER_LEFT -8611.9685,-8611.9685 MAX_XTALK_VMODE OFF MAX_PEAK_XTALK_VMODE OFF IMPEDANCE_RULE_VMODE OFF STUB_LENGTH_VMODE OFF MAX_VIA_COUNT_VMODE OFF MATCH_VIA_COUNT_VMODE OFF MAX_EXPOSED_LENGTH_VMODE OFF MAX_PARALLEL_VMODE OFF LAYERSET_GROUP_VMODE OFF PROPAGATION_DELAY_MIN_VMODE OFF TOTAL_ETCH_LENGTH_MIN_VMODE OFF RELATIVE_PROPAGATION_DELAY_VMODE OFF DIFFP_PRIMARY_GAP_VMODE OFF MIN_LINE_WIDTH_VMODE ON MAX_LINE_WIDTH_VMODE ON DRC_UNROUTED_MINPROP N DRC_UNROUTED_RELPROP N PIN_DELAY_PVF 1.524e+08 m/s PIN_DELAY_ENABLED N VIA_Z_PVF 1.524e+08 m/s VIA_Z_ENABLED N SAME_NET_XTALK_ENABLED N ALLOW_ON_ETCH_SUBCLASS_VMODE ON TS_ALLOWED_VMODE ON MIN_BVIA_STAGGER_VMODE ON MAX_BVIA_STAGGER_VMODE OFF PAD_PAD_DIRECT_CONNECT_VMODE OFF THRUPIN_TO_THRUPIN_SPACING_VMODE ON THRUPIN_TO_SMDPIN_SPACING_VMODE ON TESTPIN_TO_THRUPIN_SPACING_VMODE ON THRUPIN_TO_THRUVIA_SPACING_VMODE ON TESTVIA_TO_THRUPIN_SPACING_VMODE ON BBV_TO_THRUPIN_SPACING_VMODE ON THRUPIN_TO_BONDPAD_SPACING_VMODE ON LINE_TO_THRUPIN_SPACING_VMODE ON THRUPIN_TO_SHAPE_SPACING_VMODE ON SMDPIN_TO_SMDPIN_SPACING_VMODE ON SMDPIN_TO_TESTPIN_SPACING_VMODE ON SMDPIN_TO_THRUVIA_SPACING_VMODE ON SMDPIN_TO_TESTVIA_SPACING_VMODE ON BBV_TO_SMDPIN_SPACING_VMODE ON SMDPIN_TO_BONDPAD_SPACING_VMODE ON LINE_TO_SMDPIN_SPACING_VMODE ON SHAPE_TO_SMDPIN_SPACING_VMODE ON TESTPIN_TO_TESTPIN_SPACING_VMODE ON TESTPIN_TO_THRUVIA_SPACING_VMODE ON TESTPIN_TO_TESTVIA_SPACING_VMODE ON BBV_TO_TESTPIN_SPACING_VMODE ON BONDPAD_TO_TESTPIN_SPACING_VMODE ON LINE_TO_TESTPIN_SPACING_VMODE ON SHAPE_TO_TESTPIN_SPACING_VMODE ON THRUVIA_TO_THRUVIA_SPACING_VMODE ON TESTVIA_TO_THRUVIA_SPACING_VMODE ON BBV_TO_THRUVIA_SPACING_VMODE ON BONDPAD_TO_THRUVIA_SPACING_VMODE ON LINE_TO_THRUVIA_SPACING_VMODE ON SHAPE_TO_THRUVIA_SPACING_VMODE ON TESTVIA_TO_TESTVIA_SPACING_VMODE ON BBV_TO_TESTVIA_SPACING_VMODE ON BONDPAD_TO_TESTVIA_SPACING_VMODE ON LINE_TO_TESTVIA_SPACING_VMODE ON SHAPE_TO_TESTVIA_SPACING_VMODE ON BBV_TO_BBV_SPACING_VMODE ON BONDPAD_TO_BBV_SPACING_VMODE ON BBV_TO_LINE_SPACING_VMODE ON BBV_TO_SHAPE_SPACING_VMODE ON BONDPAD_TO_BONDPAD_SPACING_VMODE ON BONDPAD_TO_LINE_SPACING_VMODE ON BONDPAD_TO_SHAPE_SPACING_VMODE ON LINE_TO_LINE_SPACING_VMODE ON LINE_TO_SHAPE_SPACING_VMODE ON SHAPE_TO_SHAPE_SPACING_VMODE ON HOLE_TO_PIN_SPACING_VMODE OFF HOLE_TO_VIA_SPACING_VMODE OFF HOLE_TO_LINE_SPACING_VMODE OFF HOLE_TO_SHAPE_SPACING_VMODE OFF HOLE_TO_HOLE_SPACING_VMODE OFF MVIA_TO_MVIA_SPACING_VMODE ON MVIA_TO_THRUPIN_SPACING_VMODE ON MVIA_TO_SMDPIN_SPACING_VMODE ON MVIA_TO_THRUVIA_SPACING_VMODE ON MVIA_TO_BBV_SPACING_VMODE ON MVIA_TO_LINE_SPACING_VMODE ON MVIA_TO_SHAPE_SPACING_VMODE ON MVIA_TO_TESTPIN_SPACING_VMODE ON MVIA_TO_TESTVIA_SPACING_VMODE ON BONDPAD_TO_MVIA_SPACING_VMODE ON MIN_BVIA_GAP_VMODE ON SN_THRUPIN_TO_THRUPIN_SPACING_VMODE OFF SN_THRUPIN_TO_SMDPIN_SPACING_VMODE OFF SN_TESTPIN_TO_THRUPIN_SPACING_VMODE OFF SN_THRUPIN_TO_THRUVIA_SPACING_VMODE OFF SN_TESTVIA_TO_THRUPIN_SPACING_VMODE OFF SN_BBV_TO_THRUPIN_SPACING_VMODE OFF SN_THRUPIN_TO_BONDPAD_SPACING_VMODE OFF SN_LINE_TO_THRUPIN_SPACING_VMODE OFF SN_THRUPIN_TO_SHAPE_SPACING_VMODE OFF SN_SMDPIN_TO_SMDPIN_SPACING_VMODE OFF SN_SMDPIN_TO_TESTPIN_SPACING_VMODE OFF SN_SMDPIN_TO_THRUVIA_SPACING_VMODE OFF SN_SMDPIN_TO_TESTVIA_SPACING_VMODE OFF SN_BBV_TO_SMDPIN_SPACING_VMODE OFF SN_SMDPIN_TO_BONDPAD_SPACING_VMODE OFF SN_LINE_TO_SMDPIN_SPACING_VMODE OFF SN_SHAPE_TO_SMDPIN_SPACING_VMODE OFF SN_TESTPIN_TO_TESTPIN_SPACING_VMODE OFF SN_TESTPIN_TO_THRUVIA_SPACING_VMODE OFF SN_TESTPIN_TO_TESTVIA_SPACING_VMODE OFF SN_BBV_TO_TESTPIN_SPACING_VMODE OFF SN_BONDPAD_TO_TESTPIN_SPACING_VMODE OFF SN_LINE_TO_TESTPIN_SPACING_VMODE OFF SN_SHAPE_TO_TESTPIN_SPACING_VMODE OFF SN_THRUVIA_TO_THRUVIA_SPACING_VMODE OFF SN_TESTVIA_TO_THRUVIA_SPACING_VMODE OFF SN_BBV_TO_THRUVIA_SPACING_VMODE OFF SN_BONDPAD_TO_THRUVIA_SPACING_VMODE OFF SN_LINE_TO_THRUVIA_SPACING_VMODE OFF SN_SHAPE_TO_THRUVIA_SPACING_VMODE OFF SN_TESTVIA_TO_TESTVIA_SPACING_VMODE OFF SN_BBV_TO_TESTVIA_SPACING_VMODE OFF SN_BONDPAD_TO_TESTVIA_SPACING_VMODE OFF SN_LINE_TO_TESTVIA_SPACING_VMODE OFF SN_SHAPE_TO_TESTVIA_SPACING_VMODE OFF SN_BBV_TO_BBV_SPACING_VMODE OFF SN_BONDPAD_TO_BBV_SPACING_VMODE OFF SN_BBV_TO_LINE_SPACING_VMODE OFF SN_BBV_TO_SHAPE_SPACING_VMODE OFF SN_BONDPAD_TO_BONDPAD_SPACING_VMODE OFF SN_BONDPAD_TO_LINE_SPACING_VMODE OFF SN_BONDPAD_TO_SHAPE_SPACING_VMODE OFF SN_LINE_TO_LINE_SPACING_VMODE OFF SN_LINE_TO_SHAPE_SPACING_VMODE OFF SN_SHAPE_TO_SHAPE_SPACING_VMODE OFF SN_HOLE_TO_PIN_SPACING_VMODE OFF SN_HOLE_TO_VIA_SPACING_VMODE OFF SN_HOLE_TO_LINE_SPACING_VMODE OFF SN_HOLE_TO_SHAPE_SPACING_VMODE OFF SN_HOLE_TO_HOLE_SPACING_VMODE OFF SN_MVIA_TO_MVIA_SPACING_VMODE OFF SN_MVIA_TO_THRUPIN_SPACING_VMODE OFF SN_MVIA_TO_SMDPIN_SPACING_VMODE OFF SN_MVIA_TO_THRUVIA_SPACING_VMODE OFF SN_MVIA_TO_BBV_SPACING_VMODE OFF SN_MVIA_TO_LINE_SPACING_VMODE OFF SN_MVIA_TO_SHAPE_SPACING_VMODE OFF SN_MVIA_TO_TESTPIN_SPACING_VMODE OFF SN_MVIA_TO_TESTVIA_SPACING_VMODE OFF SN_BONDPAD_TO_MVIA_SPACING_VMODE OFF BONDPAD_TO_BONDPAD_DIFFP_SPC_VMODE OFF PACKAGE_PACKAGE_VMODE ON PACKAGE_KEEPIN_VMODE ON PACKAGE_KEEPOUT_VMODE ON ROOM_TYPE_VMODE ON PACKAGE_TO_CAVITY_SPACING_VMODE OFF PACKAGE_TO_LAYER_SPACING_VMODE OFF SHAPE_ISLAND_OVERSIZE_VMODE OFF SOLDERMASK_ALIGNMENT_VMODE OFF SOLDERMASK_SPACING_VMODE OFF SOLDERMASK_CLINE_SPACING_VMODE OFF SOLDERMASK_SHAPE_SPACING_VMODE OFF TPPAD_CMP_SPACING_VMODE OFF TPLOC_CMP_SPACING_VMODE OFF TESTPOINT_ALLOW_UNDER_VMODE OFF MECH_PIN_TO_MECH_PIN_SPACING_VMODE OFF MECH_PIN_TO_CONDUCTOR_SPACING_VMODE OFF VIA_AT_SMD_VMODE OFF VIA_AT_SMD_FIT_VMODE OFF VIA_AT_SMD_THRU_VMODE OFF ETCH_TURN_UNDER_PAD_VMODE OFF PASTEMASK_SPACING_VMODE OFF NEGATIVE_PLANE_SLIVER_SPACING_VMODE OFF VIA_LIST_VMODE OFF PIN_TO_ROUTE_KEEPOUT_VMODE OFF MIN_METAL_SPACING_VMODE OFF DUP_DRILL_HOLE_VMODE OFF MAXIMUM_CAVITY_SIZE_VMODE OFF MAXIMUM_CAVITY_COMPONENT_COUNT_VMODE OFF DESCRIPTION dString sProperty oPart oGate oPin oNet oIODriver oShape oVia oSymbolDefn oSymbol oLine oFigure oVoid oCLine SQ_LINE_WIDTH_VALUES dString sProperty oDesign SURFACE_INDEX_0 CDS_LAYER_TYPE SURFACE gBackEnd CDS_LAYER_MATERIAL AIR gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 0.0000 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 0.0000 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 1.000 gBackEnd CDS_LAYER_LOSS_TANGENT 0.0000 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd TOP CDS_LAYER_IS_NAMED 1 gBackEnd CDS_LAYER_TYPE CONDUCTOR gBackEnd CDS_LAYER_MATERIAL COPPER gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 2.8 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 595900 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.0000 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd CDS_LAYER_IS_TOP_SUBSTRATE 1 gBackEnd CDS_LAYER_ETCH_FACTOR 90.00 gBackEnd CDS_LAYER_EMBEDDED_STATUS NOT_EMBEDDED gBackEnd DIELECTRIC_BELOW_TOP CDS_LAYER_TYPE DIELECTRIC gBackEnd CDS_LAYER_MATERIAL FR-4 gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 29.4 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 0.0000 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd GND_BATT_M CDS_LAYER_IS_NAMED 1 gBackEnd CDS_LAYER_TYPE CONDUCTOR gBackEnd CDS_LAYER_MATERIAL COPPER gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 2.8 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 595900 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd CDS_LAYER_ETCH_FACTOR 90.00 gBackEnd CDS_LAYER_EMBEDDED_STATUS NOT_EMBEDDED gBackEnd DIELECTRIC_BELOW_GND_BATT_M CDS_LAYER_TYPE DIELECTRIC gBackEnd CDS_LAYER_MATERIAL FR-4 gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 6 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 0.0000 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd SIGROUTE_1 CDS_LAYER_IS_NAMED 1 gBackEnd CDS_LAYER_TYPE CONDUCTOR gBackEnd CDS_LAYER_MATERIAL COPPER gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 1.2 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 595900 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd CDS_LAYER_ETCH_FACTOR 90.00 gBackEnd CDS_LAYER_EMBEDDED_STATUS NOT_EMBEDDED gBackEnd DIELECTRIC_BELOW_SIGROUTE_1 CDS_LAYER_TYPE DIELECTRIC gBackEnd CDS_LAYER_MATERIAL FR-4 gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 8 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 0.0000 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd BATT_+_CHG CDS_LAYER_IS_NAMED 1 gBackEnd CDS_LAYER_TYPE CONDUCTOR gBackEnd CDS_LAYER_MATERIAL COPPER gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 1.2 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 595900 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd CDS_LAYER_ETCH_FACTOR 90.00 gBackEnd CDS_LAYER_EMBEDDED_STATUS NOT_EMBEDDED gBackEnd DIELECTRIC_BELOW_BATT_+_CHG CDS_LAYER_TYPE DIELECTRIC gBackEnd CDS_LAYER_MATERIAL FR-4 gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 8 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 0.0000 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd BATT_+_DSCHG CDS_LAYER_IS_NAMED 1 gBackEnd CDS_LAYER_TYPE CONDUCTOR gBackEnd CDS_LAYER_MATERIAL COPPER gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 2.8 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 595900 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd CDS_LAYER_ETCH_FACTOR 90.00 gBackEnd CDS_LAYER_EMBEDDED_STATUS NOT_EMBEDDED gBackEnd DIELECTRIC_BELOW_BATT_+_DSCHG CDS_LAYER_TYPE DIELECTRIC gBackEnd CDS_LAYER_MATERIAL FR-4 gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 28 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 0.0000 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.03500 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd BOTTOM CDS_LAYER_IS_NAMED 1 gBackEnd CDS_LAYER_TYPE CONDUCTOR gBackEnd CDS_LAYER_MATERIAL COPPER gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 2.8 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 595900 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 4.500 gBackEnd CDS_LAYER_LOSS_TANGENT 0.0000 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd CDS_LAYER_IS_BOTTOM_SUBSTRATE 1 gBackEnd CDS_LAYER_ETCH_FACTOR 90.00 gBackEnd CDS_LAYER_EMBEDDED_STATUS NOT_EMBEDDED gBackEnd SURFACE_BELOW_BOTTOM CDS_LAYER_TYPE SURFACE gBackEnd CDS_LAYER_MATERIAL AIR gBackEnd CDS_LAYER_NEGATIVE_ARTWORK FALSE gBackEnd CDS_LAYER_IS_SHIELD FALSE gBackEnd CDS_LAYER_THICKNESS 0.0000 uLayerThickness mil 1.000000 gBackEnd CDS_LAYER_ELECTRICAL_CONDUCTIVITY 0.0000 uElectricalConductivity mho/cm 1.000000 gBackEnd CDS_LAYER_DIELECTRIC_CONSTANT 1.000 gBackEnd CDS_LAYER_LOSS_TANGENT 0.0000 gBackEnd CDS_LAYER_THERMAL_CONDUCTIVITY 0.0000 uThermalConductivity W/cm-degC 1.000000 gBackEnd allRules 41_cell_rev_B DEFAULT DEFAULT DEFAULT DEFAULT MIN_LINE_WIDTH 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd MIN_NECK_WIDTH 6.0000,6.0000,6.0000,6.0000,6.0000,6.0000 gBackEnd MIN_BVIA_STAGGER 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MAX_BVIA_STAGGER 0.0000,0.0000,0.0000,0.0000,0.0000,0.0000 gBackEnd TS_ALLOWED ANYWHERE,ANYWHERE,ANYWHERE,ANYWHERE,ANYWHERE,ANYWHERE gBackEnd DIFFP_PRIMARY_GAP 6.0000,6.0000,6.0000,6.0000,6.0000,6.0000 gBackEnd DIFFP_NECK_GAP 0.0000,0.0000,0.0000,0.0000,0.0000,0.0000 gBackEnd MAX_LINE_WIDTH 100.0000,100.0000,100.0000,100.0000,100.0000,100.0000 gBackEnd MAXIMUM_NECK_LENGTH 12000.0000,12000.0000,12000.0000,12000.0000,12000.0000,12000.0000 gBackEnd PAD_PAD_DIRECT_CONNECT ALL_ALLOWED,ALL_ALLOWED,ALL_ALLOWED,ALL_ALLOWED,ALL_ALLOWED,ALL_ALLOWED gBackEnd ALLOW_ON_ETCH_SUBCLASS TRUE,TRUE,TRUE,TRUE,TRUE,TRUE gBackEnd DIFFP_COUPLED_PLUS 0.0000,0.0000,0.0000,0.0000,0.0000,0.0000 gBackEnd DIFFP_COUPLED_MINUS 0.0000,0.0000,0.0000,0.0000,0.0000,0.0000 gBackEnd DIFFP_MIN_SPACE 6.0000,6.0000,6.0000,6.0000,6.0000,6.0000 gBackEnd VIA_LIST 28C12D gBackEnd fObjectNOTReadOnly DEFAULT THRUPIN_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd THRUPIN_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd THRUPIN_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd LINE_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd THRUPIN_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SMDPIN_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SMDPIN_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd LINE_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SHAPE_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd THRUVIA_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd LINE_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SHAPE_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd LINE_TO_LINE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd LINE_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SHAPE_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BBV_TO_BBV_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BBV_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BBV_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BBV_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BBV_TO_LINE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BBV_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BBV_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BBV_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd TESTPIN_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd TESTPIN_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SMDPIN_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd TESTPIN_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd TESTPIN_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd LINE_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SHAPE_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd TESTVIA_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd TESTVIA_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SMDPIN_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd TESTVIA_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd LINE_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SHAPE_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_BONDPAD_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd THRUPIN_TO_BONDPAD_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SMDPIN_TO_BONDPAD_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_LINE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_BBV_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MIN_BVIA_GAP 5.0000 gBackEnd HOLE_TO_PIN_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd HOLE_TO_VIA_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd HOLE_TO_LINE_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd HOLE_TO_SHAPE_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd HOLE_TO_HOLE_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd MVIA_TO_MVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MVIA_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MVIA_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MVIA_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MVIA_TO_BBV_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MVIA_TO_LINE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MVIA_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MVIA_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd MVIA_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_MVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd BONDPAD_TO_BONDPAD_DIFFP_SPC 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd fObjectNOTReadOnly DEFAULT SN_THRUPIN_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_THRUPIN_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_THRUPIN_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_LINE_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_THRUPIN_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SMDPIN_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SMDPIN_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_LINE_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SHAPE_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_THRUVIA_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_LINE_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SHAPE_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_LINE_TO_LINE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_LINE_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SHAPE_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BBV_TO_BBV_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BBV_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BBV_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BBV_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BBV_TO_LINE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BBV_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BBV_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BBV_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_TESTPIN_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_TESTPIN_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SMDPIN_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_TESTPIN_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_TESTPIN_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_LINE_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SHAPE_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_TESTVIA_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_TESTVIA_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SMDPIN_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_TESTVIA_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_LINE_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SHAPE_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BONDPAD_TO_BONDPAD_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_THRUPIN_TO_BONDPAD_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_SMDPIN_TO_BONDPAD_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BONDPAD_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BONDPAD_TO_LINE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BONDPAD_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BONDPAD_TO_BBV_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BONDPAD_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BONDPAD_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SAME_NET TRUE,TRUE,TRUE,TRUE,TRUE,TRUE gBackEnd SN_HOLE_TO_PIN_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd SN_HOLE_TO_VIA_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd SN_HOLE_TO_LINE_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd SN_HOLE_TO_SHAPE_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd SN_HOLE_TO_HOLE_SPACING 8.0000,8.0000,8.0000,8.0000,8.0000,8.0000 gBackEnd SN_MVIA_TO_MVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_MVIA_TO_THRUPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_MVIA_TO_SMDPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_MVIA_TO_THRUVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_MVIA_TO_BBV_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_MVIA_TO_LINE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_MVIA_TO_SHAPE_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_MVIA_TO_TESTPIN_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_MVIA_TO_TESTVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd SN_BONDPAD_TO_MVIA_SPACING 5.0000,5.0000,5.0000,5.0000,5.0000,5.0000 gBackEnd fObjectNOTReadOnly