6. Programming Notes for SPI I/O System Each board in the MOOS Power System contains acquisition and/or control functions that are interfaced via the backplane SPI bus. Each SPI_CSn_N select signal on the backplane selects one board. Generally each board will contain a 74HC595 shift register that functions as a control register, with outputs that sub-select one or more I/O devices on the board. In special cases (e.g. Ground Fault measurement circuit) there is a second level control register that can be written as one of the selectable I/O devices. Electrical isolation is provided between the backplane SPI bus signals and the analog I/O section of each board. This allows the analog circuits to operate referenced to power system ground, without ground loops in the backplane. The P2 Processor Board (the Power Acquisition Subsystem controller board) contains an analog section that is very similar to those on the other power system boards, including electrical isolation. It is selected by an SPI_CSn_N signal local to the board. To Select and Read/Write an I/O device: 6.1 De-assert (high) all backplane SPI_CSn_N signals. 6.2 Write an 8-bit value to the backplane SPI bus using SPI_MOSI and SPI_SCK. The value will be clocked into the ‘595 register on each board in the system. All bits should be ‘1’ except the device select bit for the desired device on the desired board, which should be ‘0’. 6.3 Take SPI_CSn_N low for the desired board. This will transfer the 8-bit value to the ‘595 output register (RCLK) on that board, enable the ’595 outputs (G), select one device on the board, and enable the board’s SPI_MISO output to drive the backplane SPI_MISO bus. You have now selected a device on the board and are ready to read or write. 6.4 Read or write data from or to the selected device, using SPI_SCK and SPI_MISO (for reads) or SPI_MOSI (for writes). (For the LTC2433 A/D converter, 19 bits are read, and a new conversion will start automatically after the 19th bit is read.) 6.5 To deselect the device, take SPI_CSn_N high for the selected board. This disables the ‘595 outputs and disables the board’s SPI_MISO driver output. Optionally, write 0xFF to the ‘595 and then cycle SPI_CS* low and then high again; this will prevent runt select pulses out of the ‘595 when the board is next selected. To Operate Second-Level Devices (e.g. Ground Fault circuit): 6.6 Proceed as for an I/O device, above, however at step 6.2, write 16 data bits instead of 8. The first 8 bits should be the desired contents of the second-level control register (e.g., as needed to enable the Ground Fault test switches). The second 8 bits are for the first-level control register and should be 0x7F. This bit 6.7 pattern will assert 2ND_REG_SEL_N which will clock the second-level latch clock in the next step. 6.8 Cycle SPI_CSn_N for the board low and then high. This will clock the first-level ‘595 and enable its outputs, which in turn will cycle 2ND_REG_SEL_N and clock the second-level ‘595 to produce the desired output bits for control of the Ground Fault circuit. To Operate Ground Fault test circuit: 6.9 De-assert (low) all second-level control register output bits per procedure above. 6.10 Assert GF_ENABLE output to power up the isolation amplifier. Wait 10 to 100 milliseconds (exact delay not critical.) Leave GF_ENABLE asserted thru remainder of procedure. 6.11 Read GF A/D and discard reading. Wait 200 milliseconds or until conversion completes. Read A/D again and save reading as GF_Zero_Value. 6.12 Assert GF_TEST_LOW_SIDE to enable low-side PhotoMOS relay. Wait GF_SETTLE_TIME (0.2 to 10 seconds, exact delay not critical), read GF A/D and discard reading. Wait 200 milliseconds or until conversion completes; read A/D again and save reading as GF_Lowside_Value. De-assert GF_TEST_LOW_SIDE. Wait 10 milliseconds. 6.13 Assert GF_TEST_HIGH_SIDE to enable high-side PhotoMOS relay. Wait 1 to 2 seconds (exact delay not critical), read GF A/D and discard reading. Wait 200 milliseconds or until conversion completes; read A/D again and save reading as GF_Highside_Value. De-assert GF_TEST_HIGH_SIDE. 6.14 Assert GF_TEST_SELFTEST to enable self-test function. Wait 1 to 2 seconds (exact delay not critical), read GF A/D and discard reading. Wait 200 milliseconds or until conversion completes; read A/D again and save reading as GF_Selftest_Value. De-assert GF_TEST_SELFTEST. 6.15 De-assert all second-level control register outputs, including GF_ENABLE which has been on since beginning of procedure (step 6.9). 6.16 Summary (with nominal timing): De-assert all control bits Assert GF_ENABLE Wait 10 msec Read GF A/D and discard Wait 200 msec Read GF A/D, save reading as GF_Zero_Value Assert GF_TEST_LOW_SIDE Wait GF_SETTLE_TIME (1 second nom) Read GF A/D and discard Wait 200 msec Read GF A/D, save reading as GF_LOWSIDE_VALUE De-assert GF_TEST_LOW_SIDE Wait 10 msec Assert GF_TEST_HIGH_SIDE Wait GF_SETTLE_TIME (1 second nom) Read GF A/D and discard Wait 200 msec Read GF A/D, save reading as GF_HIGHSIDE_VALUE De-assert GF_TEST_HIGH_SIDE Wait 10 msec Assert GF_TEST_SELFTEST Wait GF_SETTLE_TIME (1 second nom) Read GF A/D and discard Wait 200 msec Read GF A/D, save reading as GF_SELFTEST_VALUE De-assert GF_TEST_SELFTEST De-assert all control bits.