iMOOS Power System
48-12V Converter
Design Notes

Ed Mellinger
October 2003

1) Component Options

	PWM Chips

			units		ISL6740		MIC3838	Si9122		IR2805		UCC28083

	Vdd max	V		20					
	Vdd Clamp	V		no		
	UV Trip		V		6.0

	Iop, nl		mA		8
	Istart		uA		140

	Ctrl Mode			voltage
	Vin Feedfwd			no
	Curr Lim Typ			hiccup
	Curr Lim Thres	V		0.6
	Soft Start			adj

	Osc Freq	kHz		20-1000	
	Duty Cycle	%		0-99

	Vref		V		5.0
	Vref reg L/L	%
	Vref out		mA		20/-5
	
	SR Sync			no	
	Sw Drive	V/A		5/.05
	High Sw Drive	V		no
	Deadtime Ctrl			adj

	Mfgr				Intersil	
	Release Date			8/03
	Lead Time	wks		3 ?
	Ref Design			48-12 unreg		
	Eval Board			no

	MOSFETs

					IRF7493	IRFR3518	IRFR3410	FDD3682	FDB3672

	Vbrdss		V		80		80		100		100		100
	Rdson		mohm		15		29		39		36		28
	  @ Vgs		V		10		10		10		10		10
	Qg typ		nC		31		37		37		18		24
	Qgd typ		nC		12		12		11		
	Package			SO8		DPak		DPak		Dpak		DPak
	Rthjc		K/W		50		1.4		1.4

	Note DPak = TO-252AA; D2Pak = TO-263AB (per IR site)		

	Schottky Rectfiers

					50WQ10FN		50WQ06FN

	Vrrm		V		100			60
	IF av		A		5.5			5.5
	Vf max 25C	V		0.77			.57
	Cj @ 5V	pF		183			360
	Ir max 25C	mA		1			3
	Package			Dpak Tab Cath		Dpak Tab Cath

2)  Requirements

				min	normal op	max		note						

	Input Voltage	V	42	45-54		60		V/cell: 1.75 min, 1.87-2.25 operating, 2.50 max

	Output Voltage	V	10.5	11.2-13.4	15		unregulated, divide-by-4, fixed duty 99%
				11.2	12.0 - 14.4	15		quasi-regulated, divide 3.75, limit duty above 54V input
				13	13.5		14		regulated

	Output Power	W	5	10-30		50
	Output Current	A	.37	0.75 - 2.2	3.7		10:1 output ratio; higher if possible (inductor CCM)
	Current Limit	A		12				or as set by thermal limits (probably lower)

3) Design Notes

	3.1	Transformer turns ratio; Vin/2 for cap leg divider, Vout+1 for rectifier drop and other loss fudge factor. 
		Sims use 0.6V rectifier drop, other baseline parameters.

		Quasi-regulated:  	42V in, 11.2V out:  (42/2) / (11.2 + 1) = 1.72, choose 1.667 or 5:3
					Simulated duty 0.95 max

		Regulated:		45 V in, 13.5V out: (45/2) / (13.5 + 1) = 1.55, choose 1.5 or 3:2
					Simulated duty 0.95 @ 45V, 0.79 @ 54V, 0.71 @ 60V 

	3.2	Choose 50 kHz as a starting point (means actual transformer flux frequency 25 kHz)

		Allow 100 nsec deadtime for starters.  (May be able to reduce later)

		100 nsec/20 usec = 0.5% so max duty = 99.5%

		Oscillator components:

			(need updated data sheet from Intersil to choose values)

	3.3	Transformer design

		Regulated option – duty cycle varied with Vin (open loop) 

		A) Initial design with Power 4-5-6

		No airflow, 85C (to get biggest core suggestion) : 2.19 cm2
		Use generic core, E-lam shape, TDK PC44, delB .064T, loss .022W @ 54 Vin
		Window is 2.21 cm wide x .74 build
		Pri 15 T #18, 2 layers, 2 strands.  Loss .025W @ 20W out.
		Pri leakage .55 uH, I peak 1.63... approx .04W loss @ 50 kHz, 1.6 amps peak
		Sec 10T x 2 strands #19... loss .02 W
		total loss approx 0.1 W
		Lmag .89 mH; Imag approx 0.5 A p-p (viewed in primary current waveform with output inductor = 999 uH)

		above values juggled to give approx equal winding, core, and leakage losses
		12T primary gives lower leakage and copper losses, higher core loss and Imag.

		Aux Windings

		Core excitation is 21-30V on 15 T, or 1.4 – 2.0 V/turn
		Desired SR switch drive is 8-12 V, 6T gives 8.4 to 12.0 V drive.
		Desired bias supply 10 VDC, use LT3010 LDO, need 10.5 V in
		Allow 0.3V sag on storage cap (peak detecting), 0.7 V for diode (e.g. BAS19), need 11.5 V in
		9 turns gives 12.6 – 18 V raw supply to LDO

B) Design based on E625 core (Magnetics 44721) using ‘F’ ferrite… 
Ae = 2.39 cm2, Ve = 21.3 cm3, hgt 1.34”, window 2.11 x 0.65 cm

With Vin=60V, Pout=20W.  Typical duty .70-.72
Based on 15:10(6):9 design above (Primary:Secondary(SR Tap):Bias)
Fundamental Ratios are 2.5:1.67(1):1.5… try options using Power 4-5-6

Pri T	Sec T	SR T	Bias T	Pri AWG	Pri W	Sec AWG	Sec W	Bmax 	Core W	    Llk
			15	10	6	9	19x2x2		.031	19x2		.032	.058	.145	    0.9
			20	13	8	12	19x2x2		.037	22x2		.069	.045	.065	    1.4
			25	17	10	15	21x2x2		.053	23x2		.104	.036	.032	    1.8
			30	20	12	18	23x2x2		.084	25x2		.192	.029	.016	    2.3	

	3.4	Inductor design

		Suggested 118 uH, use 300 uH
		at Vin = 60V, gives ripple of 0.3A p-p
		CCM down to 4% output (2W)
		2.76 cm2 core area – E shape generic
		Window 2.5 x 0.83 cm – 94% filled
		33 turns
		5 layers x 2 strands #15 AWG
		10.8 mohms
		0.15 W @ I = 3.7 A (50 W load)

		Note – Mag Ckt Elements HL series MPP toroids has two suitable parts:
		250 uH – 11 mohm – 19 A max – swings to 200 uH @ 4A, 75 uH @ 12A
		400 uH – 17 mohm – 15 A max – swings to 320 uH @ 4A, 80 uH @ 12A
		Both ED95 size, 2.2” dia x 1.4” h

Also can use HL series ED78 size… 1.8” dia x 1.1” h, 125 g
(Higher resistance… probably OK in light of transformer 50 mohm secondary)
250 uH – 15 mohm – 11 A max – swings to 37uH @ 12A

3.5	Rectifiers

Assume worst case is full Vin applied to primary (e.g. badly out of balance duty cycle).
60 V in, 40 V each secondary
Rectifiers see 80V
(Future: If primary does see half Vin under all conditions –
	30 V in, 20 V each secondary, 40V on rectifiers… use 60V parts)

Backup Schottky:
Use 100V parts initially… 50WQ10FN… Vf = 0.77V max

With no SRs, backups carry full current.
Worst case would be low line, 99% switch duty… Schottky duty would be 0.50
12A x 0.91V = 10.9 W…
	… x 0.50 duty = 5.45W dissipation.
DPak on 1” sq Cu can handle 2-3 W
Thus max current without SRs will be approx 6A output.

		With SRs working, backup Schottky conducts only during dead time
		Worst case duty 0.28 at Vin = 60V
		2 diodes, center tap topology
		Each carries half of IL 
		IL = 3.7 A @ 50W, diode current = 3.7 * 0.5 * 0.28 = 0.52 A
		IL = 12 A @ CurrLim, diode current 12 * 0.5 * 0.28 = 1.68 A

		Sync Rect:
		Use 100 V parts initially
		FDB3672 100V, 28 mohm, 24 nC

		@ Vin = 60 V
		Switch duty = 0.72, rectifier duty 0.28
		
Full Load condition
Output current IL sees 28 mohms for 0.72,  0.77 V for 0.28
				Prect 	= (.028 * 3.7 *3.7 * 0.72) + (0.77 * 3.7 * 0.28)
					= 0.28 + 0.80
					= 1.08 W
		Each device loss half this or 0.54 W

		Current Limit condition
				Prect 	= (.028 * 12 * 12 * 0.72) + (0.95 * 12 * 0.28)
					= 2.9 + 3.2
					= 6.1 W
		Each device loss half this or 3 W
		Actual device Rthja will determine actual current limit.  

		Run Power 4-5-6 for Vin = 60V, Pout = 50W with Vf = (0.77 x 0.28) = 0.22 V, Rf = (.028 x 0.72) = .020 ohm
		Predicted total loss 1.05 W
		
		At other output power: total loss 0.36 W at 20 W out, .08 W at 5 W out

3.6	Main Switches

Aim for equal (or equally varying) loss due to conduction and to (switching + gate drive) at Pout = 20W
Assume 1A gate drive: Tsw in nsec equals Qg in nC
Pgate = 60V * Qg * 50 kHz (for both switches)

At Vin = 60V, Pout = 20W:
Using IRF7493 (80 V, 31 nC, .015 ohm)
Pcond = .016 W, Psw = .19 W, Pgate = .093 W
Using FDB3672 (100V, 24 nC, .028 ohm)
	Pcond = .03 W, Psw = .087 W, Pgate = .072 W
Using FDB3682	 (100V, 18 nC, .036 ohm)
	Pcond = .038 W, Psw = .065 W, Pgate = .054 W

Main Switch Gate Drive

Using HIP2101
3 ohm drive, 1 ohm bootstrap diode
Bootstrap capacitor:
Qg = 28 nC worst case
Driver HB pin:
	Quiescent + Operating = 0.2mA + 3 mA/10 = 0.5 mA
	0.5 mA x 20 usec = 10 nC
Total 10 + 28 = 38 nC
Allow 0.3 V ripple; Q/V = C, 38 E-9/0.3 = 127 nF, use 0.22?
50V allows margin for negative swing at driver HS pin.

3.7	Bridge Caps

Assume 20 usec on time, 8 amps primary (42V low line, i12 amp output)
20 usec x 8 amps = 160 uC charge… 80 uC for each half of cap bridge.

dV on bridge caps (sag)… builds linearly… stepped down by turns ratio then integrated (averaged) by output inductor.  E.g. 1V peak sag at primary is 0.7V at secondary, 0.35V at output.
Try 50uF… V = Q/C = 80E-6/50E-6 = 1.6V on primary… 1.12V on secondary… 0.56V at output… apparent impedance contribution .56V/12A = 47E-3 ohms.
Hold sag to 1V… C = Q/V = 80E-6/1 = 80 uF… use two each Elec Concepts 50 uF units… lots of ripple capacity.
Cap voltage should be ½ Vin unless PWM stalls or other disaster, then could go to full Vin (!)

(Protect caps with TVS… 45V would allow midpoint to go halfway to either rail but allow 50V caps
43V 5kW TVS avail thru DigiKey
Protect front-end with 10A fuse… need to work out Prospective SCC and survival time of FETs and TVSs vs fuse.
TVS would also protect output rectifiers and bias supply… and of course, protect input against spikes and reverse polarity.)

So caps can be 50 uF, 50V units… 1.03” x 1.44” x 1.06” high.  Or since Xfmr looks to be 1.34” high, could use 50 uF, 75V units which are 1.31” high… these might be useful elsewhere in system as 48V bypass (e.g. load dump).)

3.8	Input Cap

Input ripple 4A peak (other half is supplied by bridge caps).  RMS depends on duty cycle and source inductance.
At Vin = max, duty = 0.7.   Cap waveform is 1.2 A out at 0.7, 2.8 A in at 0.3 duty… 
…Irms is (2.8**2 x 0.3 + 1.2**2 x 0.7)**0.5 = 1.83 Ac
Panasonic FC series (DigiKey)… 63 WVDC… 12.5mm dia x 25mm h… 390 uF… .07 ohms… 1.72 A ripple.
Use two.

3.9	Output Cap

At 12A output, 80 uH inductor, sim says cap ripple is 0.3 A RMS.
(Ripple depends on L, Vin, and D, not Iout)
Panasonic FC (Digi-Key) 1500 uF, 16 WVDC, 16 dia x 15 h mm case, 1.69 A each (at 105C), 43 mohm
2 parallel gives 3000 uF,  22 mohm, 3.4 A RMS
(Choose this size to allow 16mm x 31mm caps on 375V version… they will be 2 ea 47uF, 400 WVDC, 730mA each.)

3.10	Bias Supply, Startup Supply

Loads are 	ISL6740 Idd of 8 mA, 
main switch drive of (28nC * 50kHz) = 1.4 mA, 
HIP2101 Idd of 0.6 + 0.34 = 1 mA
Op amp Icc of 1 mA
Total 14 mA… round up to 20 mA
Time between “refresh” of bias supply holdup cap could be 40 usec worst case
40 usec x 20 mA = 800 nC
Try for 0.3 V ripple… C = Q/V = 800E-9/0.3 = 2.7 uF
Use Sprague/Vishay 293D, 3.3 uF @ 20V, B case (3528)

LT3010 LDO -– Run Side
Program for 10.0 V output
R1 = 102k, R2 = 698k (zero error!)… divider current 1.275V/102k = 12.5uA… 50nA/12.5uA = 0.4% error
Lead comp cap… 100k at 10kHz… C = 1/(2*pi*f*Z) = 1/(2*pi*10k*102k) = 156 pF… use 180pF
Output cap… use 3.3uF from input stage… ESR = 3 ohms which is max.

3.3uF will be “bulk” bypass for PWM chip and startup supply
Holdup time… Q = CV… V = 0.75V UVLO hysteresis… Q = 3.3E-6 * 0.75 = 2.5uC… 
2.5uC/20mA = 125 usec holdup time which is 3 PWM cycles…. enough?

LT3010 LDO – Startup Side
Program for 9.0 V… gives 1V margin above UVLO Max, 1V below nominal Vbias
R1 = 102k, R2 = 619k (0.14% error)… other values as above.

3.11	Vin Feedforward

Need duty of approx 0.70 at Vin = 60V, and 0.99 at Vin = 42V.

Oscillator swings 0.8 to 2.8 V per datasheet; swing is 2.0 V (+/- 0.15V)
Osc and Verror pins both have gain of 0.4, thus Verror pin should have same active range as Osc
0.8V -> min duty… 2.8V -> max duty
0.70 duty * 2.0V range = 1.4V… 0.8V + 1.4V = 2.2V at Verror 
Thus desired mapping of Feedfwd ckt  from Vin to Verror is 42V à 2.8V… 60V à 2.2V.
Can treat as +4.2V offset and gain of -0.6/18 = -1/30 :

	   0 Vin		4.2 Verror
 42 		2.8
 60 		2.2
126	0
127	
Use Vref = 5.00V from 6740 for offset… run op amp at gain needed to give double output swing, then divide down (alternative is to divide offset before op amp… same parts count, more noise sens)

Noninverting gain is (1+Rf/Ri)… inverting is –Rf/Ri
Set NI gain to scale 5.00 V up to 8.4V output with Vin=0
	Av = 8.4/5 = 1.680
	Resistor ratio Rf/Ri = 0.68… use Rf = 13.7k, ideal Ri is then (13.7 / .68) = 20.15k
	(Would like higher values but need to keep Vin divider upper resistor value tractable)
	Need input divider that looks like 20.15k
	Inverting gain would be –Rf/Ri = 0.68
	Input divider was 1/30 or 0.033 but now should be 0.68 of that or 1/20.4 or .04902
	…times 2 due to op amp operating at 2x output… 0.09804
	Thus need divider that divides by .09804 and looks like 20.15k at the midpoint… 
205k and 22.1k divide to .0973 or 0.74% low… look like 19.95k or 1% low (which gives 1% extra gain)
Test case with exact values and Vref = 5.00V
Vin	Vamp	Verror
0	8.43	4.21
42	5.62	2.81
60	4.43	2.21
Make 2:1 divider on amp output a “select at checkout” value, until we get a feel for variability of PWM chips.  Adjusting here affects both offset and gain at once… delta Vin cancellation will not be “perfect”… but it should be good enough (couple of percent of delta Vin percent).

Alternative scheme would use Vin divider and voltage follower… change to divider would adjust “gain” of Vin term… feeding thru build-out resistor into unity gain inverting amp with 2.10V offset on NI input (NI gain of 2)… adjusting offset would adjust “offset” of final cancellation signal.

Use 30:1 divider from Vin, 1.4V @ 42V, 2.0V @ 60V.  
Offset at NI input is 2.1V, output is 4.2 – 1.4V = 2.8V @ 42V, 4.2V – 2.0V @ 60V 

3.12	UVLO Sense

	Use Vin Feedfwd divider... set tap at 1.00 V for UVLO input to 6740.
	At Vin = 42V, divider current is 42/(576k + 20k) = 70uA...
	... 1V/70uA = 14.2k... use 14.3k as tap... 5.76k to make 20k total.
	Hysteresis: With rising Vin, 10uA goes into 6740 UVLO... need 80uA in divider to get 70uA thru 14.3k
	Von = 80uA * (576k + 5.76k) + 1V = 47.8V.... reasonable value for startup.

3.13	Soft Start

	3000uF output cap
	Charge at Inom of 3.7A to 13.5V...
		dt = C*(dV/I) = 3E-3 * (13.5V/3.7A) = 10.9 msec
	Soft start condition... Verror 2V swing... 55uA charge
		C = I * (dt/dV) = 55E-6 * (10E-3 / 2V) = 275nF... use 0.33 (already elsewhere on board)
	Overcurrent response time
	Discharge SS Cap at 15uA for 0.25V
		dt = C * (dV / I) = 0.33E-6 * (0.25 / 15E-6) = 5.5 msec... Yikes, huge.
	Need alternate fast shutdown on large overcurrent... try OTS input.

3.14	Current Sense, Current Limit

	Try shunt resistor and diff amp combination
	Try .005 ohm... 0.32W loss at 8A limit condition... 
		... (.005 x 8A) = 40mV signal full scale at 8A (nominal limit); 60mV at 12A (OTS shutdown)
	Need 0.6V for CS input... Av = 0.6/.04 = 15
	Need 2.5V for OTS input... Av = 2.5/.06 = 41.67... use 1.00k and 41.2k in diff amp.
	Per TI appnote, set diff amp rolloff corner at 3X switching freq, or 150 kHz.
		C = 1/(2 * pi * R * f) = 1/(2 * pi * 41k * 150kHz) = 26pF use 27pF

	For CS input, need to divide OTS signal down by 15/41.2 = 0.364 to wind up with overall Av = 15.
	Use 18.7k and 10.7k … .01% off.

3.15	Fuse

	Rated output 12A @ 13.5V, 162W
	100% input @ 42V is 162/42 = 3.85A, @ 85% eff  4.5 A
	Use 8A fuse since MOOS converter is protected by upstream fuse on Conv/GF board
	(may use 5A or 6.3A fuse in other future apps)
	Fuse rated 180mV drop @ 8A,  22.5 mohm
	Drop @ 4.5A = 4.5 x .0225 = 101 mV
	Eff loss @ 42V is .101/42 = 0.25%

	

Simulated Performance

	Vin	Vout	Iout	D	Iswpk	Psw	Iprirms	Ppri	Pcore Psec	Precttot	 Il min	Pl	Loss	Eff