## Synthesis Log

Created on 11:25:33 04/09/02

Running XST Synthesis...
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=========================================================================
---- Global Settings
Tmp directory : .
DUMPDIR : .
overwrite : YES
EdifUpper : YES
=========================================================================
XST D-27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
--> Parameter DUMPDIR set to .
--> Parameter overwrite set to YES
--> Parameter EdifUpper set to YES
--> =========================================================================
---- Source Parameters
Input File Name : dpa_top.prj
Input Format : Verilog
---- Target Parameters
Output File Name : dpa_top.edn
Output Format : EDIF
---- Source Options
Entity Name : dpa_top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Compact
HDL Verbose Level : 2
RAM Extraction : YES
RAM Style : Auto
Mux Extraction : YES
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
Resource Sharing : YES
Resolution Style : WIRE_MS
---- FSM Options
FSM Flip-Flop Type : D
---- Target Options
Family : 9500
Add IO Buffers : YES
Use Fast Output Buffers : NO
Macro Generator : Macro+
MACRO Preserve : YES
XOR Preserve : YES
FF Optimization : YES
Flatten Hierarchy : YES
Clock Enable : YES
---- General Options
Optimization Criterion : Area
Optimization Effort : 2
---- Other Options
comlex_clken : YES
attribute : G:\VSS_Projects\work\sjensen\HDL_project2\src\cool_pinout.ucf
=========================================================================
Setting FSM Encoding Algorithm to : OPT
Compiling source file : dpa_top.prj
Compiling included source file '..\compile\dpa_top.v'
Module <dpa_top> compiled.
Continuing compilation of source file 'dpa_top.prj'
Compiling included source file '..\compile\SSPInterface.v'
Continuing compilation of source file 'dpa_top.prj'
Module <SPInterface> compiled.
Compiling included source file '..\src\Synchronizer.v'
Module <Synchronizer> compiled.
Continuing compilation of source file 'dpa_top.prj'
Compiling included source file '..\compile\ADC_control.v'
Continuing compilation of source file 'dpa_top.prj'
Module <ADC_control> compiled.
Compiling included source file '..\compile\Dpot_control.v'
Continuing compilation of source file 'dpa_top.prj'
Module <Dpot_control> compiled.
Compiling included source file '..\src\Dpot_counter.v'
Module <Dpot_counter> compiled.
Continuing compilation of source file 'dpa_top.prj'
Compiling included source file '..\compile\Interrupt.v'
Continuing compilation of source file 'dpa_top.prj'
Module <Interrupt> compiled.
Compiling included source file '..\src\interrupt_generator.v'
Module <interrupt_generator> compiled.
Continuing compilation of source file 'dpa_top.prj'
Compiling included source file '..\src\Pulse_generator.v'
Module <Pulse_generator> compiled.
Continuing compilation of source file 'dpa_top.prj'
Compiling included source file '..\compile\Relay_control.v'
Module <Relay_control> compiled.
Continuing compilation of source file 'dpa_top.prj'
Compiling included source file '..\src\Relay_driver.v'
Module <Relay_driver> compiled.
Continuing compilation of source file 'dpa_top.prj'
Compiling included source file '..\compile\ch_control.v'
Continuing compilation of source file 'dpa_top.prj'
Module <ch_control> compiled.
Compiling included source file '..\compile\Write_command.v'
Continuing compilation of source file 'dpa_top.prj'
Module <Write_command> compiled.
Compiling included source file '..\src\Response.v'
Module <Response> compiled.
Continuing compilation of source file 'dpa_top.prj'
WARNING : (VLG__5005). ..\compile\dpa_top.v Line 293. Port sizes don't match in port #7
WARNING : (VLG__5005). ..\compile\dpa_top.v Line 334. Port sizes don't match in port #2
WARNING : (VLG__5005). ..\compile\dpa_top.v Line 351. Port sizes don't match in port #2
3 warnings in compilation
No errors in compilation
Analysis of file <dpa_top.prj> succeeded.
Starting Verilog synthesis.
"..\compile\SSPInterface.v", Line 76: Found FullParallel Case directive in module <SPInterface>.
"..\compile\ADC_control.v", Line 70: Found FullParallel Case directive in module <ADC_control>.
"..\compile\Dpot_control.v", Line 79: Found FullParallel Case directive in module <Dpot_control>.
"..\compile\Interrupt.v", Line 48: Found FullParallel Case directive in module <Interrupt>.
"..\compile\ch_control.v", Line 63: Found FullParallel Case directive in module <ch_control>.
"..\compile\Write_command.v", Line 73: Found FullParallel Case directive in module <Write_command>.
Analyzing module <SPInterface>.
Module <SPInterface> is correct for synthesis.
Analyzing module <Response>.
Module <Response> is correct for synthesis.
Analyzing module <Relay_driver>.
Module <Relay_driver> is correct for synthesis.
Analyzing module <Relay_control>.
Module <Relay_control> is correct for synthesis.
Analyzing module <ch_control>.
Module <ch_control> is correct for synthesis.
Analyzing module <interrupt_generator>.
Module <interrupt_generator> is correct for synthesis.
Analyzing module <Interrupt>.
Module <Interrupt> is correct for synthesis.
Analyzing module <ADC_control>.
Module <ADC_control> is correct for synthesis.
Analyzing module <Write_command>.
Module <Write_command> is correct for synthesis.
Analyzing module <Pulse_generator>.
Module <Pulse_generator> is correct for synthesis.
Analyzing module <Dpot_counter>.
Module <Dpot_counter> is correct for synthesis.
Analyzing module <Dpot_control>.
Module <Dpot_control> is correct for synthesis.
Analyzing module <Synchronizer>.
Module <Synchronizer> is correct for synthesis.
Analyzing top module <dpa_top>.
Module <dpa_top> is correct for synthesis.
Synthesizing Unit <SPInterface>.
Extracting finite state machine <FSM_0> for signal <CurrState_Sreg0>.
-----------------------------------------------------------------------
| States | 16 |
| Transitions | 31 |
| Inputs | 1 |
| Outputs | 20 |
| Reset type | asynchronous |
| Encoding | compact |
| State register | D flip-flops |
-----------------------------------------------------------------------
Extracting 1-bit register for signal <hold_DAVe>.
Extracting 1-bit register for signal <set_DAVe>.
Extracting 1-bit register for signal <mosi_data>.
Extracting 4-bit register for signal <Command>.
Extracting 12-bit register for signal <data_out>.
Summary:
inferred 1 Finite State Machine(s).
inferred 19 D-type flip-flop(s).
Unit <SPInterface> synthesized.
Synthesizing Unit <Response>.
Extracting 1-bit register for signal <miso_pin_reg>.
Extracting 1-bit register for signal <miso_reg<11>>.
Extracting 1-bit register for signal <miso_reg<10>>.
Extracting 1-bit register for signal <miso_reg<9>>.
Extracting 1-bit register for signal <miso_reg<8>>.
Extracting 1-bit register for signal <miso_reg<7>>.
Extracting 1-bit register for signal <miso_reg<6>>.
Extracting 1-bit register for signal <miso_reg<5>>.
Extracting 1-bit register for signal <miso_reg<4>>.
Extracting 1-bit register for signal <miso_reg<3>>.
Extracting 1-bit register for signal <miso_reg<2>>.
Extracting 1-bit register for signal <miso_reg<1>>.
Extracting 1-bit register for signal <miso_reg<0>>.
Extracting tristate(s) for signal <miso>.
Extracting 1-bit 2-to-1 multiplexer for internal node.
WARNING : (HDL__0002). Input <command<3>> is never used.
WARNING : (HDL__0002). Input <DAVe> is never used.
Summary:
inferred 13 D-type flip-flop(s).
inferred 1 Multiplexer(s).
inferred 1 Tristate(s).
Unit <Response> synthesized.
Synthesizing Unit <Relay_driver>.
Extracting 1-bit register for signal <Position>.
WARNING : (HDL__0003). Output <Pulse_request> is never used.
Summary:
inferred 1 D-type flip-flop(s).
Unit <Relay_driver> synthesized.
Synthesizing Unit <Relay_control>.
Unit <Relay_control> synthesized.
Synthesizing Unit <ch_control>.
Extracting finite state machine <FSM_1> for signal <CurrState_Sreg0>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 7 |
| Inputs | 2 |
| Outputs | 7 |
| Reset type | asynchronous |
| Encoding | compact |
| State register | D flip-flops |
-----------------------------------------------------------------------
Extracting 1-bit register for signal <instr_pwr>.
Extracting 1-bit register for signal <comm_pwr>.
Extracting 1-bit register for signal <fast>.
Extracting 1-bit register for signal <mode>.
Extracting 1-bit register for signal <duplex>.
Extracting 1-bit register for signal <serial_dir>.
Extracting 1-bit register for signal <reset_DAVe>.
Extracting 1-bit 2-to-1 multiplexer for internal node.
Extracting 1-bit 2-to-1 multiplexer for internal node.
Extracting 1-bit 2-to-1 multiplexer for internal node.
Extracting 1-bit 2-to-1 multiplexer for internal node.
Extracting 1-bit 2-to-1 multiplexer for internal node.
Extracting 1-bit 2-to-1 multiplexer for internal node.
Summary:
inferred 1 Finite State Machine(s).
inferred 7 D-type flip-flop(s).
inferred 6 Multiplexer(s).
Unit <ch_control> synthesized.
Synthesizing Unit <interrupt_generator>.
Extracting tristate(s) for signal <intr>.
WARNING : (HDL__0002). Input <reset> is never used.
Summary:
inferred 1 Tristate(s).
Unit <interrupt_generator> synthesized.
Synthesizing Unit <Interrupt>.
Extracting finite state machine <FSM_2> for signal <CurrState_Sreg0>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 7 |
| Inputs | 2 |
| Outputs | 2 |
| Reset type | asynchronous |
| Encoding | compact |
| State register | D flip-flops |
-----------------------------------------------------------------------
Extracting 3-bit register for signal <read_flags>.
Extracting 1-bit register for signal <reset_DAVe>.
Extracting 3-bit 2-to-1 multiplexer for internal node.
Summary:
inferred 1 Finite State Machine(s).
inferred 4 D-type flip-flop(s).
inferred 3 Multiplexer(s).
Unit <Interrupt> synthesized.
Synthesizing Unit <ADC_control>.
Extracting finite state machine <FSM_3> for signal <CurrState_Sreg0>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 11 |
| Inputs | 3 |
| Outputs | 18 |
| Reset type | asynchronous |
| Encoding | compact |
| State register | D flip-flops |
-----------------------------------------------------------------------
Extracting 1-bit register for signal <ADC_CS>.
Extracting 1-bit register for signal <ADC_WR>.
Extracting 1-bit register for signal <ADC_RD>.
Extracting 1-bit register for signal <ADC_HBEN>.
Extracting 1-bit register for signal <reset_DAVe>.
Extracting 12-bit register for signal <ADC_out>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<11>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<10>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<9>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<8>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<7>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<6>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<5>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<4>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<3>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<2>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<1>>.
Extracting 1-bit 2-to-1 multiplexer for signal <next_ADC_out<0>>.
Extracting tristate(s) for signal <ADC_BUS>.
WARNING : (HDL__0002). Input <ADC_INT> is never used.
Summary:
inferred 1 Finite State Machine(s).
inferred 17 D-type flip-flop(s).
inferred 12 Multiplexer(s).
inferred 8 Tristate(s).
Unit <ADC_control> synthesized.
Synthesizing Unit <Write_command>.
Extracting finite state machine <FSM_4> for signal <CurrState_Sreg0>.
-----------------------------------------------------------------------
| States | 9 |
| Transitions | 26 |
| Inputs | 10 |
| Outputs | 0 |
| Reset type | asynchronous |
| Encoding | compact |
| State register | D flip-flops |
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <Write_command> synthesized.
Synthesizing Unit <Pulse_generator>.
Extracting 11-bit register for signal <count>.
Extracting 1-bit register for signal <Pulse>.
Extracting 1-bit register for signal <Pulse_end>.
Extracting 11-bit comparator greater for internal node.
Extracting 11-bit subtractor for internal node.
Summary:
inferred 13 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 1 Comparator(s).
Unit <Pulse_generator> synthesized.
Synthesizing Unit <Dpot_counter>.
Extracting 8-bit register for signal <counter>.
Extracting 8-bit comparator lessequal for signal <Counter_Zero>.
Extracting 8-bit subtractor for internal node.
Summary:
inferred 8 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 1 Comparator(s).
Unit <Dpot_counter> synthesized.
Synthesizing Unit <Dpot_control>.
Extracting finite state machine <FSM_5> for signal <CurrState_Sreg0>.
-----------------------------------------------------------------------
| States | 9 |
| Transitions | 19 |
| Inputs | 6 |
| Outputs | 7 |
| Reset type | asynchronous |
| Encoding | compact |
| State register | D flip-flops |
-----------------------------------------------------------------------
Extracting 1-bit register for signal <dpot_clk>.
Extracting 1-bit register for signal <dpot1_cs>.
Extracting 1-bit register for signal <dpot2_cs>.
Extracting 1-bit register for signal <dpot_ud>.
Extracting 1-bit register for signal <dpot_complete>.
Extracting 1-bit register for signal <Load_counter>.
Extracting 1-bit register for signal <Enable_count>.
Summary:
inferred 1 Finite State Machine(s).
inferred 7 D-type flip-flop(s).
Unit <Dpot_control> synthesized.
Synthesizing Unit <Synchronizer>.
Extracting 1-bit register for signal <clk_side>.
Extracting 1-bit register for signal <spi_side>.
Extracting 1-bit xor2 for signal <DAVe>.
Summary:
inferred 2 D-type flip-flop(s).
inferred 1 Xor(s).
Unit <Synchronizer> synthesized.
Synthesizing Unit <dpa_top>.
Unit <dpa_top> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 7
# Registers : 59
4-bit register : 1
1-bit register : 53
3-bit register : 1
12-bit register : 2
11-bit register : 1
8-bit register : 1
# Multiplexers : 26
1-bit 2-to-1 multiplexer : 25
3-bit 2-to-1 multiplexer : 1
# Adders/Subtractors : 2
11-bit subtractor : 1
8-bit subtractor : 1
# Comparators : 2
11-bit comparator greater : 1
8-bit comparator lessequal : 1
# Xors : 1
1-bit xor2 : 1
=========================================================================
Optimizing FSM <FSM_0> with Compact encoding and D flip-flops.
Optimizing FSM <FSM_1> with Compact encoding and D flip-flops.
Optimizing FSM <FSM_2> with Compact encoding and D flip-flops.
Optimizing FSM <FSM_3> with Compact encoding and D flip-flops.
Optimizing FSM <FSM_4> with Compact encoding and D flip-flops.
Optimizing FSM <FSM_5> with Compact encoding and D flip-flops.
Starting low level synthesis...
Optimizing unit <dpa_top> ...
=========================================================================
Final Results
Output File Name : dpa_top.edn
Output Format : edif
Optimization Criterion : Area
Target Technology : 9500
Flatten Hierarchy : YES
Macro Preserve : YES
Macro Generation : Macro+
XOR Preserve : YES
Macro Statistics
# FSMs : 7
# Adders/Subtractors : 2
11-bit subtractor : 1
8-bit subtractor : 1
# Comparators : 2
11-bit comparator greater : 1
8-bit comparator lessequal : 1
Design Statistics
# Edif Instances : 1004
# I/Os : 71
Other Data
.NCF file name : dpa_top.ncf
=========================================================================
-->
Synthesis finished with warnings.