//////////////////////////////////////////////////////////////////////////////
//                                                                           /
// IAR ARM ANSI C/C++ Compiler V4.11A/W32              20/Jul/2004  18:58:52 /
// Copyright 1999-2004 IAR Systems. All rights reserved.                     /
//                                                                           /
//    Cpu mode        =  arm                                                 /
//    Endian          =  little                                              /
//    Stack alignment =  4                                                   /
//    Source file     =  C:\medusa\zl_util.c                                 /
//    Command line    =  -I "C:\Program Files\IAR Systems\Embedded           /
//                       Workbench 4.0\ARM\INC\" -lc C:\medusa\Debug\List\   /
//                       -la C:\medusa\Debug\List\ -o C:\medusa\Debug\Obj\   /
//                       -s2 --no_cse --no_unroll --no_inline                /
//                       --no_code_motion --no_tbaa --no_clustering          /
//                       --no_scheduling --debug --cpu_mode arm --endian     /
//                       little --cpu ARM7TDMI-S --stack_align 4 -e --fpu    /
//                       None "-D_DLIB_CONFIG_FILE=C:\Program Files\IAR      /
//                       Systems\Embedded Workbench                          /
//                       4.0\ARM\LIB\dl4tpannl8n.h" C:\medusa\zl_util.c      /
//    List file       =  C:\medusa\Debug\List\zl_util.s79                    /
//                                                                           /
//                                                                           /
//////////////////////////////////////////////////////////////////////////////

        NAME zl_util

        RTMODEL "ARMv4M", "USED"
        RTMODEL "StackAlign4", "USED"
        RTMODEL "__cpu_mode", "__pcs__arm"
        RTMODEL "__data_model", "absolute"
        RTMODEL "__dlib_file_descriptor", "0"
        RTMODEL "__endian", "little"
        RTMODEL "__rt_version", "6"

        RSEG CSTACK:DATA:NOROOT(2)

        PUBWEAK `?*?DATA_ID`
        PUBWEAK ?init?tab?DATA_I
        PUBWEAK ?init?tab?DATA_Z
        PUBLIC byteSwap16
        FUNCTION byteSwap16,0203H
        LOCFRAME CSTACK, 4, STACK
        MULTWEAK cliRegisterCommand??rA
        MULTWEAK clicharGetOutputBuffer??rA
        MULTWEAK clicharSendOutputBuffer??rA
        PUBLIC parseDottedQuadV4
        FUNCTION parseDottedQuadV4,0203H
        LOCFRAME CSTACK, 16, STACK
        FUNCTION pdownHandler,0603H
        LOCFRAME CSTACK, 28, STACK
        FUNCTION pdqTestHandler,0603H
        LOCFRAME CSTACK, 52, STACK
        FUNCTION pupHandler,0603H
        LOCFRAME CSTACK, 28, STACK
        FUNCTION quickStatHandler,0603H
        LOCFRAME CSTACK, 44, STACK
        FUNCTION setmacHandler,0603H
        LOCFRAME CSTACK, 44, STACK
        MULTWEAK sprintf??rA
        MULTWEAK strtol??rA
        PUBLIC swapMac
        FUNCTION swapMac,0203H
        PUBLIC zarlinkCpuMacAddrGet
        FUNCTION zarlinkCpuMacAddrGet,0203H
        LOCFRAME CSTACK, 12, STACK
        PUBLIC zarlinkCpuMacAddrSet
        FUNCTION zarlinkCpuMacAddrSet,0203H
        LOCFRAME CSTACK, 12, STACK
        FUNCTION zarlinkHandler,0603H
        LOCFRAME CSTACK, 44, STACK
        MULTWEAK zarlinkIndexedRead??rA
        MULTWEAK zarlinkIndexedWrite??rA
        MULTWEAK zarlinkStatusRead??rA
        PUBLIC zarlinkUtilInit
        FUNCTION zarlinkUtilInit,0203H
        LOCFRAME CSTACK, 4, STACK
        
        CFI Names cfiNames0
        CFI StackFrame CFA R13 HUGEDATA
        CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
        CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13:32
        CFI Resource R14:32, SPSR:32
        CFI VirtualResource ?RET:32
        CFI EndNames cfiNames0
        
        CFI Common cfiCommon0 Using cfiNames0
        CFI CodeAlign 4
        CFI DataAlign 4
        CFI ReturnAddress ?RET CODE
        CFI CFA R13+0
        CFI R0 Undefined
        CFI R1 Undefined
        CFI R2 Undefined
        CFI R3 Undefined
        CFI R4 SameValue
        CFI R5 SameValue
        CFI R6 SameValue
        CFI R7 SameValue
        CFI R8 SameValue
        CFI R9 SameValue
        CFI R10 SameValue
        CFI R11 SameValue
        CFI R12 Undefined
        CFI CPSR SameValue
        CFI R14 Undefined
        CFI SPSR SameValue
        CFI ?RET R14
        CFI EndCommon cfiCommon0
        
cliRegisterCommand  SYMBOL "cliRegisterCommand"
clicharGetOutputBuffer SYMBOL "clicharGetOutputBuffer"
clicharSendOutputBuffer SYMBOL "clicharSendOutputBuffer"
sprintf             SYMBOL "sprintf"
strtol              SYMBOL "strtol"
zarlinkIndexedRead  SYMBOL "zarlinkIndexedRead"
zarlinkIndexedWrite SYMBOL "zarlinkIndexedWrite"
zarlinkStatusRead   SYMBOL "zarlinkStatusRead"
cliRegisterCommand??rA SYMBOL "??rA", cliRegisterCommand
clicharGetOutputBuffer??rA SYMBOL "??rA", clicharGetOutputBuffer
clicharSendOutputBuffer??rA SYMBOL "??rA", clicharSendOutputBuffer
sprintf??rA         SYMBOL "??rA", sprintf
strtol??rA          SYMBOL "??rA", strtol
zarlinkIndexedRead??rA SYMBOL "??rA", zarlinkIndexedRead
zarlinkIndexedWrite??rA SYMBOL "??rA", zarlinkIndexedWrite
zarlinkStatusRead??rA SYMBOL "??rA", zarlinkStatusRead

        EXTERN cliRegisterCommand
        FUNCTION cliRegisterCommand,0202H
        EXTERN clicharGetOutputBuffer
        FUNCTION clicharGetOutputBuffer,0202H
        EXTERN clicharSendOutputBuffer
        FUNCTION clicharSendOutputBuffer,0202H
        EXTERN sprintf
        FUNCTION sprintf,010202H
        EXTERN strtol
        FUNCTION strtol,010202H
        EXTERN zarlinkIndexedRead
        FUNCTION zarlinkIndexedRead,0202H
        EXTERN zarlinkIndexedWrite
        FUNCTION zarlinkIndexedWrite,0202H
        EXTERN zarlinkStatusRead
        FUNCTION zarlinkStatusRead,0202H


        RSEG DATA_Z:DATA:SORT:NOROOT(2)
cpuMacAddr:
        DS8 8

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock0 Using cfiCommon0
        CFI Function byteSwap16
   CODE32      
byteSwap16:
   SUB         SP,SP,#+0x4
        CFI CFA R13+4
   MOV         R1,R0
   STRH        R1,[SP, #+0]
   LDRB        R12,[SP, #+0]
   MOV         R2,R12
   LDRB        R12,[SP, #+1]
   STRB        R12,[SP, #+0]
   STRB        R2,[SP, #+1]
   LDRH        R0,[SP, #+0]
   ADD         SP,SP,#+0x4        ;; stack cleaning
        CFI CFA R13+0
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock0

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock1 Using cfiCommon0
        CFI Function swapMac
   CODE32      
swapMac:
   CMP         R0,#+0x0
   BEQ         ??swapMac_0
   MOV         R3,#+0x0
   MOV         R1,R3
??swapMac_1:
   CMP         R1,#+0x3
   BGE         ??swapMac_0
   LDRB        R12,[R1, +R0]
   MOV         R2,R12
   RSB         R3,R1,#+0x0
   ADDS        R12,R3,R0
   LDRB        R3,[R12, #+5]
   STRB        R3,[R1, +R0]
   RSB         R12,R1,#+0x0
   ADDS        R3,R12,R0
   STRB        R2,[R3, #+5]
   ADDS        R1,R1,#+0x1
   B           ??swapMac_1
??swapMac_0:
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock1

        RSEG DATA_Z:DATA:SORT:NOROOT(2)
foo:
        DS8 16

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock2 Using cfiCommon0
        CFI Function parseDottedQuadV4
   CODE32      
parseDottedQuadV4:
   STMDB       SP!,{R4-R6,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R6 Frame(CFA, -8)
        CFI R5 Frame(CFA, -12)
        CFI R4 Frame(CFA, -16)
        CFI CFA R13+16
   MOV         R4,R0
   MOV         R5,R1
   MOV         R0,#+0x0
   MOV         R6,R0
   CMP         R4,#+0x0
   BEQ         ??parseDottedQuadV4_0
   CMP         R5,#+0x0
   BNE         ??parseDottedQuadV4_1
??parseDottedQuadV4_0:
   MVN         R0,#+0x0
   B           ??parseDottedQuadV4_2
??parseDottedQuadV4_1:
   MOV         R1,#+0x4
   LDR         R2,??parseDottedQuadV4_3  ;; foo
   MLAS        R3,R1,R6,R2
   STR         R4,[R3, #+0]
   ADDS        R6,R6,#+0x1
??parseDottedQuadV4_4:
   CMP         R6,#+0x4
   BGE         ??parseDottedQuadV4_5
   LDRB        R12,[R4, #+0]
   CMP         R12,#+0x0
   BEQ         ??parseDottedQuadV4_5
   LDRB        LR,[R4, #+0]
   CMP         LR,#+0x2E
   BNE         ??parseDottedQuadV4_6
   MOV         R0,#+0x0
   STRB        R0,[R4, #+0]
   ADDS        R4,R4,#+0x1
   MOV         R1,#+0x4
   LDR         R2,??parseDottedQuadV4_3  ;; foo
   MLAS        R3,R1,R6,R2
   STR         R4,[R3, #+0]
   ADDS        R6,R6,#+0x1
   B           ??parseDottedQuadV4_4
??parseDottedQuadV4_6:
   ADDS        R4,R4,#+0x1
   B           ??parseDottedQuadV4_4
??parseDottedQuadV4_5:
   CMP         R6,#+0x4
   BGE         ??parseDottedQuadV4_7
   MVN         R0,#+0x0
   B           ??parseDottedQuadV4_2
??parseDottedQuadV4_7:
   MOV         R12,#+0x0
   MOV         R6,R12
??parseDottedQuadV4_8:
   CMP         R6,#+0x5
   BGE         ??parseDottedQuadV4_9
   MOV         R2,#+0xA
   MOV         R1,#+0x0
   MOV         LR,#+0x4
   LDR         R0,??parseDottedQuadV4_3  ;; foo
   MLAS        R3,LR,R6,R0
   LDR         R0,[R3, #+0]
   _BLF        strtol,strtol??rA
   STRB        R0,[R6, +R5]
   ADDS        R6,R6,#+0x1
   B           ??parseDottedQuadV4_8
??parseDottedQuadV4_9:
   MOV         R0,#+0x0
??parseDottedQuadV4_2:
   LDMIA       SP!,{R4-R6,PC}     ;; return
   DATA        
??parseDottedQuadV4_3:
   DC32        foo
        CFI EndBlock cfiBlock2

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock3 Using cfiCommon0
        CFI Function zarlinkHandler
   CODE32      
zarlinkHandler:
   STMDB       SP!,{R4-R11,LR}    ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R11 Frame(CFA, -8)
        CFI R10 Frame(CFA, -12)
        CFI R9 Frame(CFA, -16)
        CFI R8 Frame(CFA, -20)
        CFI R7 Frame(CFA, -24)
        CFI R6 Frame(CFA, -28)
        CFI R5 Frame(CFA, -32)
        CFI R4 Frame(CFA, -36)
        CFI CFA R13+36
   SUB         SP,SP,#+0x8
        CFI CFA R13+44
   MOV         R8,R0
   MOV         R9,R1
   MOV         R10,R2
   MVN         R0,#+0x0
   MOV         R11,R0
   MOV         R0,SP
   _BLF        clicharGetOutputBuffer,clicharGetOutputBuffer??rA
   MOV         R7,R0
   LDR         R1,[R9, #+4]
   LDRB        R2,[R1, #+0]
   CMP         R2,#+0x2D
   BNE         ??zarlinkHandler_0
   LDR         R3,[R9, #+4]
   ADDS        R12,R3,#+0x1
   STR         R12,[R9, #+4]
??zarlinkHandler_0:
   LDR         LR,[R9, #+4]
   LDRB        R0,[LR, #+0]
   ANDS        R0,R0,#+0xFF       ;; Zero extend
   SUB         R0,R0,#+0x51
   CMP         R0,#+0x26
   BHI         ??zarlinkHandler_1
   ADR         R1,`?<Jumptable for zarlinkHandler>_0`
   LDRB        R1,[R1, R0]
   ADD         PC,PC,R1, LSL #+2
   DATA        
`?<Jumptable for zarlinkHandler>_0`:
   DC8         +0x9,+0x1E,+0x36,+0x61
   DC8         +0x61,+0x61,+0x42,+0x61
   DC8         +0x61,+0x61,+0x61,+0x61
   DC8         +0x61,+0x61,+0x61,+0x61
   DC8         +0x61,+0x61,+0x61,+0x61
   DC8         +0x61,+0x61,+0x61,+0x61
   DC8         +0x61,+0x61,+0x61,+0x61
   DC8         +0x61,+0x61,+0x61,+0x61
   DC8         +0x9,+0x1E,+0x36,+0x61
   DC8         +0x61,+0x61,+0x42,+0x0
   CODE32      
??zarlinkHandler_2:
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R9, #+8]
   _BLF        strtol,strtol??rA
   MOV         R5,R0
   MOV         R0,R5
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedRead,zarlinkIndexedRead??rA
   MOV         R6,R0
   MOV         R2,R6
   ANDS        R2,R2,#+0xFF       ;; Zero extend
   LDR         R1,??zarlinkHandler_3  ;; `?<Constant "0x%02x\\n">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   LDR         R1,[SP, #+0]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         R3,#+0x0
   MOV         R11,R3
   B           ??zarlinkHandler_1
??zarlinkHandler_4:
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R9, #+8]
   _BLF        strtol,strtol??rA
   MOV         R5,R0
   MOV         R0,R5
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedRead,zarlinkIndexedRead??rA
   MOV         R6,R0
   MOV         R3,R6
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   MOV         R2,R5
   MOV         R2,R2, LSL #+16
   MOVS        R2,R2, LSR #+16
   LDR         R1,??zarlinkHandler_3+4  ;; `?<Constant "zl reg[%04x] = %02x\\n">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   LDR         R1,[SP, #+0]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         LR,#+0x0
   MOV         R11,LR
   B           ??zarlinkHandler_1
??zarlinkHandler_5:
   _BLF        zarlinkStatusRead,zarlinkStatusRead??rA
   ANDS        R0,R0,#+0xFF       ;; Zero extend
   MOV         R2,R0
   LDR         R1,??zarlinkHandler_3+8  ;; `?<Constant "zl status[%02x]\\r\\n">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   LDR         R1,[SP, #+0]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         R1,#+0x0
   MOV         R11,R1
   B           ??zarlinkHandler_1
??zarlinkHandler_6:
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R9, #+8]
   _BLF        strtol,strtol??rA
   MOV         R5,R0
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R9, #+12]
   _BLF        strtol,strtol??rA
   MOV         R4,R0
   MOV         R2,R4
   MOV         R6,R2
   MOV         R1,R6
   ANDS        R1,R1,#+0xFF       ;; Zero extend
   MOV         R0,R5
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   MOV         R3,R6
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   MOV         R2,R5
   MOV         R2,R2, LSL #+16
   MOVS        R2,R2, LSR #+16
   LDR         R1,??zarlinkHandler_3+12  ;; `?<Constant "zl reg[%04x] <-- %02x\\n">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   LDR         R1,[SP, #+0]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         R12,#+0x0
   MOV         R11,R12
??zarlinkHandler_1:
   MOV         R0,R11
   ADD         SP,SP,#+0x8        ;; stack cleaning
        CFI CFA R13+36
   LDMIA       SP!,{R4-R11,PC}    ;; return
   DATA        
??zarlinkHandler_3:
   DC32        `?<Constant "0x%02x\\n">`
   DC32        `?<Constant "zl reg[%04x] = %02x\\n">`
   DC32        `?<Constant "zl status[%02x]\\r\\n">`
   DC32        `?<Constant "zl reg[%04x] <-- %02x\\n">`
        CFI EndBlock cfiBlock3

        RSEG DATA_Z:DATA:SORT:NOROOT(2)
qStats:
        DS8 12

        RSEG DATA_I:DATA:SORT:NOROOT(0)
yesBlar:
        DS8 8
	REQUIRE `?<Initializer for yesBlar>`

        RSEG DATA_I:DATA:SORT:NOROOT(0)
noBlar:
        DS8 8
	REQUIRE `?<Initializer for noBlar>`

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock4 Using cfiCommon0
        CFI Function quickStatHandler
   CODE32      
quickStatHandler:
   STMDB       SP!,{R4-R9,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R9 Frame(CFA, -8)
        CFI R8 Frame(CFA, -12)
        CFI R7 Frame(CFA, -16)
        CFI R6 Frame(CFA, -20)
        CFI R5 Frame(CFA, -24)
        CFI R4 Frame(CFA, -28)
        CFI CFA R13+28
   SUB         SP,SP,#+0x10
        CFI CFA R13+44
   MOV         R4,R0
   MOV         R5,R1
   MOV         R6,R2
   ADD         R0,SP,#+0x8
   _BLF        clicharGetOutputBuffer,clicharGetOutputBuffer??rA
   MOV         R7,R0
   LDR         R2,[R5, #+0]
   LDR         R1,??quickStatHandler_0  ;; `?<Constant "%s: Flow Ctrl[f]  FDX...">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   LDR         R1,[SP, #+8]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         R2,#+0x0
   STR         R2,[SP, #+0]
??quickStatHandler_1:
   LDR         R12,[SP, #+0]
   CMP         R12,#+0xA
   BGE         ??quickStatHandler_2
   LDR         R1,[SP, #+0]
   ANDS        R1,R1,#+0xFF       ;; Zero extend
   MOV         R0,#+0x3
   ORR         R0,R0,#+0xF00
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   LDR         R9,[SP, #+0]
   MOV         R0,#+0x4
   ORR         R0,R0,#+0xF00
   _BLF        zarlinkIndexedRead,zarlinkIndexedRead??rA
   LDR         R1,??quickStatHandler_0+4  ;; qStats
   STRB        R0,[R9, +R1]
   LDR         R2,[SP, #+0]
   ADD         R2,R2,#+0x1
   STR         R2,[SP, #+0]
   B           ??quickStatHandler_1
??quickStatHandler_2:
   MOV         R12,#+0x0
   STR         R12,[SP, #+0]
??quickStatHandler_3:
   LDR         R9,[SP, #+0]
   CMP         R9,#+0xA
   BGE         ??quickStatHandler_4
   LDR         R0,[SP, #+0]
   CMP         R0,#+0x8
   BNE         ??quickStatHandler_5
   LDR         R2,[SP, #+0]
   LDR         R1,??quickStatHandler_0+8  ;; `?<Constant "_cpu[%02x]  ">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   B           ??quickStatHandler_6
??quickStatHandler_5:
   LDR         R12,[SP, #+0]
   CMP         R12,#+0x9
   BNE         ??quickStatHandler_7
   LDR         R2,[SP, #+0]
   LDR         R1,??quickStatHandler_0+12  ;; `?<Constant "mmac[%02x]  ">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   B           ??quickStatHandler_6
??quickStatHandler_7:
   LDR         R2,[SP, #+0]
   LDR         R1,??quickStatHandler_0+16  ;; `?<Constant "port[%02x]  ">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
??quickStatHandler_6:
   MOV         R8,R7
??quickStatHandler_8:
   LDRB        R1,[R8, #+0]
   CMP         R1,#+0x20
   BEQ         ??quickStatHandler_9
   ADDS        R8,R8,#+0x1
   B           ??quickStatHandler_8
??quickStatHandler_9:
   ADDS        R8,R8,#+0x2
   MOV         R2,#+0x0
   STR         R2,[SP, #+4]
??quickStatHandler_10:
   LDR         R12,[SP, #+4]
   CMP         R12,#+0x8
   BGE         ??quickStatHandler_11
   LDR         R9,[SP, #+0]
   LDR         R1,??quickStatHandler_0+4  ;; qStats
   LDRB        R0,[R9, +R1]
   ANDS        R0,R0,#+0xFF       ;; Zero extend
   LDR         R3,[SP, #+4]
   MOV         R12,#+0x1
   TST         R12,R0, ASR R3
   BEQ         ??quickStatHandler_12
   LDR         R9,[SP, #+4]
   LDR         R1,??quickStatHandler_0+20  ;; yesBlar
   LDRB        R0,[R9, +R1]
   STRB        R0,[R8, #+0]
   ADDS        R8,R8,#+0x1
   B           ??quickStatHandler_13
??quickStatHandler_12:
   LDR         R3,[SP, #+4]
   LDR         R12,??quickStatHandler_0+24  ;; noBlar
   LDRB        LR,[R3, +R12]
   STRB        LR,[R8, #+0]
   ADDS        R8,R8,#+0x1
??quickStatHandler_13:
   LDR         R1,[SP, #+4]
   ADD         R1,R1,#+0x1
   STR         R1,[SP, #+4]
   B           ??quickStatHandler_10
??quickStatHandler_11:
   MOV         R0,#+0xD
   STRB        R0,[R8, #+0]
   ADDS        R8,R8,#+0x1
   MOV         R2,#+0xA
   STRB        R2,[R8, #+0]
   ADDS        R8,R8,#+0x1
   MOV         R3,#+0x0
   STRB        R3,[R8, #+0]
   LDR         R1,[SP, #+8]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   LDR         R9,[SP, #+0]
   ADD         R9,R9,#+0x1
   STR         R9,[SP, #+0]
   B           ??quickStatHandler_3
??quickStatHandler_4:
   MOV         R0,#+0x0
   ADD         SP,SP,#+0x10       ;; stack cleaning
        CFI CFA R13+28
   LDMIA       SP!,{R4-R9,PC}     ;; return
   DATA        
??quickStatHandler_0:
   DC32        `?<Constant "%s: Flow Ctrl[f]  FDX...">`
   DC32        qStats
   DC32        `?<Constant "_cpu[%02x]  ">`
   DC32        `?<Constant "mmac[%02x]  ">`
   DC32        `?<Constant "port[%02x]  ">`
   DC32        yesBlar
   DC32        noBlar
        CFI EndBlock cfiBlock4

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock5 Using cfiCommon0
        CFI Function zarlinkCpuMacAddrSet
   CODE32      
zarlinkCpuMacAddrSet:
   STMDB       SP!,{R4,R5,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R5 Frame(CFA, -8)
        CFI R4 Frame(CFA, -12)
        CFI CFA R13+12
   MOV         R4,R0
   CMP         R4,#+0x0
   BNE         ??zarlinkCpuMacAddrSet_0
   MVN         R0,#+0x0
   B           ??zarlinkCpuMacAddrSet_1
??zarlinkCpuMacAddrSet_0:
   MOV         R0,#+0x0
   MOV         R5,R0
??zarlinkCpuMacAddrSet_2:
   CMP         R5,#+0x6
   BGE         ??zarlinkCpuMacAddrSet_3
   RSB         R1,R5,#+0x0
   ADDS        R2,R1,R4
   LDRB        R1,[R2, #+5]
   MOV         R3,R5
   ADDS        R0,R3,#+0x300
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   ADDS        R5,R5,#+0x1
   B           ??zarlinkCpuMacAddrSet_2
??zarlinkCpuMacAddrSet_3:
   MOV         R0,#+0x0
??zarlinkCpuMacAddrSet_1:
   LDMIA       SP!,{R4,R5,PC}     ;; return
        CFI EndBlock cfiBlock5

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock6 Using cfiCommon0
        CFI Function zarlinkCpuMacAddrGet
   CODE32      
zarlinkCpuMacAddrGet:
   STMDB       SP!,{R4,R5,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R5 Frame(CFA, -8)
        CFI R4 Frame(CFA, -12)
        CFI CFA R13+12
   MOV         R4,R0
   CMP         R4,#+0x0
   BNE         ??zarlinkCpuMacAddrGet_0
   MVN         R0,#+0x0
   B           ??zarlinkCpuMacAddrGet_1
??zarlinkCpuMacAddrGet_0:
   MOV         R0,#+0x0
   MOV         R5,R0
??zarlinkCpuMacAddrGet_2:
   CMP         R5,#+0x6
   BGE         ??zarlinkCpuMacAddrGet_3
   MOV         R1,R5
   ADDS        R0,R1,#+0x300
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedRead,zarlinkIndexedRead??rA
   RSB         R2,R5,#+0x0
   ADDS        R3,R2,R4
   STRB        R0,[R3, #+5]
   ADDS        R5,R5,#+0x1
   B           ??zarlinkCpuMacAddrGet_2
??zarlinkCpuMacAddrGet_3:
   MOV         R0,#+0x0
??zarlinkCpuMacAddrGet_1:
   LDMIA       SP!,{R4,R5,PC}     ;; return
        CFI EndBlock cfiBlock6

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock7 Using cfiCommon0
        CFI Function setmacHandler
   CODE32      
setmacHandler:
   STMDB       SP!,{R4-R7,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R7 Frame(CFA, -8)
        CFI R6 Frame(CFA, -12)
        CFI R5 Frame(CFA, -16)
        CFI R4 Frame(CFA, -20)
        CFI CFA R13+20
   SUB         SP,SP,#+0x4
        CFI CFA R13+24
   MOV         R4,R0
   MOV         R5,R1
   MOV         R6,R2
   MOV         R0,SP
   _BLF        clicharGetOutputBuffer,clicharGetOutputBuffer??rA
   MOV         R7,R0
   CMP         R4,#+0x4
   BNE         ??setmacHandler_0
   LDR         R0,??setmacHandler_1  ;; cpuMacAddr
   MOV         R1,#+0x0
   STRB        R1,[R0, #+5]
   LDR         R2,??setmacHandler_1  ;; cpuMacAddr
   MOV         R3,#+0xC
   STRB        R3,[R2, #+4]
   LDR         R12,??setmacHandler_1  ;; cpuMacAddr
   MOV         LR,#+0x6A
   STRB        LR,[R12, #+3]
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R5, #+4]
   _BLF        strtol,strtol??rA
   LDR         R1,??setmacHandler_1  ;; cpuMacAddr
   STRB        R0,[R1, #+2]
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R5, #+8]
   _BLF        strtol,strtol??rA
   LDR         R2,??setmacHandler_1  ;; cpuMacAddr
   STRB        R0,[R2, #+1]
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R5, #+12]
   _BLF        strtol,strtol??rA
   LDR         R3,??setmacHandler_1  ;; cpuMacAddr
   STRB        R0,[R3, #+0]
   LDR         R0,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R3,[R0, #+0]
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   LDR         R12,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R2,[R12, #+1]
   ANDS        R2,R2,#+0xFF       ;; Zero extend
   LDR         LR,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R1,[LR, #+2]
   ANDS        R1,R1,#+0xFF       ;; Zero extend
   LDR         R0,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R0,[R0, #+3]
   ANDS        R0,R0,#+0xFF       ;; Zero extend
   STMDB       SP!,{R0-R3}        ;; Push
        CFI CFA R13+40
   LDR         R1,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R2,[R1, #+4]
   ANDS        R2,R2,#+0xFF       ;; Zero extend
   STMDB       SP!,{R2}           ;; Push
        CFI CFA R13+44
   LDR         R3,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R3,[R3, #+5]
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   LDR         R2,[R5, #+0]
   LDR         R1,??setmacHandler_1+4  ;; `?<Constant "%s: setting cpu MAC a...">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   ADD         SP,SP,#+0x14       ;; stack cleaning
        CFI CFA R13+24
   LDR         R0,??setmacHandler_1  ;; cpuMacAddr
   BL          zarlinkCpuMacAddrSet
   B           ??setmacHandler_2
??setmacHandler_0:
   CMP         R4,#+0x1
   BNE         ??setmacHandler_3
   LDR         R0,??setmacHandler_1  ;; cpuMacAddr
   BL          zarlinkCpuMacAddrGet
   LDR         R12,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R3,[R12, #+0]
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   LDR         LR,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R2,[LR, #+1]
   ANDS        R2,R2,#+0xFF       ;; Zero extend
   LDR         R0,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R1,[R0, #+2]
   ANDS        R1,R1,#+0xFF       ;; Zero extend
   LDR         R12,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R0,[R12, #+3]
   ANDS        R0,R0,#+0xFF       ;; Zero extend
   STMDB       SP!,{R0-R3}        ;; Push
        CFI CFA R13+40
   LDR         R1,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R2,[R1, #+4]
   ANDS        R2,R2,#+0xFF       ;; Zero extend
   STMDB       SP!,{R2}           ;; Push
        CFI CFA R13+44
   LDR         R3,??setmacHandler_1  ;; cpuMacAddr
   LDRB        R3,[R3, #+5]
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   LDR         R2,[R5, #+0]
   LDR         R1,??setmacHandler_1+8  ;; `?<Constant "%s: cpu MAC address i...">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   ADD         SP,SP,#+0x14       ;; stack cleaning
        CFI CFA R13+24
   B           ??setmacHandler_2
??setmacHandler_3:
   MVN         R0,#+0x0
   B           ??setmacHandler_4
??setmacHandler_2:
   LDR         R1,[SP, #+0]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         R0,#+0x0
??setmacHandler_4:
   ADD         SP,SP,#+0x4        ;; stack cleaning
        CFI CFA R13+20
   LDMIA       SP!,{R4-R7,PC}     ;; return
   DATA        
??setmacHandler_1:
   DC32        cpuMacAddr
   DC32        `?<Constant "%s: setting cpu MAC a...">`
   DC32        `?<Constant "%s: cpu MAC address i...">`
        CFI EndBlock cfiBlock7

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock8 Using cfiCommon0
        CFI Function pupHandler
   CODE32      
pupHandler:
   STMDB       SP!,{R4-R8,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R8 Frame(CFA, -8)
        CFI R7 Frame(CFA, -12)
        CFI R6 Frame(CFA, -16)
        CFI R5 Frame(CFA, -20)
        CFI R4 Frame(CFA, -24)
        CFI CFA R13+24
   SUB         SP,SP,#+0x4
        CFI CFA R13+28
   MOV         R4,R0
   MOV         R5,R1
   MOV         R6,R2
   CMP         R4,#+0x2
   BGE         ??pupHandler_0
   MVN         R0,#+0x0
   B           ??pupHandler_1
??pupHandler_0:
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R5, #+4]
   _BLF        strtol,strtol??rA
   MOV         R8,R0
   ANDS        R8,R8,#+0xF
   MOV         R0,SP
   _BLF        clicharGetOutputBuffer,clicharGetOutputBuffer??rA
   MOV         R7,R0
   MOV         R3,R8
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   LDR         R2,[R5, #+0]
   LDR         R1,??pupHandler_2  ;; `?<Constant "%s: forcing port [%02...">`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   LDR         R1,[SP, #+0]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         R1,#+0xD8
   MOV         R2,R8
   ANDS        R2,R2,#+0xFF       ;; Zero extend
   MOV         R3,#+0x2
   MULS        R0,R3,R2
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   MOV         R0,#+0x0
??pupHandler_1:
   ADD         SP,SP,#+0x4        ;; stack cleaning
        CFI CFA R13+24
   LDMIA       SP!,{R4-R8,PC}     ;; return
   DATA        
??pupHandler_2:
   DC32        `?<Constant "%s: forcing port [%02...">`
        CFI EndBlock cfiBlock8

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock9 Using cfiCommon0
        CFI Function pdownHandler
   CODE32      
pdownHandler:
   STMDB       SP!,{R4-R8,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R8 Frame(CFA, -8)
        CFI R7 Frame(CFA, -12)
        CFI R6 Frame(CFA, -16)
        CFI R5 Frame(CFA, -20)
        CFI R4 Frame(CFA, -24)
        CFI CFA R13+24
   SUB         SP,SP,#+0x4
        CFI CFA R13+28
   MOV         R4,R0
   MOV         R5,R1
   MOV         R6,R2
   CMP         R4,#+0x2
   BGE         ??pdownHandler_0
   MVN         R0,#+0x0
   B           ??pdownHandler_1
??pdownHandler_0:
   MOV         R2,#+0x10
   MOV         R1,#+0x0
   LDR         R0,[R5, #+4]
   _BLF        strtol,strtol??rA
   MOV         R8,R0
   ANDS        R8,R8,#+0xF
   MOV         R0,SP
   _BLF        clicharGetOutputBuffer,clicharGetOutputBuffer??rA
   MOV         R7,R0
   MOV         R3,R8
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   LDR         R2,[R5, #+0]
   LDR         R1,??pdownHandler_2  ;; `?<Constant "%s: forcing port [%02...">_1`
   MOV         R0,R7
   _BLF        sprintf,sprintf??rA
   LDR         R1,[SP, #+0]
   MOV         R0,R7
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         R1,#+0xD0
   MOV         R2,R8
   ANDS        R2,R2,#+0xFF       ;; Zero extend
   MOV         R3,#+0x2
   MULS        R0,R3,R2
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   MOV         R0,#+0x0
??pdownHandler_1:
   ADD         SP,SP,#+0x4        ;; stack cleaning
        CFI CFA R13+24
   LDMIA       SP!,{R4-R8,PC}     ;; return
   DATA        
??pdownHandler_2:
   DC32        `?<Constant "%s: forcing port [%02...">_1`
        CFI EndBlock cfiBlock9

        RSEG DATA_Z:DATA:SORT:NOROOT(2)
pdqTestArray:
        DS8 4

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock10 Using cfiCommon0
        CFI Function pdqTestHandler
   CODE32      
pdqTestHandler:
   STMDB       SP!,{R4-R8,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R8 Frame(CFA, -8)
        CFI R7 Frame(CFA, -12)
        CFI R6 Frame(CFA, -16)
        CFI R5 Frame(CFA, -20)
        CFI R4 Frame(CFA, -24)
        CFI CFA R13+24
   SUB         SP,SP,#+0x10
        CFI CFA R13+40
   MOV         R5,R0
   MOV         R6,R1
   MOV         R7,R2
   MVN         R0,#+0x0
   MOV         R8,R0
   CMP         R5,#+0x2
   BEQ         ??pdqTestHandler_0
   MVN         R0,#+0x0
   B           ??pdqTestHandler_1
??pdqTestHandler_0:
   MOV         R0,SP
   _BLF        clicharGetOutputBuffer,clicharGetOutputBuffer??rA
   MOV         R4,R0
   LDR         R1,??pdqTestHandler_2  ;; pdqTestArray
   LDR         R0,[R6, #+4]
   BL          parseDottedQuadV4
   CMP         R0,#+0x0
   BNE         ??pdqTestHandler_3
   LDR         R1,??pdqTestHandler_2  ;; pdqTestArray
   LDRB        R2,[R1, #+3]
   ANDS        R2,R2,#+0xFF       ;; Zero extend
   LDR         R3,??pdqTestHandler_2  ;; pdqTestArray
   LDRB        R1,[R3, #+2]
   ANDS        R1,R1,#+0xFF       ;; Zero extend
   LDR         R12,??pdqTestHandler_2  ;; pdqTestArray
   LDRB        R0,[R12, #+1]
   ANDS        R0,R0,#+0xFF       ;; Zero extend
   STMDB       SP!,{R0-R2}        ;; Push
        CFI CFA R13+52
   LDR         R2,??pdqTestHandler_2  ;; pdqTestArray
   LDRB        R3,[R2, #+0]
   ANDS        R3,R3,#+0xFF       ;; Zero extend
   LDR         R2,[R6, #+0]
   LDR         R1,??pdqTestHandler_2+4  ;; `?<Constant "%s: IP Addr is [%02x]...">`
   MOV         R0,R4
   _BLF        sprintf,sprintf??rA
   ADD         SP,SP,#+0xC        ;; stack cleaning
        CFI CFA R13+40
   LDR         R1,[SP, #+0]
   MOV         R0,R4
   _BLF        clicharSendOutputBuffer,clicharSendOutputBuffer??rA
   MOV         R0,#+0x0
   MOV         R8,R0
   B           ??pdqTestHandler_4
??pdqTestHandler_3:
   MVN         R1,#+0x1
   MOV         R8,R1
??pdqTestHandler_4:
   MOV         R0,R8
??pdqTestHandler_1:
   ADD         SP,SP,#+0x10       ;; stack cleaning
        CFI CFA R13+24
   LDMIA       SP!,{R4-R8,PC}     ;; return
   DATA        
??pdqTestHandler_2:
   DC32        pdqTestArray
   DC32        `?<Constant "%s: IP Addr is [%02x]...">`
        CFI EndBlock cfiBlock10

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock11 Using cfiCommon0
        CFI Function zarlinkUtilInit
   CODE32      
zarlinkUtilInit:
   STMDB       SP!,{LR}           ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI CFA R13+4
   LDR         R2,??zarlinkUtilInit_0  ;; `?<Constant "zl [read <index>] [wr...">`
   LDR         R1,??zarlinkUtilInit_0+4  ;; zarlinkHandler
   LDR         R0,??zarlinkUtilInit_0+8  ;; `?<Constant "zl">`
   _BLF        cliRegisterCommand,cliRegisterCommand??rA
   LDR         R2,??zarlinkUtilInit_0+12  ;; `?<Constant "qstat [port] - retrie...">`
   LDR         R1,??zarlinkUtilInit_0+16  ;; quickStatHandler
   LDR         R0,??zarlinkUtilInit_0+20  ;; `?<Constant "quick">`
   _BLF        cliRegisterCommand,cliRegisterCommand??rA
   LDR         R2,??zarlinkUtilInit_0+24  ;; `?<Constant "setmac [m2] [m1] [m0]...">`
   LDR         R1,??zarlinkUtilInit_0+28  ;; setmacHandler
   LDR         R0,??zarlinkUtilInit_0+32  ;; `?<Constant "setmac">`
   _BLF        cliRegisterCommand,cliRegisterCommand??rA
   LDR         R2,??zarlinkUtilInit_0+36  ;; `?<Constant "getmac - displays the...">`
   LDR         R1,??zarlinkUtilInit_0+28  ;; setmacHandler
   LDR         R0,??zarlinkUtilInit_0+40  ;; `?<Constant "getmac">`
   _BLF        cliRegisterCommand,cliRegisterCommand??rA
   LDR         R2,??zarlinkUtilInit_0+44  ;; `?<Constant "pup [port] - forces p...">`
   LDR         R1,??zarlinkUtilInit_0+48  ;; pupHandler
   LDR         R0,??zarlinkUtilInit_0+52  ;; `?<Constant "pup">`
   _BLF        cliRegisterCommand,cliRegisterCommand??rA
   LDR         R2,??zarlinkUtilInit_0+56  ;; `?<Constant "pdown [port] - forces...">`
   LDR         R1,??zarlinkUtilInit_0+60  ;; pdownHandler
   LDR         R0,??zarlinkUtilInit_0+64  ;; `?<Constant "pdown">`
   _BLF        cliRegisterCommand,cliRegisterCommand??rA
   LDR         R2,??zarlinkUtilInit_0+68  ;; `?<Constant "pdqtest [dotted quad ...">`
   LDR         R1,??zarlinkUtilInit_0+72  ;; pdqTestHandler
   LDR         R0,??zarlinkUtilInit_0+76  ;; `?<Constant "pdqtest">`
   _BLF        cliRegisterCommand,cliRegisterCommand??rA
   MOV         R0,#+0x0
   LDMIA       SP!,{PC}           ;; return
   DATA        
??zarlinkUtilInit_0:
   DC32        `?<Constant "zl [read <index>] [wr...">`
   DC32        zarlinkHandler
   DC32        `?<Constant "zl">`
   DC32        `?<Constant "qstat [port] - retrie...">`
   DC32        quickStatHandler
   DC32        `?<Constant "quick">`
   DC32        `?<Constant "setmac [m2] [m1] [m0]...">`
   DC32        setmacHandler
   DC32        `?<Constant "setmac">`
   DC32        `?<Constant "getmac - displays the...">`
   DC32        `?<Constant "getmac">`
   DC32        `?<Constant "pup [port] - forces p...">`
   DC32        pupHandler
   DC32        `?<Constant "pup">`
   DC32        `?<Constant "pdown [port] - forces...">`
   DC32        pdownHandler
   DC32        `?<Constant "pdown">`
   DC32        `?<Constant "pdqtest [dotted quad ...">`
   DC32        pdqTestHandler
   DC32        `?<Constant "pdqtest">`
        CFI EndBlock cfiBlock11

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock12 Using cfiCommon0
        CFI NoFunction
   CODE32      
strtol??rA:
   LDR         R12,??Subroutine0_0  ;; strtol
   MOV         PC,R12
   DATA        
??Subroutine0_0:
   DC32        strtol
        CFI EndBlock cfiBlock12

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock13 Using cfiCommon0
        CFI NoFunction
   CODE32      
clicharGetOutputBuffer??rA:
   LDR         R12,??Subroutine1_0  ;; clicharGetOutputBuffer
   MOV         PC,R12
   DATA        
??Subroutine1_0:
   DC32        clicharGetOutputBuffer
        CFI EndBlock cfiBlock13

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock14 Using cfiCommon0
        CFI NoFunction
   CODE32      
zarlinkIndexedRead??rA:
   LDR         R12,??Subroutine2_0  ;; zarlinkIndexedRead
   MOV         PC,R12
   DATA        
??Subroutine2_0:
   DC32        zarlinkIndexedRead
        CFI EndBlock cfiBlock14

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock15 Using cfiCommon0
        CFI NoFunction
   CODE32      
sprintf??rA:
   LDR         R12,??Subroutine3_0  ;; sprintf
   MOV         PC,R12
   DATA        
??Subroutine3_0:
   DC32        sprintf
        CFI EndBlock cfiBlock15

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock16 Using cfiCommon0
        CFI NoFunction
   CODE32      
clicharSendOutputBuffer??rA:
   LDR         R12,??Subroutine4_0  ;; clicharSendOutputBuffer
   MOV         PC,R12
   DATA        
??Subroutine4_0:
   DC32        clicharSendOutputBuffer
        CFI EndBlock cfiBlock16

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock17 Using cfiCommon0
        CFI NoFunction
   CODE32      
zarlinkStatusRead??rA:
   LDR         R12,??Subroutine5_0  ;; zarlinkStatusRead
   MOV         PC,R12
   DATA        
??Subroutine5_0:
   DC32        zarlinkStatusRead
        CFI EndBlock cfiBlock17

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock18 Using cfiCommon0
        CFI NoFunction
   CODE32      
zarlinkIndexedWrite??rA:
   LDR         R12,??Subroutine6_0  ;; zarlinkIndexedWrite
   MOV         PC,R12
   DATA        
??Subroutine6_0:
   DC32        zarlinkIndexedWrite
        CFI EndBlock cfiBlock18

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock19 Using cfiCommon0
        CFI NoFunction
   CODE32      
cliRegisterCommand??rA:
   LDR         R12,??Subroutine7_0  ;; cliRegisterCommand
   MOV         PC,R12
   DATA        
??Subroutine7_0:
   DC32        cliRegisterCommand
        CFI EndBlock cfiBlock19

        RSEG DATA_ID:CONST:SORT:NOROOT(0)
`?<Initializer for yesBlar>`:
        DC8 70, 68, 83, 68, 65, 46, 46, 77

        RSEG DATA_ID:CONST:SORT:NOROOT(0)
`?<Initializer for noBlar>`:
        DC8 102, 100, 115, 100, 97, 46, 46, 109

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?*?DATA_ID`:

        RSEG INITTAB:CODE:ROOT(2)
   DATA
?init?tab?DATA_I:
   DCD      sfe(DATA_I) - sfb(DATA_I), sfb(DATA_I), sfb(DATA_ID)

        RSEG INITTAB:CODE:ROOT(2)
   DATA
?init?tab?DATA_Z:
   DCD      sfe(DATA_Z) - sfb(DATA_Z), sfb(DATA_Z), sfb(DATA_Z)

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "%s: forcing port [%02...">`:
        DC8 "%s: forcing port [%02x] up at 100MBps/FDX\015\012"

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "pup">`:
        DC8 "pup"

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "pup [port] - forces p...">`:
        DC8 "pup [port] - forces port up at 100Mbps/FDX"
        DC8 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "pdown">`:
        DC8 "pdown"
        DC8 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "pdown [port] - forces...">`:
        DC8 "pdown [port] - forces port up at 100Mbps/FDX"
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "pdqtest">`:
        DC8 "pdqtest"

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "0x%02x\\n">`:
        DC8 "0x%02x\012"

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "zl reg[%04x] = %02x\\n">`:
        DC8 "zl reg[%04x] = %02x\012"
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "zl status[%02x]\\r\\n">`:
        DC8 "zl status[%02x]\015\012"
        DC8 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "zl reg[%04x] <-- %02x\\n">`:
        DC8 "zl reg[%04x] <-- %02x\012"
        DC8 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "%s: Flow Ctrl[f]  FDX...">`:
        DC8 25H, 73H, 3AH, 20H, 46H, 6CH, 6FH, 77H
        DC8 20H, 43H, 74H, 72H, 6CH, 5BH, 66H, 5DH
        DC8 20H, 20H, 46H, 44H, 58H, 5BH, 64H, 5DH
        DC8 20H, 20H, 46H, 61H, 73H, 74H, 5BH, 73H
        DC8 5DH, 20H, 20H, 4CH, 69H, 6EH, 6BH, 20H
        DC8 44H, 6FH, 77H, 6EH, 5BH, 64H, 5DH, 20H
        DC8 20H, 41H, 75H, 74H, 6FH, 6EH, 65H, 67H
        DC8 5BH, 61H, 5DH, 20H, 20H, 4DH, 6FH, 64H
        DC8 75H, 6CH, 65H, 5BH, 6DH, 5DH, 0DH, 0AH
        DC8 0
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "_cpu[%02x]  ">`:
        DC8 "_cpu[%02x]  "
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "mmac[%02x]  ">`:
        DC8 "mmac[%02x]  "
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "port[%02x]  ">`:
        DC8 "port[%02x]  "
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "%s: setting cpu MAC a...">`:
        DC8 25H, 73H, 3AH, 20H, 73H, 65H, 74H, 74H
        DC8 69H, 6EH, 67H, 20H, 63H, 70H, 75H, 20H
        DC8 4DH, 41H, 43H, 20H, 61H, 64H, 64H, 72H
        DC8 65H, 73H, 73H, 20H, 74H, 6FH, 20H, 25H
        DC8 30H, 32H, 78H, 3AH, 25H, 30H, 32H, 78H
        DC8 3AH, 25H, 30H, 32H, 78H, 3AH, 25H, 30H
        DC8 32H, 78H, 3AH, 25H, 30H, 32H, 78H, 3AH
        DC8 25H, 30H, 32H, 78H, 0DH, 0AH, 0
        DC8 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "%s: cpu MAC address i...">`:
        DC8 25H, 73H, 3AH, 20H, 63H, 70H, 75H, 20H
        DC8 4DH, 41H, 43H, 20H, 61H, 64H, 64H, 72H
        DC8 65H, 73H, 73H, 20H, 69H, 73H, 20H, 25H
        DC8 30H, 32H, 78H, 3AH, 25H, 30H, 32H, 78H
        DC8 3AH, 25H, 30H, 32H, 78H, 3AH, 25H, 30H
        DC8 32H, 78H, 3AH, 25H, 30H, 32H, 78H, 3AH
        DC8 25H, 30H, 32H, 78H, 0DH, 0AH, 0
        DC8 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "pdqtest [dotted quad ...">`:
        DC8 70H, 64H, 71H, 74H, 65H, 73H, 74H, 20H
        DC8 5BH, 64H, 6FH, 74H, 74H, 65H, 64H, 20H
        DC8 71H, 75H, 61H, 64H, 20H, 49H, 50H, 20H
        DC8 61H, 64H, 64H, 72H, 5DH, 20H, 2DH, 20H
        DC8 74H, 65H, 73H, 74H, 20H, 49H, 50H, 20H
        DC8 41H, 64H, 64H, 72H, 20H, 70H, 61H, 72H
        DC8 73H, 69H, 6EH, 67H, 0
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "%s: forcing port [%02...">_1`:
        DC8 "%s: forcing port [%02x] down\015\012"
        DC8 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "%s: IP Addr is [%02x]...">`:
        DC8 "%s: IP Addr is [%02x] [%02x] [%02x] [%02x]\015\012"
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(0)
`?<Constant "zl">`:
        DC8 "zl"

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "zl [read <index>] [wr...">`:
        DC8 "zl [read <index>] [write <index> <hex data>]"
        DC8 0, 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "quick">`:
        DC8 "quick"
        DC8 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "qstat [port] - retrie...">`:
        DC8 71H, 73H, 74H, 61H, 74H, 20H, 5BH, 70H
        DC8 6FH, 72H, 74H, 5DH, 20H, 2DH, 20H, 72H
        DC8 65H, 74H, 72H, 69H, 65H, 76H, 65H, 20H
        DC8 71H, 75H, 69H, 63H, 6BH, 20H, 70H, 6FH
        DC8 72H, 74H, 20H, 73H, 74H, 61H, 74H, 75H
        DC8 73H, 20H, 66H, 72H, 6FH, 6DH, 20H, 73H
        DC8 77H, 69H, 74H, 63H, 68H, 0
        DC8 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "setmac">`:
        DC8 "setmac"
        DC8 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "setmac [m2] [m1] [m0]...">`:
        DC8 73H, 65H, 74H, 6DH, 61H, 63H, 20H, 5BH
        DC8 6DH, 32H, 5DH, 20H, 5BH, 6DH, 31H, 5DH
        DC8 20H, 5BH, 6DH, 30H, 5DH, 20H, 2DH, 20H
        DC8 73H, 65H, 74H, 73H, 20H, 43H, 50H, 55H
        DC8 20H, 4DH, 41H, 43H, 20H, 61H, 64H, 64H
        DC8 72H, 65H, 73H, 73H, 20H, 74H, 6FH, 20H
        DC8 30H, 30H, 3AH, 30H, 63H, 3AH, 36H, 61H
        DC8 3AH, 6DH, 32H, 3AH, 6DH, 31H, 3AH, 6DH
        DC8 30H, 0
        DC8 0, 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "getmac">`:
        DC8 "getmac"
        DC8 0

        RSEG DATA_C:CONST:SORT:NOROOT(2)
`?<Constant "getmac - displays the...">`:
        DC8 "getmac - displays the current CPU MAC address "
        DC8 0

        END
// 
// 2 756 bytes in segment CODE
//   859 bytes in segment DATA_C
//    16 bytes in segment DATA_I
//    16 bytes in segment DATA_ID
//    40 bytes in segment DATA_Z
//    24 bytes in segment INITTAB
// 
// 2 660 bytes of CODE  memory (+ 120 bytes shared)
//   875 bytes of CONST memory
//    56 bytes of DATA  memory
//
//Errors: none
//Warnings: 7
