//////////////////////////////////////////////////////////////////////////////
//                                                                           /
// IAR ARM ANSI C/C++ Compiler V4.11A/W32              20/Jul/2004  18:58:47 /
// Copyright 1999-2004 IAR Systems. All rights reserved.                     /
//                                                                           /
//    Cpu mode        =  arm                                                 /
//    Endian          =  little                                              /
//    Stack alignment =  4                                                   /
//    Source file     =  C:\medusa\timer0.c                                  /
//    Command line    =  -I "C:\Program Files\IAR Systems\Embedded           /
//                       Workbench 4.0\ARM\INC\" -lc C:\medusa\Debug\List\   /
//                       -la C:\medusa\Debug\List\ -o C:\medusa\Debug\Obj\   /
//                       -s2 --no_cse --no_unroll --no_inline                /
//                       --no_code_motion --no_tbaa --no_clustering          /
//                       --no_scheduling --debug --cpu_mode arm --endian     /
//                       little --cpu ARM7TDMI-S --stack_align 4 -e --fpu    /
//                       None "-D_DLIB_CONFIG_FILE=C:\Program Files\IAR      /
//                       Systems\Embedded Workbench                          /
//                       4.0\ARM\LIB\dl4tpannl8n.h" C:\medusa\timer0.c       /
//    List file       =  C:\medusa\Debug\List\timer0.s79                     /
//                                                                           /
//                                                                           /
//////////////////////////////////////////////////////////////////////////////

        NAME timer0

        RTMODEL "ARMv4M", "USED"
        RTMODEL "StackAlign4", "USED"
        RTMODEL "__cpu_mode", "__pcs__arm"
        RTMODEL "__data_model", "absolute"
        RTMODEL "__endian", "little"
        RTMODEL "__rt_version", "6"

        RSEG CSTACK:DATA:NOROOT(2)
        RSEG IRQSTACK:DATA:NOROOT(2)

        EXTERN ??divu32_a

        MULTWEAK ??rA??divu32_a
        PUBWEAK ?init?tab?DATA_Z
        MULTWEAK armvicIntConnect??rA
        MULTWEAK armvicIntEnable??rA
        MULTWEAK boardTimerLedToggle??rA
        MULTWEAK pllGetPeriphDivider??rA
        PUBLIC timer0Delay
        FUNCTION timer0Delay,0203H
        LOCFRAME CSTACK, 4, STACK
        PUBLIC timer0Init
        FUNCTION timer0Init,0203H
        LOCFRAME CSTACK, 12, STACK
        FUNCTION timer0Match0Isr,0603H
        LOCFRAME CSTACK, 20, STACK
        
        CFI Names cfiNames0
        CFI StackFrame CFA R13 HUGEDATA
        CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
        CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13:32
        CFI Resource R14:32, SPSR:32
        CFI VirtualResource ?RET:32
        CFI EndNames cfiNames0
        
        CFI Common cfiCommon0 Using cfiNames0
        CFI CodeAlign 4
        CFI DataAlign 4
        CFI ReturnAddress ?RET CODE
        CFI CFA R13+0
        CFI R0 Undefined
        CFI R1 Undefined
        CFI R2 Undefined
        CFI R3 Undefined
        CFI R4 SameValue
        CFI R5 SameValue
        CFI R6 SameValue
        CFI R7 SameValue
        CFI R8 SameValue
        CFI R9 SameValue
        CFI R10 SameValue
        CFI R11 SameValue
        CFI R12 Undefined
        CFI CPSR SameValue
        CFI R14 Undefined
        CFI SPSR SameValue
        CFI ?RET R14
        CFI EndCommon cfiCommon0
        
        
        CFI Names cfiNames1
        CFI StackFrame CFA_R13_usr R13_usr HUGEDATA
        CFI StackFrame CFA_R13_irq R13_irq HUGEDATA
        CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
        CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13_usr:32
        CFI Resource R14_usr:32, R13_irq:32, R14_irq:32, SPSR_irq:32
        CFI VirtualResource ?RET:32
        CFI EndNames cfiNames1
        
        CFI Common cfiCommon1 Using cfiNames1
        CFI CodeAlign 4
        CFI DataAlign 4
        CFI ReturnAddress ?RET CODE
        CFI CFA_R13_usr R13_usr+0
        CFI CFA_R13_irq R13_irq+0
        CFI R0 SameValue
        CFI R1 SameValue
        CFI R2 SameValue
        CFI R3 SameValue
        CFI R4 SameValue
        CFI R5 SameValue
        CFI R6 SameValue
        CFI R7 SameValue
        CFI R8 SameValue
        CFI R9 SameValue
        CFI R10 SameValue
        CFI R11 SameValue
        CFI R12 SameValue
        CFI CPSR SPSR_irq
        CFI R14_usr SameValue
        CFI R14_irq Undefined
        CFI SPSR_irq Undefined
        CFI ?RET add(R14_irq, literal(-4))
        CFI EndCommon cfiCommon1
        
armvicIntConnect    SYMBOL "armvicIntConnect"
armvicIntEnable     SYMBOL "armvicIntEnable"
boardTimerLedToggle SYMBOL "boardTimerLedToggle"
pllGetPeriphDivider SYMBOL "pllGetPeriphDivider"
armvicIntConnect??rA SYMBOL "??rA", armvicIntConnect
armvicIntEnable??rA SYMBOL "??rA", armvicIntEnable
boardTimerLedToggle??rA SYMBOL "??rA", boardTimerLedToggle
pllGetPeriphDivider??rA SYMBOL "??rA", pllGetPeriphDivider

        EXTERN armvicIntConnect
        FUNCTION armvicIntConnect,0202H
        EXTERN armvicIntEnable
        FUNCTION armvicIntEnable,0202H
        EXTERN boardTimerLedToggle
        FUNCTION boardTimerLedToggle,0202H
        EXTERN pllGetPeriphDivider
        FUNCTION pllGetPeriphDivider,0202H


        RSEG DATA_Z:DATA:SORT:NOROOT(2)
tickCounter:
        DS8 4

        RSEG DATA_Z:DATA:SORT:NOROOT(2)
isrEntry:
        DS8 4

        RSEG DATA_Z:DATA:SORT:NOROOT(2)
delayTicks:
        DS8 4

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock0 Using cfiCommon0
        CFI Function timer0Init
   CODE32      
timer0Init:
   STMDB       SP!,{R4,R5,LR}     ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R5 Frame(CFA, -8)
        CFI R4 Frame(CFA, -12)
        CFI CFA R13+12
   _BLF        pllGetPeriphDivider,pllGetPeriphDivider??rA
   MOV         R5,R0
   MOV         R0,#+0xE0000004
   ORR         R0,R0,#+0x4000
   MOV         R1,#+0x0
   STR         R1,[R0, #+0]
   MOV         R2,#+0xE0000008
   ORR         R2,R2,#+0x4000
   MOV         R3,#+0x0
   STR         R3,[R2, #+0]
   LDR         R12,??timer0Init_0  ;; 0xe0004010
   MOV         LR,#+0x0
   STR         LR,[R12, #+0]
   MOV         R2,#+0xE000000C
   ORR         R2,R2,#+0x4000
   MOV         R0,#+0x60
   ORR         R0,R0,#+0xEA00
   MOV         R1,R5
   _BLF        ??divu32_a,??rA??divu32_a
   STR         R1,[R2, #+0]
   LDR         R0,??timer0Init_0+4  ;; 0xe0004018
   MOV         R1,#+0x64
   STR         R1,[R0, #+0]
   LDR         R3,??timer0Init_0+8  ;; 0xe0004014
   MOV         R12,#+0x3
   STR         R12,[R3, #+0]
   LDR         R1,??timer0Init_0+12  ;; timer0Match0Isr
   MOV         R0,#+0x4
   _BLF        armvicIntConnect,armvicIntConnect??rA
   MOV         R4,R0
   CMP         R0,#+0x0
   BEQ         ??timer0Init_1
   MOV         R0,R4
   B           ??timer0Init_2
??timer0Init_1:
   MOV         R0,#+0x4
   _BLF        armvicIntEnable,armvicIntEnable??rA
   MOV         R4,R0
   CMP         R0,#+0x0
   BEQ         ??timer0Init_3
   MOV         R0,R4
   B           ??timer0Init_2
??timer0Init_3:
   MOV         LR,#+0xE0000004
   ORR         LR,LR,#+0x4000
   MOV         R2,#+0x1
   STR         R2,[LR, #+0]
   MOV         R0,#+0x0
??timer0Init_2:
   LDMIA       SP!,{R4,R5,PC}     ;; return
   DATA        
??timer0Init_0:
   DC32        0xe0004010
   DC32        0xe0004018
   DC32        0xe0004014
   DC32        timer0Match0Isr
        CFI EndBlock cfiBlock0

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock1 Using cfiCommon1
        CFI Function timer0Match0Isr
   CODE32      
timer0Match0Isr:
   SUB         LR,LR,#+0x4
        CFI ?RET R14_irq
   STMDB       SP!,{LR}
        CFI ?RET Frame(CFA_R13_irq, -4)
        CFI CFA_R13_irq R13_irq+4
   MRS         LR,SPSR
        CFI SPSR_irq R14_irq
   STMDB       SP!,{R12,LR}
        CFI R14_irq Frame(CFA_R13_irq, -8)
        CFI R12 Frame(CFA_R13_irq, -12)
        CFI CFA_R13_irq R13_irq+12
   MRS         LR,CPSR
   ORR         LR,LR,#+0x1F
   MSR         CPSR,LR
   STMDB       SP!,{R0-R3,LR}     ;; Push
        CFI R14_usr Frame(CFA_R13_usr, -4)
        CFI R3 Frame(CFA_R13_usr, -8)
        CFI R2 Frame(CFA_R13_usr, -12)
        CFI R1 Frame(CFA_R13_usr, -16)
        CFI R0 Frame(CFA_R13_usr, -20)
        CFI CFA_R13_usr R13_usr+20
   LDR         R0,??timer0Match0Isr_0  ;; isrEntry
   LDR         R1,??timer0Match0Isr_0  ;; isrEntry
   LDR         R1,[R1, #+0]
   ADDS        R1,R1,#+0x1
   STR         R1,[R0, #+0]
   MOV         R0,#+0xE0000000
   ORR         R0,R0,#+0x4000
   MOV         R1,#+0xFF
   STR         R1,[R0, #+0]
   LDR         R0,??timer0Match0Isr_0+4  ;; delayTicks
   LDR         R1,[R0, #+0]
   CMP         R1,#+0x0
   BEQ         ??timer0Match0Isr_1
   LDR         R0,??timer0Match0Isr_0+4  ;; delayTicks
   LDR         R1,??timer0Match0Isr_0+4  ;; delayTicks
   LDR         R1,[R1, #+0]
   SUBS        R1,R1,#+0x1
   STR         R1,[R0, #+0]
??timer0Match0Isr_1:
   LDR         R0,??timer0Match0Isr_0+8  ;; tickCounter
   LDR         R1,[R0, #+0]
   ADDS        R0,R1,#+0x1
   LDR         R1,??timer0Match0Isr_0+8  ;; tickCounter
   STR         R0,[R1, #+0]
   CMP         R0,#+0x5
   BNE         ??timer0Match0Isr_2
   _BLF        boardTimerLedToggle,boardTimerLedToggle??rA
   LDR         R0,??timer0Match0Isr_0+8  ;; tickCounter
   MOV         R1,#+0x0
   STR         R1,[R0, #+0]
??timer0Match0Isr_2:
   MVN         R2,#+0xCF
   BIC         R2,R2,#+0xF00
   MOV         R3,#+0x0
   STR         R3,[R2, #+0]
   LDMIA       SP!,{R0-R3,LR}     ;; Pop
        CFI R0 SameValue
        CFI R1 SameValue
        CFI R2 SameValue
        CFI R3 SameValue
        CFI R14_usr SameValue
        CFI CFA_R13_usr R13_usr+0
   MRS         R12,CPSR
   ORR         R12,R12,#+0x92
   BIC         R12,R12,#+0xD
   MSR         CPSR,R12
   LDMIA       SP!,{R12,LR}
        CFI R12 SameValue
        CFI CFA_R13_irq R13_irq+4
   MSR         SPSR,LR
        CFI R14_irq SPSR_irq
   LDMIA       SP!,{PC}^          ;; return
   DATA        
??timer0Match0Isr_0:
   DC32        isrEntry
   DC32        delayTicks
   DC32        tickCounter
        CFI EndBlock cfiBlock1

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock2 Using cfiCommon0
        CFI Function timer0Delay
   CODE32      
timer0Delay:
   SUB         SP,SP,#+0x4
        CFI CFA R13+4
   CMP         R0,#+0x0
   BEQ         ??timer0Delay_0
   MOV         R2,#+0xE0000008
   ORR         R2,R2,#+0x4000
   LDR         R3,[R2, #+0]
   ADDS        R12,R0,R3
   STR         R12,[SP, #+0]
??timer0Delay_1:
   MOV         R1,#+0xE0000008
   ORR         R1,R1,#+0x4000
   LDR         R2,[R1, #+0]
   LDR         R12,[SP, #+0]
   CMP         R2,R12
   BNE         ??timer0Delay_1
??timer0Delay_0:
   ADD         SP,SP,#+0x4        ;; stack cleaning
        CFI CFA R13+0
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock2

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock3 Using cfiCommon0
        CFI NoFunction
   CODE32      
pllGetPeriphDivider??rA:
   LDR         R12,??Subroutine0_0  ;; pllGetPeriphDivider
   MOV         PC,R12
   DATA        
??Subroutine0_0:
   DC32        pllGetPeriphDivider
        CFI EndBlock cfiBlock3

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock4 Using cfiCommon0
        CFI NoFunction
   CODE32      
??rA??divu32_a:
   LDR         R12,??Subroutine1_0  ;; ??divu32_a
   MOV         PC,R12
   DATA        
??Subroutine1_0:
   DC32        ??divu32_a
        CFI EndBlock cfiBlock4

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock5 Using cfiCommon0
        CFI NoFunction
   CODE32      
armvicIntConnect??rA:
   LDR         R12,??Subroutine2_0  ;; armvicIntConnect
   MOV         PC,R12
   DATA        
??Subroutine2_0:
   DC32        armvicIntConnect
        CFI EndBlock cfiBlock5

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock6 Using cfiCommon0
        CFI NoFunction
   CODE32      
armvicIntEnable??rA:
   LDR         R12,??Subroutine3_0  ;; armvicIntEnable
   MOV         PC,R12
   DATA        
??Subroutine3_0:
   DC32        armvicIntEnable
        CFI EndBlock cfiBlock6

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock7 Using cfiCommon0
        CFI NoFunction
   CODE32      
boardTimerLedToggle??rA:
   LDR         R12,??Subroutine4_0  ;; boardTimerLedToggle
   MOV         PC,R12
   DATA        
??Subroutine4_0:
   DC32        boardTimerLedToggle
        CFI EndBlock cfiBlock7

        RSEG INITTAB:CODE:ROOT(2)
   DATA
?init?tab?DATA_Z:
   DCD      sfe(DATA_Z) - sfb(DATA_Z), sfb(DATA_Z), sfb(DATA_Z)

        END
// 
// 540 bytes in segment CODE
//  12 bytes in segment DATA_Z
//  12 bytes in segment INITTAB
// 
// 480 bytes of CODE memory (+ 72 bytes shared)
//  12 bytes of DATA memory
//
//Errors: none
//Warnings: 1
