//////////////////////////////////////////////////////////////////////////////
//                                                                           /
// IAR ARM ANSI C/C++ Compiler V4.11A/W32              20/Jul/2004  18:58:46 /
// Copyright 1999-2004 IAR Systems. All rights reserved.                     /
//                                                                           /
//    Cpu mode        =  arm                                                 /
//    Endian          =  little                                              /
//    Stack alignment =  4                                                   /
//    Source file     =  C:\medusa\pll.c                                     /
//    Command line    =  -I "C:\Program Files\IAR Systems\Embedded           /
//                       Workbench 4.0\ARM\INC\" -lc C:\medusa\Debug\List\   /
//                       -la C:\medusa\Debug\List\ -o C:\medusa\Debug\Obj\   /
//                       -s2 --no_cse --no_unroll --no_inline                /
//                       --no_code_motion --no_tbaa --no_clustering          /
//                       --no_scheduling --debug --cpu_mode arm --endian     /
//                       little --cpu ARM7TDMI-S --stack_align 4 -e --fpu    /
//                       None "-D_DLIB_CONFIG_FILE=C:\Program Files\IAR      /
//                       Systems\Embedded Workbench                          /
//                       4.0\ARM\LIB\dl4tpannl8n.h" C:\medusa\pll.c          /
//    List file       =  C:\medusa\Debug\List\pll.s79                        /
//                                                                           /
//                                                                           /
//////////////////////////////////////////////////////////////////////////////

        NAME pll

        RTMODEL "ARMv4M", "USED"
        RTMODEL "StackAlign4", "USED"
        RTMODEL "__cpu_mode", "__pcs__arm"
        RTMODEL "__data_model", "absolute"
        RTMODEL "__endian", "little"
        RTMODEL "__rt_version", "6"

        RSEG CSTACK:DATA:NOROOT(2)

        EXTERN ??DiI_a
        EXTERN ??EnI_a
        EXTERN ??divu32_a

        PUBWEAK `?*?DATA_ID`
??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable2 EQU 0
??DataTable4 EQU 0
??DataTable5 EQU 0
??DataTable6 EQU 0
??DataTable7 EQU 0
??DataTable9 EQU 0
        MULTWEAK ??rA??DiI_a
        MULTWEAK ??rA??EnI_a
        MULTWEAK ??rA??divu32_a
        PUBWEAK ?init?tab?DATA_I
        PUBWEAK ?init?tab?DATA_Z
        PUBLIC pllGetCpuFreq
        FUNCTION pllGetCpuFreq,0203H
        PUBLIC pllGetPeriphDivider
        FUNCTION pllGetPeriphDivider,0203H
        PUBLIC pllGetPeriphFreq
        FUNCTION pllGetPeriphFreq,0203H
        LOCFRAME CSTACK, 4, STACK
        PUBLIC pllInit
        FUNCTION pllInit,0203H
        LOCFRAME CSTACK, 4, STACK
        FUNCTION pllPassword,0203H
        LOCFRAME CSTACK, 4, STACK
        PUBLIC pllSetPeriphDivider
        FUNCTION pllSetPeriphDivider,0203H
        FUNCTION pllWaitLock,0203H
        
        CFI Names cfiNames0
        CFI StackFrame CFA R13 HUGEDATA
        CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
        CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13:32
        CFI Resource R14:32, SPSR:32
        CFI VirtualResource ?RET:32
        CFI EndNames cfiNames0
        
        CFI Common cfiCommon0 Using cfiNames0
        CFI CodeAlign 4
        CFI DataAlign 4
        CFI ReturnAddress ?RET CODE
        CFI CFA R13+0
        CFI R0 Undefined
        CFI R1 Undefined
        CFI R2 Undefined
        CFI R3 Undefined
        CFI R4 SameValue
        CFI R5 SameValue
        CFI R6 SameValue
        CFI R7 SameValue
        CFI R8 SameValue
        CFI R9 SameValue
        CFI R10 SameValue
        CFI R11 SameValue
        CFI R12 Undefined
        CFI CPSR SameValue
        CFI R14 Undefined
        CFI SPSR SameValue
        CFI ?RET R14
        CFI EndCommon cfiCommon0
        

        RSEG DATA_I:DATA:SORT:NOROOT(2)
cpuFreqHz:
        DS8 4
	REQUIRE `?<Initializer for cpuFreqHz>`

        RSEG DATA_I:DATA:SORT:NOROOT(2)
vpbDivider:
        DS8 4
	REQUIRE `?<Initializer for vpbDivider>`

        RSEG DATA_I:DATA:SORT:NOROOT(2)
pllMultiplier:
        DS8 4
	REQUIRE `?<Initializer for pllMultiplier>`

        RSEG DATA_Z:DATA:SORT:NOROOT(2)
pllStatus:
        DS8 4

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock0 Using cfiCommon0
        CFI Function pllPassword
   CODE32      
pllPassword:
   STMDB       SP!,{LR}           ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI CFA R13+4
   _BLF        ??DiI_a,??rA??DiI_a
   LDR         R0,??pllPassword_0  ;; 0xe01fc08c
   MOV         R1,#+0xAA
   STR         R1,[R0, #+0]
   LDR         R2,??pllPassword_0  ;; 0xe01fc08c
   MOV         R3,#+0x55
   STR         R3,[R2, #+0]
   _BLF        ??EnI_a,??rA??EnI_a
   LDMIA       SP!,{PC}           ;; return
   DATA        
??pllPassword_0:
   DC32        0xe01fc08c
        CFI EndBlock cfiBlock0

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock1 Using cfiCommon0
        CFI Function pllWaitLock
   CODE32      
pllWaitLock:
??pllWaitLock_0:
   LDR         R0,??DataTable3    ;; 0xe01fc088
   LDR         R1,[R0, #+0]
   TST         R1,#+0x400
   BEQ         ??pllWaitLock_0
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock1

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock2 Using cfiCommon0
        CFI Function pllInit
   CODE32      
pllInit:
   STMDB       SP!,{LR}           ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI CFA R13+4
   LDR         R0,??pllInit_0     ;; 0xe01fc084
   MOV         R1,#+0x2
   STR         R1,[R0, #+0]
   LDR         R2,??pllInit_0+4   ;; pllMultiplier
   MOV         R3,#+0x3
   STR         R3,[R2, #+0]
   LDR         R12,??pllInit_0+8  ;; 0xe01fc080
   MOV         R0,#+0x1
   STR         R0,[R12, #+0]
   BL          pllPassword
   BL          pllWaitLock
   LDR         R1,??pllInit_0+8   ;; 0xe01fc080
   MOV         R2,#+0x3
   STR         R2,[R1, #+0]
   BL          pllPassword
   LDR         R3,??DataTable8    ;; cpuFreqHz
   LDR         R12,??DataTable8   ;; cpuFreqHz
   LDR         R0,[R12, #+0]
   LDR         LR,??pllInit_0+4   ;; pllMultiplier
   LDR         R1,[LR, #+0]
   MULS        R2,R1,R0
   STR         R2,[R3, #+0]
   LDR         R3,??pllInit_0+12  ;; pllStatus
   LDR         R12,??DataTable3   ;; 0xe01fc088
   LDR         R0,[R12, #+0]
   STR         R0,[R3, #+0]
   MOV         R0,#+0x0
   LDMIA       SP!,{PC}           ;; return
   DATA        
??pllInit_0:
   DC32        0xe01fc084
   DC32        pllMultiplier
   DC32        0xe01fc080
   DC32        pllStatus
        CFI EndBlock cfiBlock2

        RSEG CODE:CODE:NOROOT(2)
   DATA        
??DataTable3:
   DC32        0xe01fc088

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock3 Using cfiCommon0
        CFI Function pllSetPeriphDivider
   CODE32      
pllSetPeriphDivider:
   MOV         R1,R0
   MVN         R2,#+0x0
   MOV         R0,R2
   MOV         R3,R1
   CMP         R3,#+0x1
   BEQ         ??pllSetPeriphDivider_0
   CMP         R3,#+0x2
   BEQ         ??pllSetPeriphDivider_1
   CMP         R3,#+0x4
   BEQ         ??pllSetPeriphDivider_2
   B           ??pllSetPeriphDivider_3
??pllSetPeriphDivider_0:
   LDR         R2,??pllSetPeriphDivider_4  ;; 0xe01fc100
   MOV         R3,#+0x1
   STR         R3,[R2, #+0]
   LDR         R12,??DataTable10  ;; vpbDivider
   MOV         R2,#+0x1
   STR         R2,[R12, #+0]
   MVN         R3,#+0x0
   MOV         R0,R3
   B           ??pllSetPeriphDivider_3
??pllSetPeriphDivider_1:
   LDR         R12,??pllSetPeriphDivider_4  ;; 0xe01fc100
   MOV         R2,#+0x2
   STR         R2,[R12, #+0]
   LDR         R3,??DataTable10   ;; vpbDivider
   MOV         R12,#+0x2
   STR         R12,[R3, #+0]
   MVN         R2,#+0x0
   MOV         R0,R2
   B           ??pllSetPeriphDivider_3
??pllSetPeriphDivider_2:
   LDR         R3,??pllSetPeriphDivider_4  ;; 0xe01fc100
   MOV         R12,#+0x0
   STR         R12,[R3, #+0]
   LDR         R2,??DataTable10   ;; vpbDivider
   MOV         R3,#+0x4
   STR         R3,[R2, #+0]
   MVN         R12,#+0x0
   MOV         R0,R12
??pllSetPeriphDivider_3:
   MOV         PC,LR              ;; return
   DATA        
??pllSetPeriphDivider_4:
   DC32        0xe01fc100
        CFI EndBlock cfiBlock3

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock4 Using cfiCommon0
        CFI Function pllGetCpuFreq
   CODE32      
pllGetCpuFreq:
   LDR         R0,??DataTable8    ;; cpuFreqHz
   LDR         R0,[R0, #+0]
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock4

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock5 Using cfiCommon0
        CFI Function pllGetPeriphFreq
   CODE32      
pllGetPeriphFreq:
   STMDB       SP!,{LR}           ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI CFA R13+4
   LDR         R0,??DataTable8    ;; cpuFreqHz
   LDR         R0,[R0, #+0]
   LDR         R1,??DataTable10   ;; vpbDivider
   LDR         R1,[R1, #+0]
   _BLF        ??divu32_a,??rA??divu32_a
   MOV         R0,R1
   LDMIA       SP!,{PC}           ;; return
        CFI EndBlock cfiBlock5

        RSEG CODE:CODE:NOROOT(2)
   DATA        
??DataTable8:
   DC32        cpuFreqHz

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock6 Using cfiCommon0
        CFI Function pllGetPeriphDivider
   CODE32      
pllGetPeriphDivider:
   LDR         R0,??DataTable10   ;; vpbDivider
   LDR         R0,[R0, #+0]
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock6

        RSEG CODE:CODE:NOROOT(2)
   DATA        
??DataTable10:
   DC32        vpbDivider

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock7 Using cfiCommon0
        CFI NoFunction
   CODE32      
??rA??DiI_a:
   LDR         R12,??Subroutine0_0  ;; ??DiI_a
   MOV         PC,R12
   DATA        
??Subroutine0_0:
   DC32        ??DiI_a
        CFI EndBlock cfiBlock7

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock8 Using cfiCommon0
        CFI NoFunction
   CODE32      
??rA??EnI_a:
   LDR         R12,??Subroutine1_0  ;; ??EnI_a
   MOV         PC,R12
   DATA        
??Subroutine1_0:
   DC32        ??EnI_a
        CFI EndBlock cfiBlock8

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock9 Using cfiCommon0
        CFI NoFunction
   CODE32      
??rA??divu32_a:
   LDR         R12,??Subroutine2_0  ;; ??divu32_a
   MOV         PC,R12
   DATA        
??Subroutine2_0:
   DC32        ??divu32_a
        CFI EndBlock cfiBlock9

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?<Initializer for cpuFreqHz>`:
        DC32 20000000

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?<Initializer for vpbDivider>`:
        DC32 4

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?<Initializer for pllMultiplier>`:
        DC32 1

        RSEG INITTAB:CODE:ROOT(2)
   DATA
?init?tab?DATA_Z:
   DCD      sfe(DATA_Z) - sfb(DATA_Z), sfb(DATA_Z), sfb(DATA_Z)

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?*?DATA_ID`:

        RSEG INITTAB:CODE:ROOT(2)
   DATA
?init?tab?DATA_I:
   DCD      sfe(DATA_I) - sfb(DATA_I), sfb(DATA_I), sfb(DATA_ID)

        END
// 
// 456 bytes in segment CODE
//  12 bytes in segment DATA_I
//  12 bytes in segment DATA_ID
//   4 bytes in segment DATA_Z
//  24 bytes in segment INITTAB
// 
// 420 bytes of CODE  memory (+ 60 bytes shared)
//  12 bytes of CONST memory
//  16 bytes of DATA  memory
//
//Errors: none
//Warnings: 1
