//////////////////////////////////////////////////////////////////////////////
//                                                                           /
// IAR ARM ANSI C/C++ Compiler V4.11A/W32              20/Jul/2004  18:58:53 /
// Copyright 1999-2004 IAR Systems. All rights reserved.                     /
//                                                                           /
//    Cpu mode        =  arm                                                 /
//    Endian          =  little                                              /
//    Stack alignment =  4                                                   /
//    Source file     =  C:\medusa\armvic.c                                  /
//    Command line    =  -I "C:\Program Files\IAR Systems\Embedded           /
//                       Workbench 4.0\ARM\INC\" -lc C:\medusa\Debug\List\   /
//                       -la C:\medusa\Debug\List\ -o C:\medusa\Debug\Obj\   /
//                       -s2 --no_cse --no_unroll --no_inline                /
//                       --no_code_motion --no_tbaa --no_clustering          /
//                       --no_scheduling --debug --cpu_mode arm --endian     /
//                       little --cpu ARM7TDMI-S --stack_align 4 -e --fpu    /
//                       None "-D_DLIB_CONFIG_FILE=C:\Program Files\IAR      /
//                       Systems\Embedded Workbench                          /
//                       4.0\ARM\LIB\dl4tpannl8n.h" C:\medusa\armvic.c       /
//    List file       =  C:\medusa\Debug\List\armvic.s79                     /
//                                                                           /
//                                                                           /
//////////////////////////////////////////////////////////////////////////////

        NAME armvic

        RTMODEL "ARMv4M", "USED"
        RTMODEL "StackAlign4", "USED"
        RTMODEL "__cpu_mode", "__pcs__arm"
        RTMODEL "__data_model", "absolute"
        RTMODEL "__endian", "little"
        RTMODEL "__rt_version", "6"

        RSEG CSTACK:DATA:NOROOT(2)
        RSEG IRQSTACK:DATA:NOROOT(2)

        PUBWEAK `?*?DATA_ID`
        PUBWEAK ?init?tab?DATA_I
        PUBWEAK ?init?tab?DATA_Z
        PUBLIC armvicInit
        FUNCTION armvicInit,0203H
        PUBLIC armvicIntConnect
        FUNCTION armvicIntConnect,0203H
        PUBLIC armvicIntDisable
        FUNCTION armvicIntDisable,0203H
        PUBLIC armvicIntDisconnect
        FUNCTION armvicIntDisconnect,0203H
        PUBLIC armvicIntEnable
        FUNCTION armvicIntEnable,0203H
        PUBLIC armvicIntPrioLevelSet
        FUNCTION armvicIntPrioLevelSet,0203H
        PUBLIC armvicSoftIntAssert
        FUNCTION armvicSoftIntAssert,0203H
        PUBLIC armvicSoftIntNegate
        FUNCTION armvicSoftIntNegate,0203H
        PUBLIC armvicSoftIntNegateAll
        FUNCTION armvicSoftIntNegateAll,0203H
        PUBLIC fiqvec
        PUBLIC irqvec
        PUBLIC swivec
        FUNCTION unassignedVectorIsr,0603H
        LOCFRAME CSTACK, 8, STACK
        
        CFI Names cfiNames0
        CFI StackFrame CFA_R13_usr R13_usr HUGEDATA
        CFI StackFrame CFA_R13_irq R13_irq HUGEDATA
        CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
        CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13_usr:32
        CFI Resource R14_usr:32, R13_irq:32, R14_irq:32, SPSR_irq:32
        CFI VirtualResource ?RET:32
        CFI EndNames cfiNames0
        
        CFI Common cfiCommon0 Using cfiNames0
        CFI CodeAlign 4
        CFI DataAlign 4
        CFI ReturnAddress ?RET CODE
        CFI CFA_R13_usr R13_usr+0
        CFI CFA_R13_irq R13_irq+0
        CFI R0 SameValue
        CFI R1 SameValue
        CFI R2 SameValue
        CFI R3 SameValue
        CFI R4 SameValue
        CFI R5 SameValue
        CFI R6 SameValue
        CFI R7 SameValue
        CFI R8 SameValue
        CFI R9 SameValue
        CFI R10 SameValue
        CFI R11 SameValue
        CFI R12 SameValue
        CFI CPSR SPSR_irq
        CFI R14_usr SameValue
        CFI R14_irq Undefined
        CFI SPSR_irq Undefined
        CFI ?RET add(R14_irq, literal(-4))
        CFI EndCommon cfiCommon0
        
        
        CFI Names cfiNames1
        CFI StackFrame CFA R13 HUGEDATA
        CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
        CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13:32
        CFI Resource R14:32, SPSR:32
        CFI VirtualResource ?RET:32
        CFI EndNames cfiNames1
        
        CFI Common cfiCommon1 Using cfiNames1
        CFI CodeAlign 4
        CFI DataAlign 4
        CFI ReturnAddress ?RET CODE
        CFI CFA R13+0
        CFI R0 Undefined
        CFI R1 Undefined
        CFI R2 Undefined
        CFI R3 Undefined
        CFI R4 SameValue
        CFI R5 SameValue
        CFI R6 SameValue
        CFI R7 SameValue
        CFI R8 SameValue
        CFI R9 SameValue
        CFI R10 SameValue
        CFI R11 SameValue
        CFI R12 Undefined
        CFI CPSR SameValue
        CFI R14 Undefined
        CFI SPSR SameValue
        CFI ?RET R14
        CFI EndCommon cfiCommon1
        

        RSEG DATA_I:DATA:SORT:NOROOT(2)
// unsigned int *__data irqvec
irqvec:
        DS8 4
	REQUIRE `?<Initializer for irqvec>`

        RSEG DATA_I:DATA:SORT:NOROOT(2)
// unsigned int *__data fiqvec
fiqvec:
        DS8 4
	REQUIRE `?<Initializer for fiqvec>`

        RSEG DATA_I:DATA:SORT:NOROOT(2)
// unsigned int *__data swivec
swivec:
        DS8 4
	REQUIRE `?<Initializer for swivec>`

        RSEG DATA_Z:DATA:SORT:NOROOT(2)
unassignedVectorIrqs:
        DS8 4

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock0 Using cfiCommon0
        CFI Function unassignedVectorIsr
   CODE32      
unassignedVectorIsr:
   SUB         LR,LR,#+0x4
        CFI ?RET R14_irq
   STMDB       SP!,{LR}
        CFI ?RET Frame(CFA_R13_irq, -4)
        CFI CFA_R13_irq R13_irq+4
   MRS         LR,SPSR
        CFI SPSR_irq R14_irq
   STMDB       SP!,{R12,LR}
        CFI R14_irq Frame(CFA_R13_irq, -8)
        CFI R12 Frame(CFA_R13_irq, -12)
        CFI CFA_R13_irq R13_irq+12
   MRS         LR,CPSR
   ORR         LR,LR,#+0x1F
   MSR         CPSR,LR
   STMDB       SP!,{R0,R1}        ;; Push
        CFI R1 Frame(CFA_R13_usr, -4)
        CFI R0 Frame(CFA_R13_usr, -8)
        CFI CFA_R13_usr R13_usr+8
   LDR         R0,??unassignedVectorIsr_0  ;; unassignedVectorIrqs
   LDR         R1,??unassignedVectorIsr_0  ;; unassignedVectorIrqs
   LDR         R1,[R1, #+0]
   ADDS        R1,R1,#+0x1
   STR         R1,[R0, #+0]
   LDMIA       SP!,{R0,R1}        ;; Pop
        CFI R0 SameValue
        CFI R1 SameValue
        CFI CFA_R13_usr R13_usr+0
   MRS         R12,CPSR
   ORR         R12,R12,#+0x92
   BIC         R12,R12,#+0xD
   MSR         CPSR,R12
   LDMIA       SP!,{R12,LR}
        CFI R12 SameValue
        CFI CFA_R13_irq R13_irq+4
   MSR         SPSR,LR
        CFI R14_irq SPSR_irq
   LDMIA       SP!,{PC}^          ;; return
   DATA        
??unassignedVectorIsr_0:
   DC32        unassignedVectorIrqs
        CFI EndBlock cfiBlock0

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock1 Using cfiCommon1
        CFI Function armvicInit
   CODE32      
armvicInit:
   MVN         R0,#+0xEB
   BIC         R0,R0,#+0xF00
   MVN         R1,#+0x0
   STR         R1,[R0, #+0]
   MVN         R2,#+0xF3
   BIC         R2,R2,#+0xF00
   MOV         R3,#+0x0
   STR         R3,[R2, #+0]
   MOV         R0,#+0x0
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock1

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock2 Using cfiCommon1
        CFI Function armvicIntPrioLevelSet
   CODE32      
armvicIntPrioLevelSet:
   MOV         R2,R0
   CMP         R2,#+0x0
   BLT         ??armvicIntPrioLevelSet_0
   CMP         R2,#+0x11
   BLT         ??armvicIntPrioLevelSet_1
??armvicIntPrioLevelSet_0:
   MVN         R0,#+0x0
   B           ??armvicIntPrioLevelSet_2
??armvicIntPrioLevelSet_1:
   MOV         R0,#+0x4
   MULS        R3,R0,R2
   ANDS        R12,R1,#+0x1F
   ORRS        R0,R12,#+0x20
   STR         R0,[R3, #-3584]
   MOV         R0,#+0x0
??armvicIntPrioLevelSet_2:
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock2

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock3 Using cfiCommon1
        CFI Function armvicIntConnect
   CODE32      
armvicIntConnect:
   MOV         R2,R0
   CMP         R2,#+0x0
   BLT         ??armvicIntConnect_0
   CMP         R2,#+0x11
   BLT         ??armvicIntConnect_1
??armvicIntConnect_0:
   MVN         R0,#+0x0
   B           ??armvicIntConnect_2
??armvicIntConnect_1:
   MOV         R0,#+0x4
   MULS        R3,R0,R2
   STR         R1,[R3, #-3840]
   MOV         R12,#+0x4
   MULS        R0,R12,R2
   ANDS        R3,R2,#+0x1F
   ORRS        R12,R3,#+0x20
   STR         R12,[R0, #-3584]
   MOV         R0,#+0x0
??armvicIntConnect_2:
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock3

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock4 Using cfiCommon1
        CFI Function armvicIntDisconnect
   CODE32      
armvicIntDisconnect:
   MOV         R1,R0
   CMP         R1,#+0x0
   BLT         ??armvicIntDisconnect_0
   CMP         R1,#+0x11
   BLT         ??armvicIntDisconnect_1
??armvicIntDisconnect_0:
   MVN         R0,#+0x0
   B           ??armvicIntDisconnect_2
??armvicIntDisconnect_1:
   MOV         R0,#+0x4
   MULS        R2,R0,R1
   MOV         R3,#+0x0
   STR         R3,[R2, #-3584]
   MOV         R12,#+0x4
   MULS        R0,R12,R1
   LDR         R2,??armvicIntDisconnect_3  ;; unassignedVectorIsr
   STR         R2,[R0, #-3840]
   MOV         R0,#+0x0
??armvicIntDisconnect_2:
   MOV         PC,LR              ;; return
   DATA        
??armvicIntDisconnect_3:
   DC32        unassignedVectorIsr
        CFI EndBlock cfiBlock4

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock5 Using cfiCommon1
        CFI Function armvicSoftIntAssert
   CODE32      
armvicSoftIntAssert:
   MOV         R1,R0
   MVN         R0,#+0x0
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock5

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock6 Using cfiCommon1
        CFI Function armvicSoftIntNegate
   CODE32      
armvicSoftIntNegate:
   MOV         R1,R0
   MVN         R0,#+0x0
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock6

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock7 Using cfiCommon1
        CFI Function armvicSoftIntNegateAll
   CODE32      
armvicSoftIntNegateAll:
   MVN         R0,#+0x0
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock7

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock8 Using cfiCommon1
        CFI Function armvicIntEnable
   CODE32      
armvicIntEnable:
   MOV         R1,R0
   CMP         R1,#+0x0
   BLT         ??armvicIntEnable_0
   CMP         R1,#+0x11
   BLT         ??armvicIntEnable_1
??armvicIntEnable_0:
   MVN         R0,#+0x0
   B           ??armvicIntEnable_2
??armvicIntEnable_1:
   MVN         R0,#+0xEF
   BIC         R0,R0,#+0xF00
   MOV         R2,#+0x1
   MOV         R3,R1
   LDR         R12,[R0, #+0]
   ORR         R12,R12,R2, LSL R3
   STR         R12,[R0, #+0]
   MOV         R0,#+0x0
??armvicIntEnable_2:
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock8

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock9 Using cfiCommon1
        CFI Function armvicIntDisable
   CODE32      
armvicIntDisable:
   MOV         R1,R0
   CMP         R1,#+0x0
   BLT         ??armvicIntDisable_0
   CMP         R1,#+0x11
   BLT         ??armvicIntDisable_1
??armvicIntDisable_0:
   MVN         R0,#+0x0
   B           ??armvicIntDisable_2
??armvicIntDisable_1:
   MVN         R0,#+0xEB
   BIC         R0,R0,#+0xF00
   MOV         R2,#+0x1
   MOV         R3,R1
   LDR         R12,[R0, #+0]
   ORR         R12,R12,R2, LSL R3
   STR         R12,[R0, #+0]
   MOV         R0,#+0x0
??armvicIntDisable_2:
   MOV         PC,LR              ;; return
        CFI EndBlock cfiBlock9

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?<Initializer for irqvec>`:
        DC32 18H

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?<Initializer for fiqvec>`:
        DC32 1CH

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?<Initializer for swivec>`:
        DC32 8H

        RSEG INITTAB:CODE:ROOT(2)
   DATA
?init?tab?DATA_Z:
   DCD      sfe(DATA_Z) - sfb(DATA_Z), sfb(DATA_Z), sfb(DATA_Z)

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?*?DATA_ID`:

        RSEG INITTAB:CODE:ROOT(2)
   DATA
?init?tab?DATA_I:
   DCD      sfe(DATA_I) - sfb(DATA_I), sfb(DATA_I), sfb(DATA_ID)

        END
// 
// 484 bytes in segment CODE
//  12 bytes in segment DATA_I
//  12 bytes in segment DATA_ID
//   4 bytes in segment DATA_Z
//  24 bytes in segment INITTAB
// 
// 484 bytes of CODE  memory (+ 24 bytes shared)
//  12 bytes of CONST memory
//  16 bytes of DATA  memory
//
//Errors: none
//Warnings: none
