//////////////////////////////////////////////////////////////////////////////
//                                                                           /
// IAR ARM ANSI C/C++ Compiler V4.11A/W32              20/Jul/2004  18:58:48 /
// Copyright 1999-2004 IAR Systems. All rights reserved.                     /
//                                                                           /
//    Cpu mode        =  arm                                                 /
//    Endian          =  little                                              /
//    Stack alignment =  4                                                   /
//    Source file     =  C:\medusa\zarlink.c                                 /
//    Command line    =  -I "C:\Program Files\IAR Systems\Embedded           /
//                       Workbench 4.0\ARM\INC\" -lc C:\medusa\Debug\List\   /
//                       -la C:\medusa\Debug\List\ -o C:\medusa\Debug\Obj\   /
//                       -s2 --no_cse --no_unroll --no_inline                /
//                       --no_code_motion --no_tbaa --no_clustering          /
//                       --no_scheduling --debug --cpu_mode arm --endian     /
//                       little --cpu ARM7TDMI-S --stack_align 4 -e --fpu    /
//                       None "-D_DLIB_CONFIG_FILE=C:\Program Files\IAR      /
//                       Systems\Embedded Workbench                          /
//                       4.0\ARM\LIB\dl4tpannl8n.h" C:\medusa\zarlink.c      /
//    List file       =  C:\medusa\Debug\List\zarlink.s79                    /
//                                                                           /
//                                                                           /
//////////////////////////////////////////////////////////////////////////////

        NAME zarlink

        RTMODEL "ARMv4M", "USED"
        RTMODEL "StackAlign4", "USED"
        RTMODEL "__cpu_mode", "__pcs__arm"
        RTMODEL "__data_model", "absolute"
        RTMODEL "__endian", "little"
        RTMODEL "__rt_version", "6"

        RSEG CSTACK:DATA:NOROOT(2)

        PUBWEAK `?*?DATA_ID`
        PUBWEAK ?init?tab?DATA_I
        FUNCTION initSwitch,0203H
        LOCFRAME CSTACK, 12, STACK
        MULTWEAK zarlinkCpuMacAddrSet??rA
        MULTWEAK zarlinkIndexedWrite??rA
        PUBLIC zarlinkInit
        FUNCTION zarlinkInit,0203H
        LOCFRAME CSTACK, 8, STACK
        
        CFI Names cfiNames0
        CFI StackFrame CFA R13 HUGEDATA
        CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
        CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13:32
        CFI Resource R14:32, SPSR:32
        CFI VirtualResource ?RET:32
        CFI EndNames cfiNames0
        
        CFI Common cfiCommon0 Using cfiNames0
        CFI CodeAlign 4
        CFI DataAlign 4
        CFI ReturnAddress ?RET CODE
        CFI CFA R13+0
        CFI R0 Undefined
        CFI R1 Undefined
        CFI R2 Undefined
        CFI R3 Undefined
        CFI R4 SameValue
        CFI R5 SameValue
        CFI R6 SameValue
        CFI R7 SameValue
        CFI R8 SameValue
        CFI R9 SameValue
        CFI R10 SameValue
        CFI R11 SameValue
        CFI R12 Undefined
        CFI CPSR SameValue
        CFI R14 Undefined
        CFI SPSR SameValue
        CFI ?RET R14
        CFI EndCommon cfiCommon0
        
zarlinkCpuMacAddrSet SYMBOL "zarlinkCpuMacAddrSet"
zarlinkIndexedWrite SYMBOL "zarlinkIndexedWrite"
zarlinkCpuMacAddrSet??rA SYMBOL "??rA", zarlinkCpuMacAddrSet
zarlinkIndexedWrite??rA SYMBOL "??rA", zarlinkIndexedWrite

        EXTERN zarlinkCpuMacAddrSet
        FUNCTION zarlinkCpuMacAddrSet,0202H
        EXTERN zarlinkIndexedWrite
        FUNCTION zarlinkIndexedWrite,0202H


        RSEG DATA_I:DATA:SORT:NOROOT(2)
initialMacAddr:
        DS8 8
	REQUIRE `?<Initializer for initialMacAddr>`

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock0 Using cfiCommon0
        CFI Function initSwitch
   CODE32      
initSwitch:
   STMDB       SP!,{R4,LR}        ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI R4 Frame(CFA, -8)
        CFI CFA R13+8
   SUB         SP,SP,#+0x4
        CFI CFA R13+12
   MOV         R1,#+0x7
   MOV         R0,#+0xE10
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   MOV         R1,#+0x50
   MOV         R0,#+0x9
   ORR         R0,R0,#+0x600
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   MOV         R0,#+0x0
   MOV         R4,R0
??initSwitch_0:
   CMP         R4,#+0x6
   BGE         ??initSwitch_1
   MOV         R1,#+0x98
   MOV         R2,R4
   MOV         R3,#+0x2
   MULS        R12,R3,R2
   ADDS        R0,R12,#+0x81
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   ADDS        R4,R4,#+0x1
   B           ??initSwitch_0
??initSwitch_1:
   MOV         R1,#+0x0
   MOV         R4,R1
??initSwitch_2:
   CMP         R4,#+0xA
   BGE         ??initSwitch_3
   LDR         R0,??initSwitch_4  ;; 0xe0024014
   LDR         R2,[R0, #+0]
   STR         R2,[SP, #+0]
   ADDS        R4,R4,#+0x1
   B           ??initSwitch_2
??initSwitch_3:
   MOV         R3,#+0x0
   MOV         R4,R3
??initSwitch_5:
   CMP         R4,#+0x6
   BGE         ??initSwitch_6
   MOV         R1,#+0x18
   MOV         R12,R4
   MOV         LR,#+0x2
   MULS        R0,LR,R12
   ADDS        R0,R0,#+0x81
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   ADDS        R4,R4,#+0x1
   B           ??initSwitch_5
??initSwitch_6:
   MOV         R1,#+0x0
   MOV         R4,R1
??initSwitch_7:
   CMP         R4,#+0x6
   BGE         ??initSwitch_8
   MOV         R1,#+0x1
   MOV         R2,R4
   MOV         R3,#+0x2
   MULS        R12,R3,R2
   ADDS        R0,R12,#+0x80
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   ADDS        R4,R4,#+0x1
   B           ??initSwitch_7
??initSwitch_8:
   MOV         LR,#+0x0
   MOV         R4,LR
??initSwitch_9:
   CMP         R4,#+0x4
   BGE         ??initSwitch_10
   MOV         R1,#+0xD8
   MOV         R0,R4
   MOV         R2,#+0x2
   MULS        R0,R2,R0
   MOV         R0,R0, LSL #+16
   MOVS        R0,R0, LSR #+16
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   ADDS        R4,R4,#+0x1
   B           ??initSwitch_9
??initSwitch_10:
   MOV         R1,#+0x11
   MOV         R0,#+0x2
   ORR         R0,R0,#+0x600
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   LDR         R0,??initSwitch_4+4  ;; initialMacAddr
   _BLF        zarlinkCpuMacAddrSet,zarlinkCpuMacAddrSet??rA
   MOV         R1,#+0x10
   MOV         R0,#+0xF00
   _BLF        zarlinkIndexedWrite,zarlinkIndexedWrite??rA
   ADD         SP,SP,#+0x4        ;; stack cleaning
        CFI CFA R13+8
   LDMIA       SP!,{R4,PC}        ;; return
   DATA        
??initSwitch_4:
   DC32        0xe0024014
   DC32        initialMacAddr
        CFI EndBlock cfiBlock0

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock1 Using cfiCommon0
        CFI Function zarlinkInit
   CODE32      
zarlinkInit:
   STMDB       SP!,{LR}           ;; Push
        CFI ?RET Frame(CFA, -4)
        CFI CFA R13+4
   SUB         SP,SP,#+0x4
        CFI CFA R13+8
   MOV         R1,#+0xE0000008
   ORR         R1,R1,#+0x28000
   LDR         R2,[R1, #+0]
   STR         R2,[SP, #+0]
   MOV         R12,#+0x3000000
   ORR         R12,R12,#+0x700
   LDR         R0,[SP, #+0]
   ORR         R0,R0,R12
   STR         R0,[SP, #+0]
   LDR         R2,[SP, #+0]
   BICS        R2,R2,#+0xFF0000
   STR         R2,[SP, #+0]
   MOV         R3,#+0xE0000008
   ORR         R3,R3,#+0x28000
   LDR         R0,[SP, #+0]
   STR         R0,[R3, #+0]
   BL          initSwitch
   MOV         R0,#+0x0
   ADD         SP,SP,#+0x4        ;; stack cleaning
        CFI CFA R13+4
   LDMIA       SP!,{PC}           ;; return
        CFI EndBlock cfiBlock1

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock2 Using cfiCommon0
        CFI NoFunction
   CODE32      
zarlinkIndexedWrite??rA:
   LDR         R12,??Subroutine0_0  ;; zarlinkIndexedWrite
   MOV         PC,R12
   DATA        
??Subroutine0_0:
   DC32        zarlinkIndexedWrite
        CFI EndBlock cfiBlock2

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock3 Using cfiCommon0
        CFI NoFunction
   CODE32      
zarlinkCpuMacAddrSet??rA:
   LDR         R12,??Subroutine1_0  ;; zarlinkCpuMacAddrSet
   MOV         PC,R12
   DATA        
??Subroutine1_0:
   DC32        zarlinkCpuMacAddrSet
        CFI EndBlock cfiBlock3

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?<Initializer for initialMacAddr>`:
        DC8 0, 0, 1, 106, 12, 0, 0, 0

        RSEG DATA_ID:CONST:SORT:NOROOT(2)
`?*?DATA_ID`:

        RSEG INITTAB:CODE:ROOT(2)
   DATA
?init?tab?DATA_I:
   DCD      sfe(DATA_I) - sfb(DATA_I), sfb(DATA_I), sfb(DATA_ID)

        END
// 
// 456 bytes in segment CODE
//   8 bytes in segment DATA_I
//   8 bytes in segment DATA_ID
//  12 bytes in segment INITTAB
// 
// 432 bytes of CODE  memory (+ 36 bytes shared)
//   8 bytes of CONST memory
//   8 bytes of DATA  memory
//
//Errors: none
//Warnings: none
