#ifndef __lpc22xx_h__
#define __lpc22xx_h__

/* 
 * Register definitions for Philips LPC22xx (ARM7TDMI-S)
 *
 * Registers must be read/written as a 32-bit quantity, 16- and 8- bit
 * operations are not permitted. 
 *
 */

typedef volatile unsigned int lpc22xx_reg;

/* Watchdog Timer */

#define WDMOD  (*(lpc22xx_reg *)0xe0000000) /* Watchdog mode register */
#define WDTC   (*(lpc22xx_reg *)0xe0000004) /* Watchdog timer constant reg */
#define WDFEED (*(lpc22xx_reg *)0xe0000008) /* Watchdog 'feed' sequence reg */
#define WDTV   (*(lpc22xx_reg *)0xe000000c) /* Watchdog timer value register */

/* Timer 0 */

#define T0IR   (*(lpc22xx_reg *)0xe0004000) /* Timer0 Interrupt Register */
#define T0TCR  (*(lpc22xx_reg *)0xe0004004) /* Timer0 Control Register */
#define T0TC   (*(lpc22xx_reg *)0xe0004008) /* Timer0 Counter */
#define T0PR   (*(lpc22xx_reg *)0xe000400c) /* Timer0 Prescale Register */
#define T0PC   (*(lpc22xx_reg *)0xe0004010) /* Timer0 Prescale Counter */
#define T0MCR  (*(lpc22xx_reg *)0xe0004014) /* Timer0 Match Control Register */
#define T0MR0  (*(lpc22xx_reg *)0xe0004018) /* Timer0 Match Register 0 */
#define T0MR1  (*(lpc22xx_reg *)0xe000401c) /* Timer0 Match Register 1 */
#define T0MR2  (*(lpc22xx_reg *)0xe0004020) /* Timer0 Match Register 2 */
#define T0MR3  (*(lpc22xx_reg *)0xe0004024) /* Timer0 Match Register 3 */
#define T0CCR  (*(lpc22xx_reg *)0xe0004028) /* Timer0 Capture Control Reg */
#define T0CR0  (*(lpc22xx_reg *)0xe000402c) /* Timer0 Capture Register 0 */
#define T0CR1  (*(lpc22xx_reg *)0xe0004030) /* Timer0 Capture Register 1 */
#define T0CR2  (*(lpc22xx_reg *)0xe0004034) /* Timer0 Capture Register 2 */
#define T0CR3  (*(lpc22xx_reg *)0xe0004038) /* Timer0 Capture Register 3 */
                                            /* - missing from 10/02/03 UM */
#define T0EMR  (*(lpc22xx_reg *)0xe000403c) /* Timer0 External Match Register */

/* Timer 1 */

#define T1IR   (*(lpc22xx_reg *)0xe0008000) /* Timer1 Interrupt Register */
#define T1TCR  (*(lpc22xx_reg *)0xe0008004) /* Timer1 Control Register */
#define T1TC   (*(lpc22xx_reg *)0xe0008008) /* Timer1 Counter */
#define T1PR   (*(lpc22xx_reg *)0xe000800c) /* Timer1 Prescale Register */
#define T1PC   (*(lpc22xx_reg *)0xe0008010) /* Timer1 Prescale Counter */
#define T1MCR  (*(lpc22xx_reg *)0xe0008014) /* Timer1 Match Control Register */
#define T1MR0  (*(lpc22xx_reg *)0xe0008018) /* Timer1 Match Register 0 */
#define T1MR1  (*(lpc22xx_reg *)0xe000801c) /* Timer1 Match Register 1 */
#define T1MR2  (*(lpc22xx_reg *)0xe0008020) /* Timer1 Match Register 2 */
#define T1MR3  (*(lpc22xx_reg *)0xe0008024) /* Timer1 Match Register 3 */
#define T1CCR  (*(lpc22xx_reg *)0xe0008028) /* Timer1 Capture Control Reg */
#define T1CR0  (*(lpc22xx_reg *)0xe000802c) /* Timer1 Capture Register 0 */
#define T1CR1  (*(lpc22xx_reg *)0xe0008030) /* Timer1 Capture Register 1 */
#define T1CR2  (*(lpc22xx_reg *)0xe0008034) /* Timer1 Capture Register 2 */
#define T1CR3  (*(lpc22xx_reg *)0xe0008038) /* Timer1 Capture Register 3 */
#define T1EMR  (*(lpc22xx_reg *)0xe000803c) /* Timer1 External Match Reg */

/* UART 0 */

#define U0RBR  (*(lpc22xx_reg *)0xe000c000) /* U0 Receive Buffer Register (R)*/
#define U0THR  (*(lpc22xx_reg *)0xe000c000) /* U0 Transmit Holding Reg    (W)*/
#define U0DLL  (*(lpc22xx_reg *)0xe000c000) /* U0 Divisor Latch LSB Register */
#define U0IER  (*(lpc22xx_reg *)0xe000c004) /* U0 Interrupt Enable Register  */
#define U0DLM  (*(lpc22xx_reg *)0xe000c004) /* U0 Divisor Latch MSB Register */
#define U0IIR  (*(lpc22xx_reg *)0xe000c008) /* U0 Interrupt ID Register */
#define U0FCR  (*(lpc22xx_reg *)0xe000c008) /* U0 FIFO Control Register */
#define U0LCR  (*(lpc22xx_reg *)0xe000c00c) /* U0 Line Control Register */
#define U0LSR  (*(lpc22xx_reg *)0xe000c014) /* U0 Line Status Register */
#define U0SCR  (*(lpc22xx_reg *)0xe000c01c) /* U0 Scratchpad Register */

/* UART 1 */

#define U1RBR  (*(lpc22xx_reg *)0xe0010000) /* U1 Receive Buffer Register (R)*/
#define U1THR  (*(lpc22xx_reg *)0xe0010000) /* U1 Transmit Holding Reg    (W)*/
#define U1DLL  (*(lpc22xx_reg *)0xe0010000) /* U1 Divisor Latch LSB Register */
#define U1IER  (*(lpc22xx_reg *)0xe0010004) /* U1 Interrupt Enable Register  */
#define U1DLM  (*(lpc22xx_reg *)0xe0010004) /* U1 Divisor Latch MSB Register */
#define U1IIR  (*(lpc22xx_reg *)0xe0010008) /* U1 Interrupt ID Register */
#define U1FCR  (*(lpc22xx_reg *)0xe0010008) /* U1 FIFO Control Register */
#define U1LCR  (*(lpc22xx_reg *)0xe001000c) /* U1 Line Control Register */
#define U1MCR  (*(lpc22xx_reg *)0xe0010010) /* U1 Modem Control Register */
#define U1LSR  (*(lpc22xx_reg *)0xe0010014) /* U1 Line Status Register */
#define U1MSR  (*(lpc22xx_reg *)0xe0010018) /* U1 Modem Status Register */
#define U1SCR  (*(lpc22xx_reg *)0xe001001c) /* U1 Scratchpad Register */

/* Pulse Width Modulator (PWM) */

#define PWMIR  (*(lpc22xx_reg *)0xe0014000) /* PWM Interrupt Register */
#define PWMTCR (*(lpc22xx_reg *)0xe0014004) /* PWM Timer Control Register */
#define PWMTC  (*(lpc22xx_reg *)0xe0014008) /* PWM Timer Counter */
#define PWMPR  (*(lpc22xx_reg *)0xe001400C) /* PWM Prescale Register */
#define PWMPC  (*(lpc22xx_reg *)0xe0014010) /* PWM Prescale Counter */
#define PWMMCR (*(lpc22xx_reg *)0xe0014014) /* PWM Match Control Register */
#define PWMMR0 (*(lpc22xx_reg *)0xe0014018) /* PWM Match Register 0 */
#define PWMMR1 (*(lpc22xx_reg *)0xe001401c) /* PWM Match Register 1 */
#define PWMMR2 (*(lpc22xx_reg *)0xe0014020) /* PWM Match Register 2 */
#define PWMMR3 (*(lpc22xx_reg *)0xe0014024) /* PWM Match Register 3 */
#define PWMMR4 (*(lpc22xx_reg *)0xe0014040) /* PWM Match Register 4 */
#define PWMMR5 (*(lpc22xx_reg *)0xe0014044) /* PWM Match Register 5 */
#define PWMMR6 (*(lpc22xx_reg *)0xe0014048) /* PWM Match Register 6 */
#define PWMPCR (*(lpc22xx_reg *)0xe001404c) /* PWM Control Register */
#define PWMLER (*(lpc22xx_reg *)0xe0014050) /* PWM Latch Enable Register */

/* I2C Interface (I2C) */

#define I2CONSET (*(lpc22xx_reg *)0xe001c000) /* I2C Control Set Register */
#define I2STAT   (*(lpc22xx_reg *)0xe001c004) /* I2C Status Register */
#define I2DAT    (*(lpc22xx_reg *)0xe001c008) /* I2C Data Register */
#define I2ADR    (*(lpc22xx_reg *)0xe001c00c) /* I2C Slave Address Register */
#define I2SCLH   (*(lpc22xx_reg *)0xe001c010) /* SCL Duty Cycle Reg (MS16bit)*/
#define I2SCLL   (*(lpc22xx_reg *)0xe001c014) /* SCL Duty Cycle Reg (LS16bit)*/
#define I2CONCLR (*(lpc22xx_reg *)0xe001c018) /* I2C Control Clear Register */

/* Serial Peripheral Interface (SPI) 0 */

#define S0SPCR   (*(lpc22xx_reg *)0xe0020000) /* SPI Control Register */
#define S0SPSR   (*(lpc22xx_reg *)0xe0020004) /* SPI Status Register */
#define S0SPDR   (*(lpc22xx_reg *)0xe0020008) /* SPI Data Register */
#define S0SPCCR  (*(lpc22xx_reg *)0xe002000c) /* SPI Clock Counter Register */
#define S0SPINT  (*(lpc22xx_reg *)0xe002001c) /* SPI Interrupt Flag Register */

/* Serial Peripheral Interface (SPI) 1 */

#define S1SPCR   (*(lpc22xx_reg *)0xe0030000) /* SPI Control Register */
#define S1SPSR   (*(lpc22xx_reg *)0xe0030004) /* SPI Status Register */
#define S1SPDR   (*(lpc22xx_reg *)0xe0030008) /* SPI Data Register */
#define S1SPCCR  (*(lpc22xx_reg *)0xe003000c) /* SPI Clock Counter Register */
#define S1SPINT  (*(lpc22xx_reg *)0xe003001c) /* SPI Interrupt Flag Register */

/* For backwards compatiblity with lpc210x */

#define SPCR     (S0SPCR)
#define SPSR     (S0SPSR)
#define SPDR     (S0SPDR)
#define SPCCR    (S0SSCCR)
#define SPINT    (S0SPINT)

/* Real Time Clock (RTC) */

#define ILR      (*(lpc22xx_reg *)0xe0024000) /* Interrupt Location Register */
#define CTC      (*(lpc22xx_reg *)0xe0024004) /* Clock Tick Counter */
#define CCR      (*(lpc22xx_reg *)0xe0024008) /* Clock Control Register */
#define CIIR     (*(lpc22xx_reg *)0xe002400c) /* Counter Increm. IRQ Reg */
#define AMR      (*(lpc22xx_reg *)0xe0024010) /* Alarm Mask Register */
#define CTIME0   (*(lpc22xx_reg *)0xe0024014) /* Consolidated Time Register 0*/
#define CTIME1   (*(lpc22xx_reg *)0xe0024018) /* Consolidated Time Register 1*/
#define CTIME2   (*(lpc22xx_reg *)0xe002401c) /* Consolidated Time Register 2*/
#define SEC      (*(lpc22xx_reg *)0xe0024020) /* Seconds Register */
#define MIN      (*(lpc22xx_reg *)0xe0024024) /* Minutes Register */
#define HOUR     (*(lpc22xx_reg *)0xe0024028) /* Hours Register */
#define DOM      (*(lpc22xx_reg *)0xe002402c) /* Day of Month Register */
#define DOW      (*(lpc22xx_reg *)0xe0024030) /* Day of Week Register */
#define DOY      (*(lpc22xx_reg *)0xe0024034) /* Day of Year Register */
#define MONTH    (*(lpc22xx_reg *)0xe0024038) /* Months Register */
#define YEAR     (*(lpc22xx_reg *)0xe002403c) /* Year Register */
#define ALSEC    (*(lpc22xx_reg *)0xe0024060) /* Alarm value for Seconds */
#define ALMIN    (*(lpc22xx_reg *)0xe0024064) /* Alarm value for Minutes */
#define ALHOUR   (*(lpc22xx_reg *)0xe0024068) /* Alarm value for Hours */
#define ALDOM    (*(lpc22xx_reg *)0xe002406c) /* Alarm value for Day of Month*/
#define ALDOW    (*(lpc22xx_reg *)0xe0024070) /* Alarm value for Day of Week */
#define ALDOY    (*(lpc22xx_reg *)0xe0024074) /* Alarm value for Day of Year */
#define ALMON    (*(lpc22xx_reg *)0xe0024078) /* Alarm value for Months */
#define ALYEAR   (*(lpc22xx_reg *)0xe002407c) /* Alarm value for Year */
#define PREINT   (*(lpc22xx_reg *)0xe0024080) /* Prescale value, integer part*/
#define PREFRAC  (*(lpc22xx_reg *)0xe0024084) /* Prescale value, fract.  part*/

/* General Purpose I/O (GPIO) */

#define IO0PIN   (*(lpc22xx_reg *)0xe0028000) /* GPIO 0 Pin value register */
#define IO0SET   (*(lpc22xx_reg *)0xe0028004) /* GPIO 0 Output set register */
#define IO0DIR   (*(lpc22xx_reg *)0xe0028008) /* GPIO 0 Direction control reg */
#define IO0CLR   (*(lpc22xx_reg *)0xe002800c) /* GPIO 0 Output clear register */

#define IO1PIN   (*(lpc22xx_reg *)0xe0028010) /* GPIO 1 Pin value register */
#define IO1SET   (*(lpc22xx_reg *)0xe0028014) /* GPIO 1 Output set register */
#define IO1DIR   (*(lpc22xx_reg *)0xe0028018) /* GPIO 1 Direction control reg */
#define IO1CLR   (*(lpc22xx_reg *)0xe002801c) /* GPIO 1 Output clear register */

/* for backward compatibility with LPC21xx */

#define IOPIN (IO0PIN)
#define IOSET (IO0SET)
#define IODIR (IO0DIR)
#define IOCLR (IO0CLR)

/* Pin Connect Block */

#define PINSEL0  (*(lpc22xx_reg *)0xe002c000) /* Pin function select reg 0 */
#define PINSEL1  (*(lpc22xx_reg *)0xe002c004) /* Pin function select reg 1 */
#define PINSEL2  (*(lpc22xx_reg *)0xe002c014) /* Pin function select reg 2 */

/* ADC */

#define ADCR     (*(lpc22xx_reg *)0xe0034000) /* ADC Control Register */
#define ADDR     (*(lpc22xx_reg *)0xe0034004) /* ADC Data Register */

/* CAN */

#define CAN_RX_LKUP_BASE \
                 (*(lpc22xx_reg *)0xe0034000) /* lookup receive identifiers */

#define CAN_RX_LKUP_SIZE \
                 (2*1024) /* lookup receive identifiers buffer size */

#define AFMR     (*(lpc22xx_reg *)0xe003C000) /* CAN Acceptance Filter reg*/

/* System Control Block */

#define MAMCR  (*(lpc22xx_reg *)0xe01fc000) /* Mem accel module control reg */
#define MAMTIM (*(lpc22xx_reg *)0xe01fc004) /* Mem accel module timing ctrl */

#define MEMMAP (*(lpc22xx_reg *)0xe01fc040) /* Memory mapping control */

#define PLLCON   (*(lpc22xx_reg *)0xe01fc080) /* Phase Locked Loop control */
#define PLLCFG   (*(lpc22xx_reg *)0xe01fc084) /* Phase Locked Loop config */
#define PLLSTAT  (*(lpc22xx_reg *)0xe01fc088) /* Phase Locked Loop status */
#define PLLFEED  (*(lpc22xx_reg *)0xe01fc08c) /* Phase Locked Loop 'feed' */

#define PCON   (*(lpc22xx_reg *)0xe01fc0c0) /* Power control register */
#define PCONP  (*(lpc22xx_reg *)0xe01fc0c4) /* Power control for peripherals */

#define VPBDIV (*(lpc22xx_reg *)0xe01fc100) /* VPB clock divider control */

#define EXTINT   (*(lpc22xx_reg *)0xe01fc140) /* External interrupt flag reg */
#define EXTWAKE  (*(lpc22xx_reg *)0xe01fc144) /* External interrupt wakeup */

#endif /* __lpc22xx_h__ */