#ifndef __spiregs_h__
#define __spiregs_h__

/* SPI Control Register */

#define CTRL_MASK         (unsigned long)0xF8

#define CTRL_CLK_PHASE    (unsigned long)0x08 // 1=data sampled on trailing clock edge 
#define CTRL_CLK_POLARITY (unsigned long)0x10 // 1=SCK is active low
#define CTRL_MASTER_MODE  (unsigned long)0x20 // 1=master, 0=slave
#define CTRL_LSB_FIRST    (unsigned long)0x40 // 1=data is sent lsb first, 0=msb first
#define CTRL_IRQ_ENABLE   (unsigned long)0x80 // 1=interrupts enabled

/* SPI Status Register */

#define STATUS_MASK       (unsigned long)0xF8

#define STATUS_SLAVE_ABRT (unsigned long)0x08
#define STATUS_MODE_FAULT (unsigned long)0x10
#define STATUS_RD_OVERRUN (unsigned long)0x20 // read overrun
#define STATUS_WRITE_COL  (unsigned long)0x40
#define STATUS_XFER_DONE  (unsigned long)0x80 // data transfer complete

/* SPI Interrupt Register */

#define IRQ_ACKNOWLEDGE   (unsigned long)0x01

#endif /* __spiregs_h__ */