#ifndef __vicregs_h__
#define __vicregs_h__

/* 
 * Register definitions for ARM PrimeCell Vectored Interrupt Controller (VIC) 
 *   in Philips LPC210x (ARM7TDMI-S)
 *
 * Registers must be read/written as a 32-bit quantity, 16- and 8- bit
 * operations are not permitted. 
 *
 * Reference: ARM PrimeCell(tm) Vectored Interrupt Controller (PL190)
 *            Technical Reference Manual
 *
 * Tim Meese
 * $Id: vicregs.h,v 1.0 2004-07-22 22:55:54-07 tim Exp tim $
 * 
 */

#define VICIRQStatus    (*(lpc210x_reg *)0xfffff000) /* IRQ Status Register */
#define VICFIQStatus    (*(lpc210x_reg *)0xfffff004) /* FIQ Status Register */
#define VICRawIntr      (*(lpc210x_reg *)0xfffff008) /* Raw IRQ Status Reg */
#define VICIntSelect    (*(lpc210x_reg *)0xfffff00c) /* Interrupt Select Reg*/
#define VICIntEnable    (*(lpc210x_reg *)0xfffff010) /* Interrupt Enable Reg*/
#define VICIntEnClr     (*(lpc210x_reg *)0xfffff014) /* Interrupt Enable Clr*/
#define VICSoftInt      (*(lpc210x_reg *)0xfffff018) /* Software Int Reg*/
#define VICSoftIntClear (*(lpc210x_reg *)0xfffff01c) /* Software Int Clr Reg*/
#define VICProtection   (*(lpc210x_reg *)0xfffff020) /* Protection Enable Reg*/

#define VICVectAddr     (*(lpc210x_reg *)0xfffff030) /* Vector Address */
#define VICDefVectAddr  (*(lpc210x_reg *)0xfffff034) /* Default Vector Address */

#define VICVectAddrN(n) (*(lpc210x_reg *)(0xfffff100 + ((n)*4)))

#define VICVectAddr0     VICVectAddrN(0)   /* Vector ISR Addr  0  */
#define VICVectAddr1     VICVectAddrN(1)   /* Vector ISR Addr  1  */
#define VICVectAddr2     VICVectAddrN(2)   /* Vector ISR Addr  2  */
#define VICVectAddr3     VICVectAddrN(3)   /* Vector ISR Addr  3  */
#define VICVectAddr4     VICVectAddrN(4)   /* Vector ISR Addr  4  */
#define VICVectAddr5     VICVectAddrN(5)   /* Vector ISR Addr  5  */
#define VICVectAddr6     VICVectAddrN(6)   /* Vector ISR Addr  6  */
#define VICVectAddr7     VICVectAddrN(7)   /* Vector ISR Addr  7  */
#define VICVectAddr8     VICVectAddrN(8)   /* Vector ISR Addr  8  */
#define VICVectAddr9     VICVectAddrN(9)   /* Vector ISR Addr  9  */
#define VICVectAddr10    VICVectAddrN(10)  /* Vector ISR Addr  10 */
#define VICVectAddr11    VICVectAddrN(11)  /* Vector ISR Addr  11 */
#define VICVectAddr12    VICVectAddrN(12)  /* Vector ISR Addr  12 */
#define VICVectAddr13    VICVectAddrN(13)  /* Vector ISR Addr  13 */
#define VICVectAddr14    VICVectAddrN(14)  /* Vector ISR Addr  14 */
#define VICVectAddr15    VICVectAddrN(15)  /* Vector ISR Addr  15 */

#define VICVectCtrlN(n) (*(lpc210x_reg *)(0xfffff200 + ((n)*4)))

#define VICVectCtrl0     VICVectCtrlN(0)   /* Vector Priority  0  */
#define VICVectCtrl1     VICVectCtrlN(1)   /* Vector Priority  1  */
#define VICVectCtrl2     VICVectCtrlN(2)   /* Vector Priority  2  */
#define VICVectCtrl3     VICVectCtrlN(3)   /* Vector Priority  3  */
#define VICVectCtrl4     VICVectCtrlN(4)   /* Vector Priority  4  */
#define VICVectCtrl5     VICVectCtrlN(5)   /* Vector Priority  5  */
#define VICVectCtrl6     VICVectCtrlN(6)   /* Vector Priority  6  */
#define VICVectCtrl7     VICVectCtrlN(7)   /* Vector Priority  7  */
#define VICVectCtrl8     VICVectCtrlN(8)   /* Vector Priority  8  */
#define VICVectCtrl9     VICVectCtrlN(9)   /* Vector Priority  9  */
#define VICVectCtrl10    VICVectCtrlN(10)  /* Vector Priority  10 */
#define VICVectCtrl11    VICVectCtrlN(11)  /* Vector Priority  11 */
#define VICVectCtrl12    VICVectCtrlN(12)  /* Vector Priority  12 */
#define VICVectCtrl13    VICVectCtrlN(13)  /* Vector Priority  13 */
#define VICVectCtrl14    VICVectCtrlN(14)  /* Vector Priority  14 */
#define VICVectCtrl15    VICVectCtrlN(15)  /* Vector Priority  15 */

#define VICPeriphIdN(n) (*(lpc210x_reg *)(0xffffffe0 + ((n)*4)))

#define VICPeriphId0    VICPeriphIdN(0)  /* Periph Id [ 7: 0] */
#define VICPeriphId1    VICPeriphIdN(1)  /* Periph Id [15: 8] */
#define VICPeriphId2    VICPeriphIdN(2)  /* Periph Id [23:16] */
#define VICPeriphId3    VICPeriphIdN(3)  /* Periph Id [31:24] */

#define VICPCellIdN(n)  (*(lpc210x_reg *)(0xfffffff0 + ((n)*4)))

#define VICPCellId0     VICPCellIdN(0)  /* PrimeCell Id [ 7: 0] */
#define VICPCellId1     VICPCellIdN(1)  /* PrimeCell Id [15: 8] */
#define VICPCellId2     VICPCellIdN(2)  /* PrimeCell Id [23:16] */
#define VICPCellId3     VICPCellIdN(3)  /* PrimeCell Id [31:24] */

#endif /* __vicregs_h__ */