library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;

entity linear_select_bus_mux is	  	
	port (	
		select_uart_n	: in  std_logic; 
		uart_data		: in  std_logic_vector(uart_data_bus_width - 1 downto 0);
		cf_data			: in  std_logic_vector(cf_data_bus_width - 1 downto 0);
		mux_out			: out std_logic_vector(cpu_data_bus_width - 1 downto 0)
	);
end linear_select_bus_mux;

architecture synthesis of linear_select_bus_mux is  
	signal source_select : std_logic_vector(1 downto 0);
begin
	process (select_uart_n, uart_data, cf_data)
	begin
		case select_uart_n is
			when '0' => mux_out <= "00000000" & uart_data;
			when '1' => mux_out <= cf_data;
			when others => mux_out <= (others => '0');
		end case;
	end process;		 

end synthesis;