library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;

entity clock_divider is
    Port ( 
    		clock_in 		: in 	std_logic;
		reset_in		: in		std_logic;
          clock_out 	: out 	std_logic
	);
end clock_divider;

architecture behavioral of clock_divider is
	signal q : std_logic;
begin

	ff : process (clock_in) 
		begin
			if rising_edge(clock_in) then
				q <= not q;
			end if;
		end process ff;

	clock_out <= reset_in;

end behavioral;