 
cpldfit:  version G.26                              Xilinx Inc.
                                  Fitter Report
Design Name: sidearm_glue_logic                  Date:  1-24-2004,  2:44PM
Device Used: XCR3512XL-10-FT256
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
129/512 ( 25%) 125 /1792 (  7%) 1  /512 (  1%) 203/208 ( 98%) 165/1280 ( 13%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   75          75    |  I/O              :   199        5
Output        :   87          87    |  GCK/IO           :     4        0
Bidirectional :   40          40    |  
GCK           :    1           1    |  
                 ----        ----
        Total      203         203

MACROCELL RESOURCES:

Total Macrocells Available                   512
Registered Macrocells                          1
Non-registered Macrocell driving I/O         126

GLOBAL RESOURCES:

Signal 'uart_osc_ipad' mapped onto global clock net GCK3.
Universal Control Terms (Used/Total)                      : 1/4

BLOCK RESOURCES:

Total Function Block Local Control Terms (Used/Total)     : 1/256
Total Foldback NANDs (Used/Total)                         : 0/256

End of Resource Summary
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg Init
Name                Pt    Used            Rate #    Type      Use     State
N_PZ_169            2       3     FB1_13            (b)       (b)     
_n0003              2       4     FB1_12            (b)       (b)     
cf_address_opads<0> 1       1     FB4_1   SLOW E13  I/O       O       
cf_address_opads<10>
                    1       1     FB2_16  SLOW D15  I/O       O       
cf_address_opads<1> 1       1     FB2_14  SLOW D14  I/O       O       
cf_address_opads<2> 1       1     FB2_13  SLOW B16  I/O       O       
cf_address_opads<3> 1       1     FB2_4   SLOW C15  I/O       O       
cf_address_opads<4> 1       1     FB12_14 SLOW R13  I/O       O       
cf_address_opads<5> 1       1     FB12_13 SLOW M11  I/O       O       
cf_address_opads<6> 1       1     FB12_3  SLOW T14  I/O       O       
cf_address_opads<7> 1       1     FB12_2  SLOW N12  I/O       O       
cf_address_opads<8> 1       1     FB12_1  SLOW R14  I/O       O       
cf_address_opads<9> 1       1     FB10_16 SLOW P13  I/O       O       
cf_csel_n_opad      0       0     FB4_15  SLOW E14  I/O       O       
cf_data_iopads<0>   2       2     FB6_3   SLOW E16  I/O       I/O     
cf_data_iopads<10>  2       2     FB6_15  SLOW F14  I/O       I/O     
cf_data_iopads<11>  2       2     FB6_13  SLOW F15  I/O       I/O     
cf_data_iopads<12>  2       2     FB6_14  SLOW G12  I/O       I/O     
cf_data_iopads<13>  2       2     FB6_16  SLOW G15  I/O       I/O     
cf_data_iopads<14>  2       2     FB8_1   SLOW G13  I/O       I/O     
cf_data_iopads<15>  2       2     FB8_3   SLOW F16  I/O       I/O     
cf_data_iopads<1>   2       2     FB13_1  SLOW L15  I/O       I/O     
cf_data_iopads<2>   2       2     FB11_2  SLOW M16  I/O       I/O     
cf_data_iopads<3>   2       2     FB11_1  SLOW M14  I/O       I/O     
cf_data_iopads<4>   2       2     FB9_15  SLOW L12  I/O       I/O     
cf_data_iopads<5>   2       2     FB10_3  SLOW M12  I/O       I/O     
cf_data_iopads<6>   2       2     FB10_1  SLOW N13  I/O       I/O     
cf_data_iopads<7>   2       2     FB9_2   SLOW N14  I/O       I/O     
cf_data_iopads<8>   2       2     FB9_13  SLOW M13  I/O       I/O     
cf_data_iopads<9>   2       2     FB9_14  SLOW P15  I/O       I/O     
cf_pce1_n_opad      1       1     FB4_14  SLOW D16  I/O       O       
cf_pce2_n_opad      1       1     FB4_4   SLOW F12  I/O       O       
cf_pior_n_opad      1       1     FB10_15 SLOW T15  I/O       O       
cf_piow_n_opad      1       1     FB10_14 SLOW P14  I/O       O       
cf_poe_n_opad       1       1     FB10_13 SLOW T16  I/O       O       
cf_power_on_opad    0       0     FB23_16 SLOW B8   I/O       O       
cf_preg_n_opad      1       1     FB11_16 SLOW K12  I/O       O       
cf_pwe_n_opad       1       1     FB11_15 SLOW L16  I/O       O       
cf_reset_opad       1       1     FB3_1   SLOW A14  I/O       O       
cpu_data_iopads<0>  3       3     FB8_13  SLOW G14  I/O       I/O     
cpu_data_iopads<10> 2       2     FB8_14  SLOW G16  I/O       I/O     
cpu_data_iopads<11> 2       2     FB8_15  SLOW H13  I/O       I/O     
cpu_data_iopads<12> 2       2     FB8_16  SLOW H12  I/O       I/O     
cpu_data_iopads<13> 2       2     FB15_16 SLOW H15  I/O       I/O     
cpu_data_iopads<14> 2       2     FB15_15 SLOW H14  I/O       I/O     
cpu_data_iopads<15> 2       2     FB15_13 SLOW H16  I/O       I/O     
cpu_data_iopads<1>  3       3     FB2_3   SLOW A16  I/O       I/O     
cpu_data_iopads<2>  3       4     FB1_1   SLOW C14  I/O       I/O     
cpu_data_iopads<3>  3       4     FB1_2   SLOW D13  I/O       I/O     
cpu_data_iopads<4>  3       4     FB1_4   SLOW A15  I/O       I/O     
cpu_data_iopads<5>  3       4     FB1_14  SLOW B15  I/O       I/O     
cpu_data_iopads<6>  3       4     FB1_15  SLOW B14  I/O       I/O     
cpu_data_iopads<7>  3       4     FB1_16  SLOW C13  I/O       I/O     
cpu_data_iopads<8>  2       2     FB15_3  SLOW J14  I/O       I/O     
cpu_data_iopads<9>  2       2     FB2_1   SLOW E12  I/O       I/O     
cpu_gpio_00_opad    1       1     FB7_3   SLOW A10  I/O       O       
cpu_gpio_01_opad    1       1     FB7_2   SLOW D10  I/O       O       
cpu_gpio_02_opad    1       1     FB3_15  SLOW B13  I/O       O       
cpu_gpio_03_opad    1       1     FB3_16  SLOW C12  I/O       O       
cpu_gpio_04_opad    1       1     FB22_1  SLOW E2   I/O       O       
cpu_gpio_05_opad    1       1     FB22_2  SLOW F3   I/O       O       
cpu_gpio_06_opad    1       1     FB22_4  SLOW F2   I/O       O       
cpu_gpio_07_opad    1       1     FB7_1   SLOW B11  I/O       O       
cpu_gpio_16_opad    0       0     FB21_16 SLOW A6   I/O       O       
cpu_gpio_17_opad    0       0     FB3_2   SLOW E11  I/O       O       
cpu_gpio_19_opad    1       1     FB5_1   SLOW A12  I/O       O       
cpu_gpio_20_opad    1       1     FB5_3   SLOW D11  I/O       O       
cpu_gpio_22_opad    1       1     FB5_13  SLOW A11  I/O       O       
cpu_gpio_23_opad    1       2     FB4_3   SLOW C16  I/O       O       
cpu_gpio_24_opad    0       0     FB3_4   SLOW A13  I/O       O       
cpu_gpio_25_opad    0       0     FB3_13  SLOW D12  I/O       O       
cpu_gpio_26_opad    1       1     FB19_14 SLOW E6   I/O       O       
cpu_iois16_n_opad   1       1     FB11_14 SLOW M15  I/O       O       
cpu_pwait_n_opad    1       1     FB11_4  SLOW N15  I/O       O       
cpu_ready_opad      0       0     FB7_15  SLOW A9   I/O       O       
dummy_signal_opad   1       27    FB4_16  SLOW E15  I/O       O       
ethernet_sleep_n_opad
                    1       1     FB19_16 SLOW C5   I/O       O       
lr_power_on_opad    1       1     FB30_13 SLOW R6   I/O       O       
net_reset_opad      1       1     FB24_4  SLOW H3   I/O       O       
reset_out_n_opad    1       1     FB19_15 SLOW A4   I/O       O       
spi_cs_0_n_opad     1       4     FB15_2  SLOW J15  I/O       O       
spi_cs_1_n_opad     1       4     FB13_16 SLOW J16  I/O       O       
spi_cs_2_n_opad     1       4     FB13_15 SLOW L14  I/O       O       
spi_cs_3_n_opad     1       4     FB13_14 SLOW K15  I/O       O       
spi_cs_4_n_opad     1       4     FB13_13 SLOW K14  I/O       O       
spi_cs_5_n_opad     1       4     FB13_4  SLOW K16  I/O       O       
spi_cs_6_n_opad     1       4     FB14_1  SLOW N11  I/O       O       
spi_cs_7_n_opad     1       4     FB12_15 SLOW P12  I/O       O       
sr_power_on_opad    1       1     FB12_16 SLOW T13  I/O       O       
test_opads<0>       0       0     FB29_14 SLOW K4   I/O       O       
test_opads<10>      0       0     FB27_4  SLOW N2   I/O       O       
test_opads<11>      0       0     FB25_14 SLOW N3   I/O       O       
test_opads<12>      0       0     FB27_1  SLOW P1   I/O       O       
test_opads<13>      0       0     FB25_1  SLOW P2   I/O       O       
test_opads<14>      0       0     FB25_2  SLOW P3   I/O       O       
test_opads<15>      1       1     FB25_15 SLOW R1   I/O       O       
test_opads<1>       0       0     FB29_4  SLOW K5   I/O       O       
test_opads<2>       0       0     FB29_1  SLOW L2   I/O       O       
test_opads<3>       0       0     FB29_13 SLOW L3   I/O       O       
test_opads<4>       0       0     FB27_15 SLOW L4   I/O       O       
test_opads<5>       0       0     FB27_3  SLOW L5   I/O       O       
test_opads<6>       0       0     FB29_3  SLOW M1   I/O       O       
test_opads<7>       0       0     FB27_16 SLOW M2   I/O       O       
test_opads<8>       0       0     FB27_14 SLOW M3   I/O       O       
test_opads<9>       0       0     FB25_16 SLOW M4   I/O       O       
uart_address_opads<0>
                    1       1     FB6_1   SLOW F13  I/O       O       
uart_address_opads<1>
                    1       1     FB13_3  SLOW K13  I/O       O       
uart_address_opads<2>
                    1       1     FB11_3  SLOW L13  I/O       O       
uart_address_opads<3>
                    1       1     FB9_16  SLOW N16  I/O       O       
uart_address_opads<4>
                    1       1     FB7_16  SLOW D9   I/O       O       
uart_address_opads<5>
                    1       1     FB10_2  SLOW R15  I/O       O       
uart_address_opads<6>
                    1       1     FB9_1   SLOW P16  I/O       O       
uart_address_opads<7>
                    1       1     FB9_3   SLOW R16  I/O       O       
uart_clock_opad     0       0     FB31_1  SLOW K2   I/O       O       RESET
uart_cs0_n_opad     1       2     FB16_1  SLOW T11  I/O       O       
uart_cs1_n_opad     1       2     FB16_2  SLOW R10  I/O       O       
uart_data_iopads<0> 2       2     FB30_3  SLOW M7   I/O       I/O     
uart_data_iopads<1> 2       2     FB30_2  SLOW T5   I/O       I/O     
uart_data_iopads<2> 2       2     FB30_1  SLOW T6   I/O       I/O     
uart_data_iopads<3> 2       2     FB28_16 SLOW R5   I/O       I/O     
uart_data_iopads<4> 2       2     FB28_15 SLOW N6   I/O       I/O     
uart_data_iopads<5> 2       2     FB28_14 SLOW T4   I/O       I/O     
uart_data_iopads<6> 2       2     FB28_4  SLOW P5   I/O       I/O     
uart_data_iopads<7> 2       2     FB28_3  SLOW R4   I/O       I/O     
uart_rd_n_opad      1       1     FB16_3  SLOW P10  I/O       O       
uart_reset_n_opad   1       1     FB26_2  SLOW N4   I/O       O       
uart_wr_n_opad      1       1     FB16_4  SLOW T10  I/O       O       
uplink_rx_enable_n_opad
                    1       1     FB14_13 SLOW M10  I/O       O       
uplink_tx_enable_opad
                    1       1     FB14_3  SLOW T12  I/O       O       

** INPUTS **
Signal                            Loc          Pin  Pin       Pin      I/O 
Name                                           #    Type      Use     Style
attention_arm_ipad                FB25_4       T1   I/O       I                  
cf_bvd_1_ipad                     FB32_16      T9   I/O       I                  
cf_bvd_2_ipad                     FB30_14      N7   I/O       I                  
cf_cd1_n_ipad                     FB30_15      T7   I/O       I                  
cf_cd2_n_ipad                     FB30_16      P6   I/O       I                  
cf_iois16_n_ipad                  FB32_1       R7   I/O       I                  
cf_rdy_bsy_ipad                   FB32_2       P7   I/O       I                  
cf_wait_n_ipad                    FB32_3       T8   I/O       I                  
cpu_address_in_ipads<0>                                  FB32_4       N8   I/O       I                  
cpu_address_in_ipads<10>                                  FB32_14      R8   I/O       I                  
cpu_address_in_ipads<11>                                  FB32_15      P8   I/O       I                  
cpu_address_in_ipads<12>                                  FB18_16      E4   I/O       I                  
cpu_address_in_ipads<1>                                  FB18_14      D1   I/O       I                  
cpu_address_in_ipads<2>                                  FB18_4       F5   I/O       I                  
cpu_address_in_ipads<3>                                  FB18_3       C2   I/O       I                  
cpu_address_in_ipads<4>                                  FB18_2       D3   I/O       I                  
cpu_address_in_ipads<5>                                  FB18_1       C1   I/O       I                  
cpu_address_in_ipads<6>                                  FB17_1       B1   I/O       I                  
cpu_address_in_ipads<7>                                  FB17_2       B2   I/O       I                  
cpu_address_in_ipads<8>                                  FB16_14      N9   I/O       I                  
cpu_address_in_ipads<9>                                  FB20_1       D2   I/O       I                  
cpu_cs3_n_ipad                    FB20_2       E3   I/O       I                  
cpu_cs4_n_ipad                    FB20_4       E1   I/O       I                  
cpu_cs5_n_ipad                    FB20_14      F4   I/O       I                  
cpu_dqm0_n_ipad                   FB20_15      F1   I/O       I                  
cpu_dqm1_n_ipad                   FB20_16      G5   I/O       I                  
cpu_gpio_08_ipad                  FB5_16       C11  I/O       I                  
cpu_gpio_09_ipad                  FB5_15       B12  I/O       I                  
cpu_gpio_10_ipad                  FB5_14       E10  I/O       I                  
cpu_gpio_11_ipad                  FB23_15      D8   I/O       I                  
cpu_gpio_12_ipad                  FB23_4       C8   I/O       I                  
cpu_gpio_13_ipad                  FB23_3       C7   I/O       I                  
cpu_gpio_14_ipad                  FB23_2       B7   I/O       I                  
cpu_gpio_15_ipad                  FB23_1       D7   I/O       I                  
cpu_gpio_18_ipad                  FB17_3       C3   I/O       I                  
cpu_gpio_21_ipad                  FB17_13      D4   I/O       I                  
cpu_gpio_27_ipad                  FB17_14      A2   I/O       I                  
cpu_khz32_ipad                                 B9   GCK/I     I                  
cpu_oe_n_ipad                     FB16_15      R9   I/O       I                  
cpu_pce1_n_ipad                   FB17_15      A1   I/O       I                  
cpu_pce2_n_ipad                   FB17_16      B3   I/O       I                  
cpu_pior_n_ipad                   FB19_1       C4   I/O       I                  
cpu_piow_n_ipad                   FB19_3       A3   I/O       I                  
cpu_pktsel_ipad                   FB19_4       D5   I/O       I                  
cpu_poe_n_ipad                    FB19_13      B4   I/O       I                  
cpu_preg_n_ipad                   FB22_14      G4   I/O       I                  
cpu_pwe_n_ipad                    FB22_15      G1   I/O       I                  
cpu_rclk_ipad                                  A8   GCK/I     I                  
cpu_reset_in_n_ipad               FB22_16      G3   I/O       I                  
cpu_rnw_ipad                      FB24_1       H1   I/O       I                  
cpu_uart_cs_n_ipad                FB24_2       H4   I/O       I                  
cpu_we_n_ipad                     FB16_16      P9   I/O       I                  
cts_n_00_ipad                     FB21_14      B6   I/O       I                  
cts_n_01_ipad                     FB21_13      C6   I/O       I                  
cts_n_02_ipad                     FB21_3       A5   I/O       I                  
cts_n_03_ipad                     FB21_2       D6   I/O       I                  
cts_n_04_ipad                     FB21_1       B5   I/O       I                  
cts_n_05_ipad                     FB26_13      P4   I/O       I                  
cts_n_06_ipad                     FB26_15      R3   I/O       I                  
cts_n_07_ipad                     FB26_16      N5   I/O       I                  
cts_n_08_ipad                     FB28_1       T3   I/O       I                  
cts_n_09_ipad                     FB28_2       M6   I/O       I                  
cts_n_10_ipad                     FB24_16      J3   I/O       I                  
cts_n_11_ipad                     FB24_13      J1   I/O       I                  
ethernet_interrupt_ipad                                  FB24_3       G2   I/O       I                  
ethernet_lanled_ipad                                  FB14_4       R11  I/O       I                  
lr_ri_ipad                        FB14_16      N10  I/O       I                  
power_on_reset_n_ipad                                  FB14_14      P11  I/O       I                  
rtc_irq_n_ipad                    FB31_15      J5   I/O       I                  
rtc_khz32_ipad                                 C9   GCK/I     I                  
spi_frame_n_ipad                  FB26_4       T2   I/O       I                  
spi_interrupt_ipad                FB14_2       R12  I/O       I                  
sr_ri_ipad                        FB21_15      E7   I/O       I                  
uart_osc_ipad                                  B10  GCK/I     GCK                
uarts_0_thru_7_interrupt_ipad                                  FB29_16      L1   I/O       I                  
uarts_8_thru_15_interrupt_ipad                                  FB26_1       M5   I/O       I                  

End of Resources

Legend: PU  - Pull Up
*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           8          19          19           17         0/6        6   
FB2           6           8           8            7         4/2        6   
FB3           6           3           3            3         6/0        6   
FB4           6          32          32            5         6/0        6   
FB5           3           3           3            3         3/0        6   
FB6           6           7           7            7         1/5        6   
FB7           5           4           4            4         5/0        5   
FB8           6           9           9            8         0/6        6   
FB9           7           8           8            8         3/4        7   
FB10          7           8           8            8         5/2        7   
FB11          7           8           8            8         5/2        7   
FB12          7          10          10            7         7/0        7   
FB13          7           7           7            8         6/1        7   
FB14          3           6           6            3         3/0        7   
FB15          5           9           9            5         1/4        5   
FB16          4           4           4            4         4/0        7   
FB17          0           0           0            0         0/0        7   
FB18          0           0           0            0         0/0        6   
FB19          3           3           3            3         3/0        7   
FB20          0           0           0            0         0/0        6   
FB21          1           0           0            0         1/0        7   
FB22          3           3           3            3         3/0        6   
FB23          1           0           0            0         1/0        6   
FB24          1           1           1            1         1/0        6   
FB25          5           1           1            1         5/0        6   
FB26          1           1           1            1         1/0        7   
FB27          6           0           0            0         6/0        6   
FB28          5           6           6            6         0/5        7   
FB29          5           0           0            0         5/0        6   
FB30          4           5           5            5         1/3        7   
FB31          1           0           0            0         1/0        6   
FB32          0           0           0            0         0/0        7   
            ----                                -----       -----     ----- 
            129                                  125        87/40     204   
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block:  19
Number of function block inputs used/remaining:               19/21
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   17/31
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cpu_data_iopads<2>                  3    FB1_1     C14   I/O   I/O
cpu_data_iopads<3>                  3    FB1_2     D13   I/O   I/O
(unused)                            0    FB1_3           (b)      
cpu_data_iopads<4>                  3    FB1_4     A15   I/O   I/O
(unused)                            0    FB1_5           (b)      
(unused)                            0    FB1_6           (b)      
(unused)                            0    FB1_7           (b)      
(unused)                            0    FB1_8           (b)      
(unused)                            0    FB1_9           (b)      
(unused)                            0    FB1_10          (b)      
(unused)                            0    FB1_11          (b)      
_n0003                              2    FB1_12          (b)   (b)
N_PZ_169                            2    FB1_13          (b)   (b)
cpu_data_iopads<5>                  3    FB1_14    B15   I/O   I/O
cpu_data_iopads<6>                  3    FB1_15    B14   I/O   I/O
cpu_data_iopads<7>                  3    FB1_16    C13   I/O   I/O

Signals Used by Logic in Function Block
  1: N_PZ_169           8: cf_data_iopads<7>.PIN 
                                             14: uart_data_iopads<2>.PIN 
  2: _n0003             9: cpu_pce1_n_ipad   15: uart_data_iopads<3>.PIN 
  3: cf_data_iopads<2>.PIN 
                       10: cpu_pce2_n_ipad   16: uart_data_iopads<4>.PIN 
  4: cf_data_iopads<3>.PIN 
                       11: cpu_pktsel_ipad   17: uart_data_iopads<5>.PIN 
  5: cf_data_iopads<4>.PIN 
                       12: cpu_rnw_ipad      18: uart_data_iopads<6>.PIN 
  6: cf_data_iopads<5>.PIN 
                       13: cpu_uart_cs_n_ipad 
                                             19: uart_data_iopads<7>.PIN 
  7: cf_data_iopads<6>.PIN 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cpu_data_iopads<2> 
                  X.X.........XX.......................... 4       4
cpu_data_iopads<3> 
                  X..X........X.X......................... 4       4
cpu_data_iopads<4> 
                  X...X.......X..X........................ 4       4
_n0003            ........XXXX............................ 4       4
N_PZ_169          .X.........XX........................... 3       3
cpu_data_iopads<5> 
                  X....X......X...X....................... 4       4
cpu_data_iopads<6> 
                  X.....X.....X....X...................... 4       4
cpu_data_iopads<7> 
                  X......X....X.....X..................... 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   7/41
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cpu_data_iopads<9>                  2    FB2_1     E12   I/O   I/O
(unused)                            0    FB2_2           (b)      
cpu_data_iopads<1>                  3    FB2_3     A16   I/O   I/O
cf_address_opads<3>                 1    FB2_4     C15   I/O     O
(unused)                            0    FB2_5           (b)      
(unused)                            0    FB2_6           (b)      
(unused)                            0    FB2_7           (b)      
(unused)                            0    FB2_8           (b)      
(unused)                            0    FB2_9           (b)      
(unused)                            0    FB2_10          (b)      
(unused)                            0    FB2_11          (b)      
(unused)                            0    FB2_12          (b)      
cf_address_opads<2>                 1    FB2_13    B16   I/O     O
cf_address_opads<1>                 1    FB2_14    D14   I/O     O
(unused)                            0    FB2_15          (b)      
cf_address_opads<10>                1    FB2_16    D15   I/O     O

Signals Used by Logic in Function Block
  1: cf_data_iopads<1>.PIN 
                        4: cpu_address_in_ipads<1> 
                                              7: cpu_uart_cs_n_ipad 
  2: cf_data_iopads<9>.PIN 
                        5: cpu_address_in_ipads<2> 
                                              8: uart_data_iopads<1>.PIN 
  3: cpu_address_in_ipads<10> 
                        6: cpu_address_in_ipads<3> 
                                            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cpu_data_iopads<9> 
                  .X....X................................. 2       2
cpu_data_iopads<1> 
                  X.....XX................................ 3       3
cf_address_opads<3> 
                  .....X.................................. 1       1
cf_address_opads<2> 
                  ....X................................... 1       1
cf_address_opads<1> 
                  ...X.................................... 1       1
cf_address_opads<10> 
                  ..X..................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block:  3
Number of function block inputs used/remaining:               3/37
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   3/45
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cf_reset_opad                       1    FB3_1     A14   I/O     O
cpu_gpio_17_opad                    0    FB3_2     E11   I/O     O
(unused)                            0    FB3_3           (b)      
cpu_gpio_24_opad                    0    FB3_4     A13   I/O     O
(unused)                            0    FB3_5           (b)      
(unused)                            0    FB3_6           (b)      
(unused)                            0    FB3_7           (b)      
(unused)                            0    FB3_8           (b)      
(unused)                            0    FB3_9           (b)      
(unused)                            0    FB3_10          (b)      
(unused)                            0    FB3_11          (b)      
(unused)                            0    FB3_12          (b)      
cpu_gpio_25_opad                    0    FB3_13    D12   I/O     O
(unused)                            0    FB3_14          (b)      
cpu_gpio_02_opad                    1    FB3_15    B13   I/O     O
cpu_gpio_03_opad                    1    FB3_16    C12   I/O     O

Signals Used by Logic in Function Block
  1: cpu_gpio_21_ipad   2: uarts_0_thru_7_interrupt_ipad 
                                              3: uarts_8_thru_15_interrupt_ipad 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cf_reset_opad     X....................................... 1       1
cpu_gpio_17_opad  ........................................ 0       0
cpu_gpio_24_opad  ........................................ 0       0
cpu_gpio_25_opad  ........................................ 0       0
cpu_gpio_02_opad  .X...................................... 1       1
cpu_gpio_03_opad  ..X..................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block:  32
Number of function block inputs used/remaining:               32/8
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   5/43
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cf_address_opads<0>                 1    FB4_1     E13   I/O     O
(unused)                            0    FB4_2           (b)      
cpu_gpio_23_opad                    1    FB4_3     C16   I/O     O
cf_pce2_n_opad                      1    FB4_4     F12   I/O     O
(unused)                            0    FB4_5           (b)      
(unused)                            0    FB4_6           (b)      
(unused)                            0    FB4_7           (b)      
(unused)                            0    FB4_8           (b)      
(unused)                            0    FB4_9           (b)      
(unused)                            0    FB4_10          (b)      
(unused)                            0    FB4_11          (b)      
(unused)                            0    FB4_12          (b)      
(unused)                            0    FB4_13          (b)      
cf_pce1_n_opad                      1    FB4_14    D16   I/O     O
cf_csel_n_opad                      0    FB4_15    E14   I/O     O
dummy_signal_opad                   1    FB4_16    E15   I/O     O

Signals Used by Logic in Function Block
  1: cf_cd1_n_ipad     12: cpu_gpio_15_ipad  23: cts_n_03_ipad 
  2: cf_cd2_n_ipad     13: cpu_gpio_18_ipad  24: cts_n_04_ipad 
  3: cf_wait_n_ipad    14: cpu_khz32_ipad    25: cts_n_05_ipad 
  4: cpu_address_in_ipads<0> 
                       15: cpu_pce1_n_ipad   26: cts_n_06_ipad 
  5: cpu_address_in_ipads<11> 
                       16: cpu_pce2_n_ipad   27: cts_n_07_ipad 
  6: cpu_address_in_ipads<12> 
                       17: cpu_preg_n_ipad   28: cts_n_08_ipad 
  7: cpu_cs3_n_ipad    18: cpu_rclk_ipad     29: cts_n_09_ipad 
  8: cpu_cs4_n_ipad    19: cpu_reset_in_n_ipad 
                                             30: cts_n_10_ipad 
  9: cpu_cs5_n_ipad    20: cts_n_00_ipad     31: cts_n_11_ipad 
 10: cpu_dqm0_n_ipad   21: cts_n_01_ipad     32: rtc_khz32_ipad 
 11: cpu_dqm1_n_ipad   22: cts_n_02_ipad    

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cf_address_opads<0> 
                  ...X.................................... 1       1
cpu_gpio_23_opad  XX...................................... 2       2
cf_pce2_n_opad    ...............X........................ 1       1
cf_pce1_n_opad    ..............X......................... 1       1
cf_csel_n_opad    ........................................ 0       0
dummy_signal_opad 
                  ..X.XXXXXXXXXX..XXXXXXXXXXXXXXXX........ 27      27
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB5 ***********************************
Number of signals used by logic mapping into function block:  3
Number of function block inputs used/remaining:               3/37
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   3/45
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cpu_gpio_19_opad                    1    FB5_1     A12   I/O     O
(unused)                            0    FB5_2           (b)      
cpu_gpio_20_opad                    1    FB5_3     D11   I/O     O
(unused)                            0    FB5_4           (b)      
(unused)                            0    FB5_5           (b)      
(unused)                            0    FB5_6           (b)      
(unused)                            0    FB5_7           (b)      
(unused)                            0    FB5_8           (b)      
(unused)                            0    FB5_9           (b)      
(unused)                            0    FB5_10          (b)      
(unused)                            0    FB5_11          (b)      
(unused)                            0    FB5_12          (b)      
cpu_gpio_22_opad                    1    FB5_13    A11   I/O     O
(unused)                            0    FB5_14    E10   I/O     I
(unused)                            0    FB5_15    B12   I/O     I
(unused)                            0    FB5_16    C11   I/O     I

Signals Used by Logic in Function Block
  1: cf_bvd_1_ipad      2: cf_bvd_2_ipad      3: cf_rdy_bsy_ipad 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cpu_gpio_19_opad  X....................................... 1       1
cpu_gpio_20_opad  .X...................................... 1       1
cpu_gpio_22_opad  ..X..................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB6 ***********************************
Number of signals used by logic mapping into function block:  7
Number of function block inputs used/remaining:               7/33
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   7/41
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
uart_address_opads<0>               1    FB6_1     F13   I/O     O
(unused)                            0    FB6_2           (b)      
cf_data_iopads<0>                   2    FB6_3     E16   I/O   I/O
(unused)                            0    FB6_4           (b)      
(unused)                            0    FB6_5           (b)      
(unused)                            0    FB6_6           (b)      
(unused)                            0    FB6_7           (b)      
(unused)                            0    FB6_8           (b)      
(unused)                            0    FB6_9           (b)      
(unused)                            0    FB6_10          (b)      
(unused)                            0    FB6_11          (b)      
(unused)                            0    FB6_12          (b)      
cf_data_iopads<11>                  2    FB6_13    F15   I/O   I/O
cf_data_iopads<12>                  2    FB6_14    G12   I/O   I/O
cf_data_iopads<10>                  2    FB6_15    F14   I/O   I/O
cf_data_iopads<13>                  2    FB6_16    G15   I/O   I/O

Signals Used by Logic in Function Block
  1: _n0003             4: cpu_data_iopads<10>.PIN 
                                              6: cpu_data_iopads<12>.PIN 
  2: cpu_address_in_ipads<1> 
                        5: cpu_data_iopads<11>.PIN 
                                              7: cpu_data_iopads<13>.PIN 
  3: cpu_data_iopads<0>.PIN 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uart_address_opads<0> 
                  .X...................................... 1       1
cf_data_iopads<0> 
                  X.X..................................... 2       2
cf_data_iopads<11> 
                  X...X................................... 2       2
cf_data_iopads<12> 
                  X....X.................................. 2       2
cf_data_iopads<10> 
                  X..X.................................... 2       2
cf_data_iopads<13> 
                  X.....X................................. 2       2
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB7 ***********************************
Number of signals used by logic mapping into function block:  4
Number of function block inputs used/remaining:               4/36
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   4/44
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cpu_gpio_07_opad                    1    FB7_1     B11   I/O     O
cpu_gpio_01_opad                    1    FB7_2     D10   I/O     O
cpu_gpio_00_opad                    1    FB7_3     A10   I/O     O
(unused)                            0    FB7_4     C10TDO/I/O      
(unused)                            0    FB7_5           (b)      
(unused)                            0    FB7_6           (b)      
(unused)                            0    FB7_7           (b)      
(unused)                            0    FB7_8           (b)      
(unused)                            0    FB7_9           (b)      
(unused)                            0    FB7_10          (b)      
(unused)                            0    FB7_11          (b)      
(unused)                            0    FB7_12          (b)      
(unused)                            0    FB7_13          (b)      
(unused)                            0    FB7_14          (b)      
cpu_ready_opad                      0    FB7_15     A9   I/O     O
uart_address_opads<4>               1    FB7_16     D9   I/O     O

Signals Used by Logic in Function Block
  1: attention_arm_ipad 
                        3: ethernet_lanled_ipad 
                                              4: lr_ri_ipad 
  2: cpu_address_in_ipads<5> 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cpu_gpio_07_opad  ...X.................................... 1       1
cpu_gpio_01_opad  ..X..................................... 1       1
cpu_gpio_00_opad  X....................................... 1       1
cpu_ready_opad    ........................................ 0       0
uart_address_opads<4> 
                  .X...................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB8 ***********************************
Number of signals used by logic mapping into function block:  9
Number of function block inputs used/remaining:               9/31
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   8/40
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cf_data_iopads<14>                  2    FB8_1     G13   I/O   I/O
(unused)                            0    FB8_2           (b)      
cf_data_iopads<15>                  2    FB8_3     F16   I/O   I/O
(unused)                            0    FB8_4           (b)      
(unused)                            0    FB8_5           (b)      
(unused)                            0    FB8_6           (b)      
(unused)                            0    FB8_7           (b)      
(unused)                            0    FB8_8           (b)      
(unused)                            0    FB8_9           (b)      
(unused)                            0    FB8_10          (b)      
(unused)                            0    FB8_11          (b)      
(unused)                            0    FB8_12          (b)      
cpu_data_iopads<0>                  3    FB8_13    G14   I/O   I/O
cpu_data_iopads<10>                 2    FB8_14    G16   I/O   I/O
cpu_data_iopads<11>                 2    FB8_15    H13   I/O   I/O
cpu_data_iopads<12>                 2    FB8_16    H12   I/O   I/O

Signals Used by Logic in Function Block
  1: _n0003             4: cf_data_iopads<11>.PIN 
                                              7: cpu_data_iopads<15>.PIN 
  2: cf_data_iopads<0>.PIN 
                        5: cf_data_iopads<12>.PIN 
                                              8: cpu_uart_cs_n_ipad 
  3: cf_data_iopads<10>.PIN 
                        6: cpu_data_iopads<14>.PIN 
                                              9: uart_data_iopads<0>.PIN 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cf_data_iopads<14> 
                  X....X.................................. 2       2
cf_data_iopads<15> 
                  X.....X................................. 2       2
cpu_data_iopads<0> 
                  .X.....XX............................... 3       3
cpu_data_iopads<10> 
                  ..X....X................................ 2       2
cpu_data_iopads<11> 
                  ...X...X................................ 2       2
cpu_data_iopads<12> 
                  ....X..X................................ 2       2
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB9 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   8/40
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
uart_address_opads<6>               1    FB9_1     P16   I/O     O
cf_data_iopads<7>                   2    FB9_2     N14   I/O   I/O
uart_address_opads<7>               1    FB9_3     R16   I/O     O
(unused)                            0    FB9_4           (b)      
(unused)                            0    FB9_5           (b)      
(unused)                            0    FB9_6           (b)      
(unused)                            0    FB9_7           (b)      
(unused)                            0    FB9_8           (b)      
(unused)                            0    FB9_9           (b)      
(unused)                            0    FB9_10          (b)      
(unused)                            0    FB9_11          (b)      
(unused)                            0    FB9_12          (b)      
cf_data_iopads<8>                   2    FB9_13    M13   I/O   I/O
cf_data_iopads<9>                   2    FB9_14    P15   I/O   I/O
cf_data_iopads<4>                   2    FB9_15    L12   I/O   I/O
uart_address_opads<3>               1    FB9_16    N16   I/O     O

Signals Used by Logic in Function Block
  1: _n0003             4: cpu_address_in_ipads<8> 
                                              7: cpu_data_iopads<8>.PIN 
  2: cpu_address_in_ipads<4> 
                        5: cpu_data_iopads<4>.PIN 
                                              8: cpu_data_iopads<9>.PIN 
  3: cpu_address_in_ipads<7> 
                        6: cpu_data_iopads<7>.PIN 
                                            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uart_address_opads<6> 
                  ..X..................................... 1       1
cf_data_iopads<7> 
                  X....X.................................. 2       2
uart_address_opads<7> 
                  ...X.................................... 1       1
cf_data_iopads<8> 
                  X.....X................................. 2       2
cf_data_iopads<9> 
                  X......X................................ 2       2
cf_data_iopads<4> 
                  X...X................................... 2       2
uart_address_opads<3> 
                  .X...................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB10 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   8/40
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cf_data_iopads<6>                   2    FB10_1    N13   I/O   I/O
uart_address_opads<5>               1    FB10_2    R15   I/O     O
cf_data_iopads<5>                   2    FB10_3    M12   I/O   I/O
(unused)                            0    FB10_4          (b)      
(unused)                            0    FB10_5          (b)      
(unused)                            0    FB10_6          (b)      
(unused)                            0    FB10_7          (b)      
(unused)                            0    FB10_8          (b)      
(unused)                            0    FB10_9          (b)      
(unused)                            0    FB10_10         (b)      
(unused)                            0    FB10_11         (b)      
(unused)                            0    FB10_12         (b)      
cf_poe_n_opad                       1    FB10_13   T16   I/O     O
cf_piow_n_opad                      1    FB10_14   P14   I/O     O
cf_pior_n_opad                      1    FB10_15   T15   I/O     O
cf_address_opads<9>                 1    FB10_16   P13   I/O     O

Signals Used by Logic in Function Block
  1: _n0003             4: cpu_data_iopads<5>.PIN 
                                              7: cpu_piow_n_ipad 
  2: cpu_address_in_ipads<6> 
                        5: cpu_data_iopads<6>.PIN 
                                              8: cpu_poe_n_ipad 
  3: cpu_address_in_ipads<9> 
                        6: cpu_pior_n_ipad  

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cf_data_iopads<6> 
                  X...X................................... 2       2
uart_address_opads<5> 
                  .X...................................... 1       1
cf_data_iopads<5> 
                  X..X.................................... 2       2
cf_poe_n_opad     .......X................................ 1       1
cf_piow_n_opad    ......X................................. 1       1
cf_pior_n_opad    .....X.................................. 1       1
cf_address_opads<9> 
                  ..X..................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB11 ***********************************
Number of signals used by logic mapping into function block:  8
Number of function block inputs used/remaining:               8/32
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   8/40
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cf_data_iopads<3>                   2    FB11_1    M14   I/O   I/O
cf_data_iopads<2>                   2    FB11_2    M16   I/O   I/O
uart_address_opads<2>               1    FB11_3    L13   I/O     O
cpu_pwait_n_opad                    1    FB11_4    N15   I/O     O
(unused)                            0    FB11_5          (b)      
(unused)                            0    FB11_6          (b)      
(unused)                            0    FB11_7          (b)      
(unused)                            0    FB11_8          (b)      
(unused)                            0    FB11_9          (b)      
(unused)                            0    FB11_10         (b)      
(unused)                            0    FB11_11         (b)      
(unused)                            0    FB11_12         (b)      
(unused)                            0    FB11_13         (b)      
cpu_iois16_n_opad                   1    FB11_14   M15   I/O     O
cf_pwe_n_opad                       1    FB11_15   L16   I/O     O
cf_preg_n_opad                      1    FB11_16   K12   I/O     O

Signals Used by Logic in Function Block
  1: _n0003             4: cpu_address_in_ipads<3> 
                                              7: cpu_preg_n_ipad 
  2: cf_iois16_n_ipad   5: cpu_data_iopads<2>.PIN 
                                              8: cpu_pwe_n_ipad 
  3: cf_wait_n_ipad     6: cpu_data_iopads<3>.PIN 
                                            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cf_data_iopads<3> 
                  X....X.................................. 2       2
cf_data_iopads<2> 
                  X...X................................... 2       2
uart_address_opads<2> 
                  ...X.................................... 1       1
cpu_pwait_n_opad  ..X..................................... 1       1
cpu_iois16_n_opad 
                  .X...................................... 1       1
cf_pwe_n_opad     .......X................................ 1       1
cf_preg_n_opad    ......X................................. 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB12 ***********************************
Number of signals used by logic mapping into function block:  10
Number of function block inputs used/remaining:               10/30
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   7/41
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cf_address_opads<8>                 1    FB12_1    R14   I/O     O
cf_address_opads<7>                 1    FB12_2    N12   I/O     O
cf_address_opads<6>                 1    FB12_3    T14   I/O     O
(unused)                            0    FB12_4          (b)      
(unused)                            0    FB12_5          (b)      
(unused)                            0    FB12_6          (b)      
(unused)                            0    FB12_7          (b)      
(unused)                            0    FB12_8          (b)      
(unused)                            0    FB12_9          (b)      
(unused)                            0    FB12_10         (b)      
(unused)                            0    FB12_11         (b)      
(unused)                            0    FB12_12         (b)      
cf_address_opads<5>                 1    FB12_13   M11   I/O     O
cf_address_opads<4>                 1    FB12_14   R13   I/O     O
spi_cs_7_n_opad                     1    FB12_15   P12   I/O     O
sr_power_on_opad                    1    FB12_16   T13   I/O     O

Signals Used by Logic in Function Block
  1: cpu_address_in_ipads<4> 
                        5: cpu_address_in_ipads<8> 
                                              8: cpu_gpio_10_ipad 
  2: cpu_address_in_ipads<5> 
                        6: cpu_gpio_08_ipad   9: cpu_gpio_13_ipad 
  3: cpu_address_in_ipads<6> 
                        7: cpu_gpio_09_ipad  10: spi_frame_n_ipad 
  4: cpu_address_in_ipads<7> 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cf_address_opads<8> 
                  ....X................................... 1       1
cf_address_opads<7> 
                  ...X.................................... 1       1
cf_address_opads<6> 
                  ..X..................................... 1       1
cf_address_opads<5> 
                  .X...................................... 1       1
cf_address_opads<4> 
                  X....................................... 1       1
spi_cs_7_n_opad   .....XXX.X.............................. 4       4
sr_power_on_opad  ........X............................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB13 ***********************************
Number of signals used by logic mapping into function block:  7
Number of function block inputs used/remaining:               7/33
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   8/40
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cf_data_iopads<1>                   2    FB13_1    L15   I/O   I/O
(unused)                            0    FB13_2          (b)      
uart_address_opads<1>               1    FB13_3    K13   I/O     O
spi_cs_5_n_opad                     1    FB13_4    K16   I/O     O
(unused)                            0    FB13_5          (b)      
(unused)                            0    FB13_6          (b)      
(unused)                            0    FB13_7          (b)      
(unused)                            0    FB13_8          (b)      
(unused)                            0    FB13_9          (b)      
(unused)                            0    FB13_10         (b)      
(unused)                            0    FB13_11         (b)      
(unused)                            0    FB13_12         (b)      
spi_cs_4_n_opad                     1    FB13_13   K14   I/O     O
spi_cs_3_n_opad                     1    FB13_14   K15   I/O     O
spi_cs_2_n_opad                     1    FB13_15   L14   I/O     O
spi_cs_1_n_opad                     1    FB13_16   J16   I/O     O

Signals Used by Logic in Function Block
  1: _n0003             4: cpu_gpio_08_ipad   6: cpu_gpio_10_ipad 
  2: cpu_address_in_ipads<2> 
                        5: cpu_gpio_09_ipad   7: spi_frame_n_ipad 
  3: cpu_data_iopads<1>.PIN 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cf_data_iopads<1> 
                  X.X..................................... 2       2
uart_address_opads<1> 
                  .X...................................... 1       1
spi_cs_5_n_opad   ...XXXX................................. 4       4
spi_cs_4_n_opad   ...XXXX................................. 4       4
spi_cs_3_n_opad   ...XXXX................................. 4       4
spi_cs_2_n_opad   ...XXXX................................. 4       4
spi_cs_1_n_opad   ...XXXX................................. 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB14 ***********************************
Number of signals used by logic mapping into function block:  6
Number of function block inputs used/remaining:               6/34
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   3/45
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
spi_cs_6_n_opad                     1    FB14_1    N11   I/O     O
(unused)                            0    FB14_2    R12   I/O     I
uplink_tx_enable_opad               1    FB14_3    T12   I/O     O
(unused)                            0    FB14_4    R11   I/O     I
(unused)                            0    FB14_5          (b)      
(unused)                            0    FB14_6          (b)      
(unused)                            0    FB14_7          (b)      
(unused)                            0    FB14_8          (b)      
(unused)                            0    FB14_9          (b)      
(unused)                            0    FB14_10         (b)      
(unused)                            0    FB14_11         (b)      
(unused)                            0    FB14_12         (b)      
uplink_rx_enable_n_opad             1    FB14_13   M10   I/O     O
(unused)                            0    FB14_14   P11   I/O     I
(unused)                            0    FB14_15         (b)      
(unused)                            0    FB14_16   N10   I/O     I

Signals Used by Logic in Function Block
  1: cpu_gpio_08_ipad   3: cpu_gpio_10_ipad   5: cpu_gpio_12_ipad 
  2: cpu_gpio_09_ipad   4: cpu_gpio_11_ipad   6: spi_frame_n_ipad 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
spi_cs_6_n_opad   XXX..X.................................. 4       4
uplink_tx_enable_opad 
                  ....X................................... 1       1
uplink_rx_enable_n_opad 
                  ...X.................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB15 ***********************************
Number of signals used by logic mapping into function block:  9
Number of function block inputs used/remaining:               9/31
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   5/43
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB15_1    J13TCK/I/O      
spi_cs_0_n_opad                     1    FB15_2    J15   I/O     O
cpu_data_iopads<8>                  2    FB15_3    J14   I/O   I/O
(unused)                            0    FB15_4          (b)      
(unused)                            0    FB15_5          (b)      
(unused)                            0    FB15_6          (b)      
(unused)                            0    FB15_7          (b)      
(unused)                            0    FB15_8          (b)      
(unused)                            0    FB15_9          (b)      
(unused)                            0    FB15_10         (b)      
(unused)                            0    FB15_11         (b)      
(unused)                            0    FB15_12         (b)      
cpu_data_iopads<15>                 2    FB15_13   H16   I/O   I/O
(unused)                            0    FB15_14         (b)      
cpu_data_iopads<14>                 2    FB15_15   H14   I/O   I/O
cpu_data_iopads<13>                 2    FB15_16   H15   I/O   I/O

Signals Used by Logic in Function Block
  1: cf_data_iopads<13>.PIN 
                        4: cf_data_iopads<8>.PIN 
                                              7: cpu_gpio_10_ipad 
  2: cf_data_iopads<14>.PIN 
                        5: cpu_gpio_08_ipad   8: cpu_uart_cs_n_ipad 
  3: cf_data_iopads<15>.PIN 
                        6: cpu_gpio_09_ipad   9: spi_frame_n_ipad 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
spi_cs_0_n_opad   ....XXX.X............................... 4       4
cpu_data_iopads<8> 
                  ...X...X................................ 2       2
cpu_data_iopads<15> 
                  ..X....X................................ 2       2
cpu_data_iopads<14> 
                  .X.....X................................ 2       2
cpu_data_iopads<13> 
                  X......X................................ 2       2
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB16 ***********************************
Number of signals used by logic mapping into function block:  4
Number of function block inputs used/remaining:               4/36
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   4/44
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
uart_cs0_n_opad                     1    FB16_1    T11   I/O     O
uart_cs1_n_opad                     1    FB16_2    R10   I/O     O
uart_rd_n_opad                      1    FB16_3    P10   I/O     O
uart_wr_n_opad                      1    FB16_4    T10   I/O     O
(unused)                            0    FB16_5          (b)      
(unused)                            0    FB16_6          (b)      
(unused)                            0    FB16_7          (b)      
(unused)                            0    FB16_8          (b)      
(unused)                            0    FB16_9          (b)      
(unused)                            0    FB16_10         (b)      
(unused)                            0    FB16_11         (b)      
(unused)                            0    FB16_12         (b)      
(unused)                            0    FB16_13         (b)      
(unused)                            0    FB16_14    N9   I/O     I
(unused)                            0    FB16_15    R9   I/O     I
(unused)                            0    FB16_16    P9   I/O     I

Signals Used by Logic in Function Block
  1: cpu_address_in_ipads<9> 
                        3: cpu_uart_cs_n_ipad 
                                              4: cpu_we_n_ipad 
  2: cpu_oe_n_ipad    

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uart_cs0_n_opad   X.X..................................... 2       2
uart_cs1_n_opad   X.X..................................... 2       2
uart_rd_n_opad    .X...................................... 1       1
uart_wr_n_opad    ...X.................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB17 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB17_1     B1   I/O     I
(unused)                            0    FB17_2     B2   I/O     I
(unused)                            0    FB17_3     C3   I/O     I
(unused)                            0    FB17_4          (b)      
(unused)                            0    FB17_5          (b)      
(unused)                            0    FB17_6          (b)      
(unused)                            0    FB17_7          (b)      
(unused)                            0    FB17_8          (b)      
(unused)                            0    FB17_9          (b)      
(unused)                            0    FB17_10         (b)      
(unused)                            0    FB17_11         (b)      
(unused)                            0    FB17_12         (b)      
(unused)                            0    FB17_13    D4   I/O     I
(unused)                            0    FB17_14    A2   I/O     I
(unused)                            0    FB17_15    A1   I/O     I
(unused)                            0    FB17_16    B3   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB18 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB18_1     C1   I/O     I
(unused)                            0    FB18_2     D3   I/O     I
(unused)                            0    FB18_3     C2   I/O     I
(unused)                            0    FB18_4     F5   I/O     I
(unused)                            0    FB18_5          (b)      
(unused)                            0    FB18_6          (b)      
(unused)                            0    FB18_7          (b)      
(unused)                            0    FB18_8          (b)      
(unused)                            0    FB18_9          (b)      
(unused)                            0    FB18_10         (b)      
(unused)                            0    FB18_11         (b)      
(unused)                            0    FB18_12         (b)      
(unused)                            0    FB18_13         (b)      
(unused)                            0    FB18_14    D1   I/O     I
(unused)                            0    FB18_15         (b)      
(unused)                            0    FB18_16    E4   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB19 ***********************************
Number of signals used by logic mapping into function block:  3
Number of function block inputs used/remaining:               3/37
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   3/45
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB19_1     C4   I/O     I
(unused)                            0    FB19_2          (b)      
(unused)                            0    FB19_3     A3   I/O     I
(unused)                            0    FB19_4     D5   I/O     I
(unused)                            0    FB19_5          (b)      
(unused)                            0    FB19_6          (b)      
(unused)                            0    FB19_7          (b)      
(unused)                            0    FB19_8          (b)      
(unused)                            0    FB19_9          (b)      
(unused)                            0    FB19_10         (b)      
(unused)                            0    FB19_11         (b)      
(unused)                            0    FB19_12         (b)      
(unused)                            0    FB19_13    B4   I/O     I
cpu_gpio_26_opad                    1    FB19_14    E6   I/O     O
reset_out_n_opad                    1    FB19_15    A4   I/O     O
ethernet_sleep_n_opad               1    FB19_16    C5   I/O     O

Signals Used by Logic in Function Block
  1: cpu_gpio_27_ipad   2: ethernet_interrupt_ipad 
                                              3: power_on_reset_n_ipad 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cpu_gpio_26_opad  .X...................................... 1       1
reset_out_n_opad  ..X..................................... 1       1
ethernet_sleep_n_opad 
                  X....................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB20 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB20_1     D2   I/O     I
(unused)                            0    FB20_2     E3   I/O     I
(unused)                            0    FB20_3          (b)      
(unused)                            0    FB20_4     E1   I/O     I
(unused)                            0    FB20_5          (b)      
(unused)                            0    FB20_6          (b)      
(unused)                            0    FB20_7          (b)      
(unused)                            0    FB20_8          (b)      
(unused)                            0    FB20_9          (b)      
(unused)                            0    FB20_10         (b)      
(unused)                            0    FB20_11         (b)      
(unused)                            0    FB20_12         (b)      
(unused)                            0    FB20_13         (b)      
(unused)                            0    FB20_14    F4   I/O     I
(unused)                            0    FB20_15    F1   I/O     I
(unused)                            0    FB20_16    G5   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB21 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB21_1     B5   I/O     I
(unused)                            0    FB21_2     D6   I/O     I
(unused)                            0    FB21_3     A5   I/O     I
(unused)                            0    FB21_4          (b)      
(unused)                            0    FB21_5          (b)      
(unused)                            0    FB21_6          (b)      
(unused)                            0    FB21_7          (b)      
(unused)                            0    FB21_8          (b)      
(unused)                            0    FB21_9          (b)      
(unused)                            0    FB21_10         (b)      
(unused)                            0    FB21_11         (b)      
(unused)                            0    FB21_12         (b)      
(unused)                            0    FB21_13    C6   I/O     I
(unused)                            0    FB21_14    B6   I/O     I
(unused)                            0    FB21_15    E7   I/O     I
cpu_gpio_16_opad                    0    FB21_16    A6   I/O     O

Signals Used by Logic in Function Block

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cpu_gpio_16_opad  ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB22 ***********************************
Number of signals used by logic mapping into function block:  3
Number of function block inputs used/remaining:               3/37
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   3/45
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cpu_gpio_04_opad                    1    FB22_1     E2   I/O     O
cpu_gpio_05_opad                    1    FB22_2     F3   I/O     O
(unused)                            0    FB22_3          (b)      
cpu_gpio_06_opad                    1    FB22_4     F2   I/O     O
(unused)                            0    FB22_5          (b)      
(unused)                            0    FB22_6          (b)      
(unused)                            0    FB22_7          (b)      
(unused)                            0    FB22_8          (b)      
(unused)                            0    FB22_9          (b)      
(unused)                            0    FB22_10         (b)      
(unused)                            0    FB22_11         (b)      
(unused)                            0    FB22_12         (b)      
(unused)                            0    FB22_13         (b)      
(unused)                            0    FB22_14    G4   I/O     I
(unused)                            0    FB22_15    G1   I/O     I
(unused)                            0    FB22_16    G3   I/O     I

Signals Used by Logic in Function Block
  1: rtc_irq_n_ipad     2: spi_interrupt_ipad 
                                              3: sr_ri_ipad 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cpu_gpio_04_opad  .X...................................... 1       1
cpu_gpio_05_opad  X....................................... 1       1
cpu_gpio_06_opad  ..X..................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB23 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB23_1     D7   I/O     I
(unused)                            0    FB23_2     B7   I/O     I
(unused)                            0    FB23_3     C7   I/O     I
(unused)                            0    FB23_4     C8   I/O     I
(unused)                            0    FB23_5          (b)      
(unused)                            0    FB23_6          (b)      
(unused)                            0    FB23_7          (b)      
(unused)                            0    FB23_8          (b)      
(unused)                            0    FB23_9          (b)      
(unused)                            0    FB23_10         (b)      
(unused)                            0    FB23_11         (b)      
(unused)                            0    FB23_12         (b)      
(unused)                            0    FB23_13         (b)      
(unused)                            0    FB23_14    A7TDI/I/O      
(unused)                            0    FB23_15    D8   I/O     I
cf_power_on_opad                    0    FB23_16    B8   I/O     O

Signals Used by Logic in Function Block

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cf_power_on_opad  ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB24 ***********************************
Number of signals used by logic mapping into function block:  1
Number of function block inputs used/remaining:               1/39
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   1/47
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB24_1     H1   I/O     I
(unused)                            0    FB24_2     H4   I/O     I
(unused)                            0    FB24_3     G2   I/O     I
net_reset_opad                      1    FB24_4     H3   I/O     O
(unused)                            0    FB24_5          (b)      
(unused)                            0    FB24_6          (b)      
(unused)                            0    FB24_7          (b)      
(unused)                            0    FB24_8          (b)      
(unused)                            0    FB24_9          (b)      
(unused)                            0    FB24_10         (b)      
(unused)                            0    FB24_11         (b)      
(unused)                            0    FB24_12         (b)      
(unused)                            0    FB24_13    J1   I/O     I
(unused)                            0    FB24_14         (b)      
(unused)                            0    FB24_15         (b)      
(unused)                            0    FB24_16    J3   I/O     I

Signals Used by Logic in Function Block
  1: power_on_reset_n_ipad 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
net_reset_opad    X....................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB25 ***********************************
Number of signals used by logic mapping into function block:  1
Number of function block inputs used/remaining:               1/39
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   1/47
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
test_opads<13>                      0    FB25_1     P2   I/O     O
test_opads<14>                      0    FB25_2     P3   I/O     O
(unused)                            0    FB25_3          (b)      
(unused)                            0    FB25_4     T1   I/O     I
(unused)                            0    FB25_5          (b)      
(unused)                            0    FB25_6          (b)      
(unused)                            0    FB25_7          (b)      
(unused)                            0    FB25_8          (b)      
(unused)                            0    FB25_9          (b)      
(unused)                            0    FB25_10         (b)      
(unused)                            0    FB25_11         (b)      
(unused)                            0    FB25_12         (b)      
(unused)                            0    FB25_13         (b)      
test_opads<11>                      0    FB25_14    N3   I/O     O
test_opads<15>                      1    FB25_15    R1   I/O     O
test_opads<9>                       0    FB25_16    M4   I/O     O

Signals Used by Logic in Function Block
  1: power_on_reset_n_ipad 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
test_opads<13>    ........................................ 0       0
test_opads<14>    ........................................ 0       0
test_opads<11>    ........................................ 0       0
test_opads<15>    X....................................... 1       1
test_opads<9>     ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB26 ***********************************
Number of signals used by logic mapping into function block:  1
Number of function block inputs used/remaining:               1/39
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   1/47
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB26_1     M5   I/O     I
uart_reset_n_opad                   1    FB26_2     N4   I/O     O
(unused)                            0    FB26_3     R2   I/O      
(unused)                            0    FB26_4     T2   I/O     I
(unused)                            0    FB26_5          (b)      
(unused)                            0    FB26_6          (b)      
(unused)                            0    FB26_7          (b)      
(unused)                            0    FB26_8          (b)      
(unused)                            0    FB26_9          (b)      
(unused)                            0    FB26_10         (b)      
(unused)                            0    FB26_11         (b)      
(unused)                            0    FB26_12         (b)      
(unused)                            0    FB26_13    P4   I/O     I
(unused)                            0    FB26_14         (b)      
(unused)                            0    FB26_15    R3   I/O     I
(unused)                            0    FB26_16    N5   I/O     I

Signals Used by Logic in Function Block
  1: power_on_reset_n_ipad 
                      

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uart_reset_n_opad 
                  X....................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB27 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
test_opads<12>                      0    FB27_1     P1   I/O     O
(unused)                            0    FB27_2          (b)      
test_opads<5>                       0    FB27_3     L5   I/O     O
test_opads<10>                      0    FB27_4     N2   I/O     O
(unused)                            0    FB27_5          (b)      
(unused)                            0    FB27_6          (b)      
(unused)                            0    FB27_7          (b)      
(unused)                            0    FB27_8          (b)      
(unused)                            0    FB27_9          (b)      
(unused)                            0    FB27_10         (b)      
(unused)                            0    FB27_11         (b)      
(unused)                            0    FB27_12         (b)      
(unused)                            0    FB27_13         (b)      
test_opads<8>                       0    FB27_14    M3   I/O     O
test_opads<4>                       0    FB27_15    L4   I/O     O
test_opads<7>                       0    FB27_16    M2   I/O     O

Signals Used by Logic in Function Block

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
test_opads<12>    ........................................ 0       0
test_opads<5>     ........................................ 0       0
test_opads<10>    ........................................ 0       0
test_opads<8>     ........................................ 0       0
test_opads<4>     ........................................ 0       0
test_opads<7>     ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB28 ***********************************
Number of signals used by logic mapping into function block:  6
Number of function block inputs used/remaining:               6/34
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   6/42
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB28_1     T3   I/O     I
(unused)                            0    FB28_2     M6   I/O     I
uart_data_iopads<7>                 2    FB28_3     R4   I/O   I/O
uart_data_iopads<6>                 2    FB28_4     P5   I/O   I/O
(unused)                            0    FB28_5          (b)      
(unused)                            0    FB28_6          (b)      
(unused)                            0    FB28_7          (b)      
(unused)                            0    FB28_8          (b)      
(unused)                            0    FB28_9          (b)      
(unused)                            0    FB28_10         (b)      
(unused)                            0    FB28_11         (b)      
(unused)                            0    FB28_12         (b)      
(unused)                            0    FB28_13         (b)      
uart_data_iopads<5>                 2    FB28_14    T4   I/O   I/O
uart_data_iopads<4>                 2    FB28_15    N6   I/O   I/O
uart_data_iopads<3>                 2    FB28_16    R5   I/O   I/O

Signals Used by Logic in Function Block
  1: cpu_data_iopads<3>.PIN 
                        3: cpu_data_iopads<5>.PIN 
                                              5: cpu_data_iopads<7>.PIN 
  2: cpu_data_iopads<4>.PIN 
                        4: cpu_data_iopads<6>.PIN 
                                              6: cpu_rnw_ipad 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uart_data_iopads<7> 
                  ....XX.................................. 2       2
uart_data_iopads<6> 
                  ...X.X.................................. 2       2
uart_data_iopads<5> 
                  ..X..X.................................. 2       2
uart_data_iopads<4> 
                  .X...X.................................. 2       2
uart_data_iopads<3> 
                  X....X.................................. 2       2
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB29 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
test_opads<2>                       0    FB29_1     L2   I/O     O
(unused)                            0    FB29_2          (b)      
test_opads<6>                       0    FB29_3     M1   I/O     O
test_opads<1>                       0    FB29_4     K5   I/O     O
(unused)                            0    FB29_5          (b)      
(unused)                            0    FB29_6          (b)      
(unused)                            0    FB29_7          (b)      
(unused)                            0    FB29_8          (b)      
(unused)                            0    FB29_9          (b)      
(unused)                            0    FB29_10         (b)      
(unused)                            0    FB29_11         (b)      
(unused)                            0    FB29_12         (b)      
test_opads<3>                       0    FB29_13    L3   I/O     O
test_opads<0>                       0    FB29_14    K4   I/O     O
(unused)                            0    FB29_15         (b)      
(unused)                            0    FB29_16    L1   I/O     I

Signals Used by Logic in Function Block

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
test_opads<2>     ........................................ 0       0
test_opads<6>     ........................................ 0       0
test_opads<1>     ........................................ 0       0
test_opads<3>     ........................................ 0       0
test_opads<0>     ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB30 ***********************************
Number of signals used by logic mapping into function block:  5
Number of function block inputs used/remaining:               5/35
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   5/43
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
uart_data_iopads<2>                 2    FB30_1     T6   I/O   I/O
uart_data_iopads<1>                 2    FB30_2     T5   I/O   I/O
uart_data_iopads<0>                 2    FB30_3     M7   I/O   I/O
(unused)                            0    FB30_4          (b)      
(unused)                            0    FB30_5          (b)      
(unused)                            0    FB30_6          (b)      
(unused)                            0    FB30_7          (b)      
(unused)                            0    FB30_8          (b)      
(unused)                            0    FB30_9          (b)      
(unused)                            0    FB30_10         (b)      
(unused)                            0    FB30_11         (b)      
(unused)                            0    FB30_12         (b)      
lr_power_on_opad                    1    FB30_13    R6   I/O     O
(unused)                            0    FB30_14    N7   I/O     I
(unused)                            0    FB30_15    T7   I/O     I
(unused)                            0    FB30_16    P6   I/O     I

Signals Used by Logic in Function Block
  1: cpu_data_iopads<0>.PIN 
                        3: cpu_data_iopads<2>.PIN 
                                              5: cpu_rnw_ipad 
  2: cpu_data_iopads<1>.PIN 
                        4: cpu_gpio_14_ipad 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uart_data_iopads<2> 
                  ..X.X................................... 2       2
uart_data_iopads<1> 
                  .X..X................................... 2       2
uart_data_iopads<0> 
                  X...X................................... 2       2
lr_power_on_opad  ...X.................................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB31 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
uart_clock_opad                     0    FB31_1     K2   I/O     O
(unused)                            0    FB31_2     K3   I/O      
(unused)                            0    FB31_3     K1TMS/I/O      
(unused)                            0    FB31_4     J4   I/O      
(unused)                            0    FB31_5          (b)      
(unused)                            0    FB31_6          (b)      
(unused)                            0    FB31_7          (b)      
(unused)                            0    FB31_8          (b)      
(unused)                            0    FB31_9          (b)      
(unused)                            0    FB31_10         (b)      
(unused)                            0    FB31_11         (b)      
(unused)                            0    FB31_12         (b)      
(unused)                            0    FB31_13         (b)      
(unused)                            0    FB31_14    J2   I/O      
(unused)                            0    FB31_15    J5   I/O     I
(unused)                            0    FB31_16    H2   I/O      

Signals Used by Logic in Function Block

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uart_clock_opad   ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB32 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB32_1     R7   I/O     I
(unused)                            0    FB32_2     P7   I/O     I
(unused)                            0    FB32_3     T8   I/O     I
(unused)                            0    FB32_4     N8   I/O     I
(unused)                            0    FB32_5          (b)      
(unused)                            0    FB32_6          (b)      
(unused)                            0    FB32_7          (b)      
(unused)                            0    FB32_8          (b)      
(unused)                            0    FB32_9          (b)      
(unused)                            0    FB32_10         (b)      
(unused)                            0    FB32_11         (b)      
(unused)                            0    FB32_12         (b)      
(unused)                            0    FB32_13         (b)      
(unused)                            0    FB32_14    R8   I/O     I
(unused)                            0    FB32_15    P8   I/O     I
(unused)                            0    FB32_16    T9   I/O     I
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.

cf_address_opads<0> = cpu_address_in_ipads<0>;

cf_address_opads<10> = cpu_address_in_ipads<10>;

cf_address_opads<1> = cpu_address_in_ipads<1>;

cf_address_opads<2> = cpu_address_in_ipads<2>;

cf_address_opads<3> = cpu_address_in_ipads<3>;

cf_address_opads<4> = cpu_address_in_ipads<4>;

cf_address_opads<5> = cpu_address_in_ipads<5>;

cf_address_opads<6> = cpu_address_in_ipads<6>;

cf_address_opads<7> = cpu_address_in_ipads<7>;

cf_address_opads<8> = cpu_address_in_ipads<8>;

cf_address_opads<9> = cpu_address_in_ipads<9>;

cf_csel_n_opad = Vcc;

cf_data_iopads<0> = cpu_data_iopads<0>.PIN;
   !cf_data_iopads<0>.OE = _n0003;

_n0003 = cpu_rnw_ipad * cpu_pktsel_ipad * !cpu_pce2_n_ipad
	# cpu_rnw_ipad * cpu_pktsel_ipad * !cpu_pce1_n_ipad;

cf_data_iopads<10> = cpu_data_iopads<10>.PIN;
   !cf_data_iopads<10>.OE = _n0003;

cf_data_iopads<11> = cpu_data_iopads<11>.PIN;
   !cf_data_iopads<11>.OE = _n0003;

cf_data_iopads<12> = cpu_data_iopads<12>.PIN;
   !cf_data_iopads<12>.OE = _n0003;

cf_data_iopads<13> = cpu_data_iopads<13>.PIN;
   !cf_data_iopads<13>.OE = _n0003;

cf_data_iopads<14> = cpu_data_iopads<14>.PIN;
   !cf_data_iopads<14>.OE = _n0003;

cf_data_iopads<15> = cpu_data_iopads<15>.PIN;
   !cf_data_iopads<15>.OE = _n0003;

cf_data_iopads<1> = cpu_data_iopads<1>.PIN;
   !cf_data_iopads<1>.OE = _n0003;

cf_data_iopads<2> = cpu_data_iopads<2>.PIN;
   !cf_data_iopads<2>.OE = _n0003;

cf_data_iopads<3> = cpu_data_iopads<3>.PIN;
   !cf_data_iopads<3>.OE = _n0003;

cf_data_iopads<4> = cpu_data_iopads<4>.PIN;
   !cf_data_iopads<4>.OE = _n0003;

cf_data_iopads<5> = cpu_data_iopads<5>.PIN;
   !cf_data_iopads<5>.OE = _n0003;

cf_data_iopads<6> = cpu_data_iopads<6>.PIN;
   !cf_data_iopads<6>.OE = _n0003;

cf_data_iopads<7> = cpu_data_iopads<7>.PIN;
   !cf_data_iopads<7>.OE = _n0003;

cf_data_iopads<8> = cpu_data_iopads<8>.PIN;
   !cf_data_iopads<8>.OE = _n0003;

cf_data_iopads<9> = cpu_data_iopads<9>.PIN;
   !cf_data_iopads<9>.OE = _n0003;

cf_pce1_n_opad = cpu_pce1_n_ipad;

cf_pce2_n_opad = cpu_pce2_n_ipad;

cf_pior_n_opad = cpu_pior_n_ipad;

cf_piow_n_opad = cpu_piow_n_ipad;

cf_poe_n_opad = cpu_poe_n_ipad;

cf_power_on_opad = Vcc;

cf_preg_n_opad = cpu_preg_n_ipad;

cf_pwe_n_opad = cpu_pwe_n_ipad;

cf_reset_opad = cpu_gpio_21_ipad;

cpu_data_iopads<0> = cpu_uart_cs_n_ipad * cf_data_iopads<0>.PIN
	# !cpu_uart_cs_n_ipad * uart_data_iopads<0>.PIN;
    cpu_data_iopads<0>.OE = N_PZ_169;

N_PZ_169 = _n0003
	# cpu_rnw_ipad * !cpu_uart_cs_n_ipad;

cpu_data_iopads<10> = cpu_uart_cs_n_ipad * cf_data_iopads<10>.PIN;
    cpu_data_iopads<10>.OE = N_PZ_169;

cpu_data_iopads<11> = cpu_uart_cs_n_ipad * cf_data_iopads<11>.PIN;
    cpu_data_iopads<11>.OE = N_PZ_169;

cpu_data_iopads<12> = cpu_uart_cs_n_ipad * cf_data_iopads<12>.PIN;
    cpu_data_iopads<12>.OE = N_PZ_169;

cpu_data_iopads<13> = cpu_uart_cs_n_ipad * cf_data_iopads<13>.PIN;
    cpu_data_iopads<13>.OE = N_PZ_169;

cpu_data_iopads<14> = cpu_uart_cs_n_ipad * cf_data_iopads<14>.PIN;
    cpu_data_iopads<14>.OE = N_PZ_169;

cpu_data_iopads<15> = cpu_uart_cs_n_ipad * cf_data_iopads<15>.PIN;
    cpu_data_iopads<15>.OE = N_PZ_169;

cpu_data_iopads<1> = cpu_uart_cs_n_ipad * cf_data_iopads<1>.PIN
	# !cpu_uart_cs_n_ipad * uart_data_iopads<1>.PIN;
    cpu_data_iopads<1>.OE = N_PZ_169;

cpu_data_iopads<2> = cpu_uart_cs_n_ipad * cf_data_iopads<2>.PIN
	# !cpu_uart_cs_n_ipad * uart_data_iopads<2>.PIN;
    cpu_data_iopads<2>.OE = N_PZ_169;

cpu_data_iopads<3> = cpu_uart_cs_n_ipad * cf_data_iopads<3>.PIN
	# !cpu_uart_cs_n_ipad * uart_data_iopads<3>.PIN;
    cpu_data_iopads<3>.OE = N_PZ_169;

cpu_data_iopads<4> = cpu_uart_cs_n_ipad * cf_data_iopads<4>.PIN
	# !cpu_uart_cs_n_ipad * uart_data_iopads<4>.PIN;
    cpu_data_iopads<4>.OE = N_PZ_169;

cpu_data_iopads<5> = cpu_uart_cs_n_ipad * cf_data_iopads<5>.PIN
	# !cpu_uart_cs_n_ipad * uart_data_iopads<5>.PIN;
    cpu_data_iopads<5>.OE = N_PZ_169;

cpu_data_iopads<6> = cpu_uart_cs_n_ipad * cf_data_iopads<6>.PIN
	# !cpu_uart_cs_n_ipad * uart_data_iopads<6>.PIN;
    cpu_data_iopads<6>.OE = N_PZ_169;

cpu_data_iopads<7> = cpu_uart_cs_n_ipad * cf_data_iopads<7>.PIN
	# !cpu_uart_cs_n_ipad * uart_data_iopads<7>.PIN;
    cpu_data_iopads<7>.OE = N_PZ_169;

cpu_data_iopads<8> = cpu_uart_cs_n_ipad * cf_data_iopads<8>.PIN;
    cpu_data_iopads<8>.OE = N_PZ_169;

cpu_data_iopads<9> = cpu_uart_cs_n_ipad * cf_data_iopads<9>.PIN;
    cpu_data_iopads<9>.OE = N_PZ_169;

cpu_gpio_00_opad = attention_arm_ipad;

cpu_gpio_01_opad = ethernet_lanled_ipad;

cpu_gpio_02_opad = uarts_0_thru_7_interrupt_ipad;

cpu_gpio_03_opad = uarts_8_thru_15_interrupt_ipad;

cpu_gpio_04_opad = spi_interrupt_ipad;

cpu_gpio_05_opad = rtc_irq_n_ipad;

cpu_gpio_06_opad = sr_ri_ipad;

cpu_gpio_07_opad = lr_ri_ipad;

cpu_gpio_16_opad = Gnd;

cpu_gpio_17_opad = Gnd;

cpu_gpio_19_opad = cf_bvd_1_ipad;

cpu_gpio_20_opad = cf_bvd_2_ipad;

cpu_gpio_22_opad = cf_rdy_bsy_ipad;

!cpu_gpio_23_opad = !cf_cd2_n_ipad * !cf_cd1_n_ipad;

cpu_gpio_24_opad = Gnd;

cpu_gpio_25_opad = Gnd;

cpu_gpio_26_opad = ethernet_interrupt_ipad;

cpu_iois16_n_opad = cf_iois16_n_ipad;

cpu_pwait_n_opad = cf_wait_n_ipad;

cpu_ready_opad = Vcc;

dummy_signal_opad = cpu_preg_n_ipad * cf_wait_n_ipad * 
	rtc_khz32_ipad * cpu_reset_in_n_ipad * cpu_rclk_ipad * 
	cpu_khz32_ipad * cpu_gpio_18_ipad * cpu_gpio_15_ipad * 
	cts_n_11_ipad * cpu_dqm1_n_ipad * cpu_dqm0_n_ipad * 
	cpu_cs5_n_ipad * cpu_cs4_n_ipad * cpu_cs3_n_ipad * 
	cpu_address_in_ipads<12> * cpu_address_in_ipads<11> * cts_n_10_ipad * 
	cts_n_09_ipad * cts_n_08_ipad * cts_n_07_ipad * cts_n_06_ipad * 
	cts_n_05_ipad * cts_n_04_ipad * cts_n_03_ipad * cts_n_02_ipad * 
	cts_n_01_ipad * cts_n_00_ipad;

ethernet_sleep_n_opad = cpu_gpio_27_ipad;

lr_power_on_opad = cpu_gpio_14_ipad;

!net_reset_opad = power_on_reset_n_ipad;

reset_out_n_opad = power_on_reset_n_ipad;

!spi_cs_0_n_opad = !spi_frame_n_ipad * !cpu_gpio_10_ipad * 
	!cpu_gpio_09_ipad * !cpu_gpio_08_ipad;

!spi_cs_1_n_opad = !spi_frame_n_ipad * !cpu_gpio_10_ipad * 
	!cpu_gpio_09_ipad * cpu_gpio_08_ipad;

!spi_cs_2_n_opad = !spi_frame_n_ipad * !cpu_gpio_10_ipad * 
	cpu_gpio_09_ipad * !cpu_gpio_08_ipad;

!spi_cs_3_n_opad = !spi_frame_n_ipad * !cpu_gpio_10_ipad * 
	cpu_gpio_09_ipad * cpu_gpio_08_ipad;

!spi_cs_4_n_opad = !spi_frame_n_ipad * cpu_gpio_10_ipad * 
	!cpu_gpio_09_ipad * !cpu_gpio_08_ipad;

!spi_cs_5_n_opad = !spi_frame_n_ipad * cpu_gpio_10_ipad * 
	!cpu_gpio_09_ipad * cpu_gpio_08_ipad;

!spi_cs_6_n_opad = !spi_frame_n_ipad * cpu_gpio_10_ipad * 
	cpu_gpio_09_ipad * !cpu_gpio_08_ipad;

!spi_cs_7_n_opad = !spi_frame_n_ipad * cpu_gpio_10_ipad * 
	cpu_gpio_09_ipad * cpu_gpio_08_ipad;

sr_power_on_opad = cpu_gpio_13_ipad;

test_opads<0> = Gnd;

test_opads<10> = Gnd;

test_opads<11> = Gnd;

test_opads<12> = Gnd;

test_opads<13> = Gnd;

test_opads<14> = Gnd;

test_opads<15> = power_on_reset_n_ipad;

test_opads<1> = Gnd;

test_opads<2> = Gnd;

test_opads<3> = Gnd;

test_opads<4> = Gnd;

test_opads<5> = Gnd;

test_opads<6> = Gnd;

test_opads<7> = Gnd;

test_opads<8> = Gnd;

test_opads<9> = Gnd;

uart_address_opads<0> = cpu_address_in_ipads<1>;

uart_address_opads<1> = cpu_address_in_ipads<2>;

uart_address_opads<2> = cpu_address_in_ipads<3>;

uart_address_opads<3> = cpu_address_in_ipads<4>;

uart_address_opads<4> = cpu_address_in_ipads<5>;

uart_address_opads<5> = cpu_address_in_ipads<6>;

uart_address_opads<6> = cpu_address_in_ipads<7>;

uart_address_opads<7> = cpu_address_in_ipads<8>;

uart_clock_opad.T := Vcc;
   uart_clock_opad.CLK  =  uart_osc_ipad;	// GCK

!uart_cs0_n_opad = !cpu_address_in_ipads<9> * !cpu_uart_cs_n_ipad;

!uart_cs1_n_opad = cpu_address_in_ipads<9> * !cpu_uart_cs_n_ipad;

uart_data_iopads<0> = cpu_data_iopads<0>.PIN;
   !uart_data_iopads<0>.OE = cpu_rnw_ipad;

uart_data_iopads<1> = cpu_data_iopads<1>.PIN;
   !uart_data_iopads<1>.OE = cpu_rnw_ipad;

uart_data_iopads<2> = cpu_data_iopads<2>.PIN;
   !uart_data_iopads<2>.OE = cpu_rnw_ipad;

uart_data_iopads<3> = cpu_data_iopads<3>.PIN;
   !uart_data_iopads<3>.OE = cpu_rnw_ipad;

uart_data_iopads<4> = cpu_data_iopads<4>.PIN;
   !uart_data_iopads<4>.OE = cpu_rnw_ipad;

uart_data_iopads<5> = cpu_data_iopads<5>.PIN;
   !uart_data_iopads<5>.OE = cpu_rnw_ipad;

uart_data_iopads<6> = cpu_data_iopads<6>.PIN;
   !uart_data_iopads<6>.OE = cpu_rnw_ipad;

uart_data_iopads<7> = cpu_data_iopads<7>.PIN;
   !uart_data_iopads<7>.OE = cpu_rnw_ipad;

uart_rd_n_opad = cpu_oe_n_ipad;

uart_reset_n_opad = power_on_reset_n_ipad;

uart_wr_n_opad = cpu_we_n_ipad;

!uplink_rx_enable_n_opad = cpu_gpio_11_ipad;

uplink_tx_enable_opad = cpu_gpio_12_ipad;



Legend:  <signame>.COMB = combinational node mapped to the same physical macrocell
                          as the FastInput "signal" (not logically related)
****************************  Device Pin Out ****************************

Device : XCR3512XL-10-FT256


                     ___________________________________
                    /                                   \
                  T |  o o o o o o o o o o o o o o o o  |
                  R |  o o o o o o o o o o o o o o o o  |
                  P |  o o o o o o o o o o o o o o o o  |
                  N |  o o o o o o o o o o o o o o o o  |
                  M |  o o o o o o o o o o o o o o o o  |
                  L |  o o o o o o o o o o o o o o o o  |
                  K |  o o o o o o o o o o o o o o o o  |
                  J |  o o o o o o o o o o o o o o o o  |
                  H |  o o o o o o o o o o o o o o o o  |
                  G |  o o o o o o o o o o o o o o o o  |
                  F |  o o o o o o o o o o o o o o o o  |
                  E |  o o o o o o o o o o o o o o o o  |
                  D |  o o o o o o o o o o o o o o o o  |
                  C |  o o o o o o o o o o o o o o o o  |
                  B |  o o o o o o o o o o o o o o o o  |
                  A |  o o o o o o o o o o o o o o o o  |
                    \___________________________________/
                       1   3   5   7   9   11  13  15  
                         2   4   6   8   10  12  14  16  

Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
 A1 cpu_pce1_n_ipad                  J1 cts_n_11_ipad                 
 A2 cpu_gpio_27_ipad                 J2 WPU                           
 A3 cpu_piow_n_ipad                  J3 cts_n_10_ipad                 
 A4 reset_out_n_opad                 J4 WPU                           
 A5 cts_n_02_ipad                    J5 rtc_irq_n_ipad                
 A6 cpu_gpio_16_opad                 J6 VCC                           
 A7 TDI                              J7 GND                           
 A8 cpu_rclk_ipad                    J8 GND                           
 A9 cpu_ready_opad                   J9 GND                           
A10 cpu_gpio_00_opad                J10 GND                           
A11 cpu_gpio_22_opad                J11 VCC                           
A12 cpu_gpio_19_opad                J12 VCC                           
A13 cpu_gpio_24_opad                J13 TCK                           
A14 cf_reset_opad                   J14 cpu_data_iopads<8>            
A15 cpu_data_iopads<4>              J15 spi_cs_0_n_opad               
A16 cpu_data_iopads<1>              J16 spi_cs_1_n_opad               
 B1 cpu_address_in_ipads<6>          K1 TMS                           
 B2 cpu_address_in_ipads<7>          K2 uart_clock_opad               
 B3 cpu_pce2_n_ipad                  K3 WPU                           
 B4 cpu_poe_n_ipad                   K4 test_opads<0>                 
 B5 cts_n_04_ipad                    K5 test_opads<1>                 
 B6 cts_n_00_ipad                    K6 VCC                           
 B7 cpu_gpio_14_ipad                 K7 GND                           
 B8 cf_power_on_opad                 K8 GND                           
 B9 cpu_khz32_ipad                   K9 GND                           
B10 uart_osc_ipad                   K10 GND                           
B11 cpu_gpio_07_opad                K11 VCC                           
B12 cpu_gpio_09_ipad                K12 cf_preg_n_opad                
B13 cpu_gpio_02_opad                K13 uart_address_opads<1>         
B14 cpu_data_iopads<6>              K14 spi_cs_4_n_opad               
B15 cpu_data_iopads<5>              K15 spi_cs_3_n_opad               
B16 cf_address_opads<2>             K16 spi_cs_5_n_opad               
 C1 cpu_address_in_ipads<5>          L1 uarts_0_thru_7_interrupt_ipad 
 C2 cpu_address_in_ipads<3>          L2 test_opads<2>                 
 C3 cpu_gpio_18_ipad                 L3 test_opads<3>                 
 C4 cpu_pior_n_ipad                  L4 test_opads<4>                 
 C5 ethernet_sleep_n_opad            L5 test_opads<5>                 
 C6 cts_n_01_ipad                    L6 GND                           
 C7 cpu_gpio_13_ipad                 L7 VCC                           
 C8 cpu_gpio_12_ipad                 L8 VCC                           
 C9 rtc_khz32_ipad                   L9 VCC                           
C10 TDO                             L10 VCC                           
C11 cpu_gpio_08_ipad                L11 GND                           
C12 cpu_gpio_03_opad                L12 cf_data_iopads<4>             
C13 cpu_data_iopads<7>              L13 uart_address_opads<2>         
C14 cpu_data_iopads<2>              L14 spi_cs_2_n_opad               
C15 cf_address_opads<3>             L15 cf_data_iopads<1>             
C16 cpu_gpio_23_opad                L16 cf_pwe_n_opad                 
 D1 cpu_address_in_ipads<1>          M1 test_opads<6>                 
 D2 cpu_address_in_ipads<9>          M2 test_opads<7>                 
 D3 cpu_address_in_ipads<4>          M3 test_opads<8>                 
 D4 cpu_gpio_21_ipad                 M4 test_opads<9>                 
 D5 cpu_pktsel_ipad                 
 M5 uarts_8_thru_15_interrupt_ipad
 D6 cts_n_03_ipad                    M6 cts_n_09_ipad                 
 D7 cpu_gpio_15_ipad                 M7 uart_data_iopads<0>           
 D8 cpu_gpio_11_ipad                 M8 VCC                           
 D9 uart_address_opads<4>            M9 VCC                           
D10 cpu_gpio_01_opad                M10 uplink_rx_enable_n_opad       
D11 cpu_gpio_20_opad                M11 cf_address_opads<5>           
D12 cpu_gpio_25_opad                M12 cf_data_iopads<5>             
D13 cpu_data_iopads<3>              M13 cf_data_iopads<8>             
D14 cf_address_opads<1>             M14 cf_data_iopads<3>             
D15 cf_address_opads<10>            M15 cpu_iois16_n_opad             
D16 cf_pce1_n_opad                  M16 cf_data_iopads<2>             
 E1 cpu_cs4_n_ipad                   N1 PE                            
 E2 cpu_gpio_04_opad                 N2 test_opads<10>                
 E3 cpu_cs3_n_ipad                   N3 test_opads<11>                
 E4 cpu_address_in_ipads<12>         N4 uart_reset_n_opad             
 E5 GND                              N5 cts_n_07_ipad                 
 E6 cpu_gpio_26_opad                 N6 uart_data_iopads<4>           
 E7 sr_ri_ipad                       N7 cf_bvd_2_ipad                 
 E8 VCC                              N8 cpu_address_in_ipads<0>       
 E9 VCC                              N9 cpu_address_in_ipads<8>       
E10 cpu_gpio_10_ipad                N10 lr_ri_ipad                    
E11 cpu_gpio_17_opad                N11 spi_cs_6_n_opad               
E12 cpu_data_iopads<9>              N12 cf_address_opads<7>           
E13 cf_address_opads<0>             N13 cf_data_iopads<6>             
E14 cf_csel_n_opad                  N14 cf_data_iopads<7>             
E15 dummy_signal_opad               N15 cpu_pwait_n_opad              
E16 cf_data_iopads<0>               N16 uart_address_opads<3>         
 F1 cpu_dqm0_n_ipad                  P1 test_opads<12>                
 F2 cpu_gpio_06_opad                 P2 test_opads<13>                
 F3 cpu_gpio_05_opad                 P3 test_opads<14>                
 F4 cpu_cs5_n_ipad                   P4 cts_n_05_ipad                 
 F5 cpu_address_in_ipads<2>          P5 uart_data_iopads<6>           
 F6 GND                              P6 cf_cd2_n_ipad                 
 F7 VCC                              P7 cf_rdy_bsy_ipad               
 F8 VCC                              P8 cpu_address_in_ipads<11>      
 F9 VCC                              P9 cpu_we_n_ipad                 
F10 VCC                             P10 uart_rd_n_opad                
F11 GND                             P11 power_on_reset_n_ipad         
F12 cf_pce2_n_opad                  P12 spi_cs_7_n_opad               
F13 uart_address_opads<0>           P13 cf_address_opads<9>           
F14 cf_data_iopads<10>              P14 cf_piow_n_opad                
F15 cf_data_iopads<11>              P15 cf_data_iopads<9>             
F16 cf_data_iopads<15>              P16 uart_address_opads<6>         
 G1 cpu_pwe_n_ipad                   R1 test_opads<15>                
 G2 ethernet_interrupt_ipad          R2 WPU                           
 G3 cpu_reset_in_n_ipad              R3 cts_n_06_ipad                 
 G4 cpu_preg_n_ipad                  R4 uart_data_iopads<7>           
 G5 cpu_dqm1_n_ipad                  R5 uart_data_iopads<3>           
 G6 VCC                              R6 lr_power_on_opad              
 G7 GND                              R7 cf_iois16_n_ipad              
 G8 GND                              R8 cpu_address_in_ipads<10>      
 G9 GND                              R9 cpu_oe_n_ipad                 
G10 GND                             R10 uart_cs1_n_opad               
G11 VCC                             R11 ethernet_lanled_ipad          
G12 cf_data_iopads<12>              R12 spi_interrupt_ipad            
G13 cf_data_iopads<14>              R13 cf_address_opads<4>           
G14 cpu_data_iopads<0>              R14 cf_address_opads<8>           
G15 cf_data_iopads<13>              R15 uart_address_opads<5>         
G16 cpu_data_iopads<10>             R16 uart_address_opads<7>         
 H1 cpu_rnw_ipad                     T1 attention_arm_ipad            
 H2 WPU                              T2 spi_frame_n_ipad              
 H3 net_reset_opad                   T3 cts_n_08_ipad                 
 H4 cpu_uart_cs_n_ipad               T4 uart_data_iopads<5>           
 H5 VCC                              T5 uart_data_iopads<1>           
 H6 VCC                              T6 uart_data_iopads<2>           
 H7 GND                              T7 cf_cd1_n_ipad                 
 H8 GND                              T8 cf_wait_n_ipad                
 H9 GND                              T9 cf_bvd_1_ipad                 
H10 GND                             T10 uart_wr_n_opad                
H11 VCC                             T11 uart_cs0_n_opad               
H12 cpu_data_iopads<12>             T12 uplink_tx_enable_opad         
H13 cpu_data_iopads<11>             T13 sr_power_on_opad              
H14 cpu_data_iopads<14>             T14 cf_address_opads<6>           
H15 cpu_data_iopads<13>             T15 cf_pior_n_opad                
H16 cpu_data_iopads<15>             T16 cf_poe_n_opad                 


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xcr3512xl-10-FT256
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Set Unused I/O Pin Termination              : PULLUP
Set Input-Only Termination                  : FLOAT
Set Universal Control Term Optimization     : OFF
Enable Foldback NANDs                       : OFF
Reserve ISP Pins                            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Input Limit                                 : 32
Pterm Limit                                 : 28
