/******************************************************************************/ /* Name : VL_OSALib.h */ /* */ /* Contents : Function prototypes for Operating System Agnostic calls */ /* */ /* Author : Andy Dowie based on work already completed by */ /* Anthony Chisolm */ /* */ /* Version : 1.01 Beta */ /* */ /* Copyright 2014 VersaLogic Corporation */ /******************************************************************************/ #ifdef WIN32 // The following ifdef block is the standard way of creating macros which make exporting // from a DLL simpler. All files within this DLL are compiled with the VL_OSALIB_EXPORTS // symbol defined on the command line. this symbol should not be defined on any project // that uses this DLL. This way any other project whose source files include this file see // VL_OSALIB_API functions as being imported from a DLL, whereas this DLL sees symbols // defined with this macro as being exported. #ifdef VL_OSALIB_EXPORTS #define VL_OSALIB_API __declspec(dllexport) #else #define VL_OSALIB_API __declspec(dllimport) #endif typedef int BOOL; #endif #ifndef FILE_DEVICE_XRPORT #define FILE_DEVICE_XRPORT 0x00008005 #define XRPORT_IOCTL_INDEX 0x805 #define IOCTL_XRPORT_READ_CONFIG_REG \ CTL_CODE(FILE_DEVICE_XRPORT , \ XRPORT_IOCTL_INDEX + 8, \ METHOD_BUFFERED, \ FILE_ANY_ACCESS) #define IOCTL_XRPORT_WRITE_CONFIG_REG \ CTL_CODE(FILE_DEVICE_XRPORT , \ XRPORT_IOCTL_INDEX + 9, \ METHOD_BUFFERED, \ FILE_ANY_ACCESS) typedef struct { unsigned char bReg; unsigned char bData; } CONFIG_WRITE, *PCONFIG_WRITE; #endif #ifdef linux #define VL_OSALIB_API #endif #ifdef __cplusplus extern "C" { #endif /* User exposed API calls that will allow access to the Versalogic driver and I/O functions*/ VL_OSALIB_API void VSL_ADCSetAnalogInputRange(unsigned char Channel, unsigned char Range); VL_OSALIB_API double VSL_ADCGetAnalogInput(unsigned char Channel, unsigned char Format); VL_OSALIB_API void VSL_DACSetAnalogOutput(unsigned char Channel, unsigned short Level); VL_OSALIB_API unsigned char VSL_GetADCType(); VL_OSALIB_API unsigned long VSL_Open(); VL_OSALIB_API unsigned long VSL_Close(); VL_OSALIB_API void VSL_GetVersion(unsigned char *Major, unsigned char *Minor, unsigned char *Release); VL_OSALIB_API unsigned char VSL_DIOGetChannelLevel(unsigned char Channel); VL_OSALIB_API void VSL_DIOSetChannelLevel(unsigned char Channel, unsigned char Level); VL_OSALIB_API void VSL_DIOSetChannelDirection(unsigned char Channel, unsigned char Direction); VL_OSALIB_API unsigned char VSL_TMRSet(unsigned char Timer, unsigned char Mode, unsigned short Count, BOOL External); VL_OSALIB_API void VSL_TMRClear(unsigned char Timer); VL_OSALIB_API unsigned short VSL_TMRGet(unsigned char Timer); VL_OSALIB_API unsigned int VSL_TMRGetEvent(unsigned char Timer); #define VL_Open VSL_Open #define VL_Close VSL_Close #define VL_GetVersion VSL_GetVersion #define VL_DIOGetChannelLevel VSL_DIOGetChannelLevel #define VL_DIOSetChannelLevel VSL_DIOSetChannelLevel #define VL_DIOSetChannelDirection VSL_DIOSetChannelDirection #define VL_ADCSetAnalogInputRange VSL_ADCSetAnalogInputRange #define VL_ADCGetAnalogInput VSL_ADCGetAnalogInput #define VL_DACSetAnalogOutput VSL_DACSetAnalogOutput #define VL_GetADCType VSL_GetADCType #define VL_TMRSet VSL_TMRSet #define VL_TMRClear VSL_TMRClear #define VL_TMRGet VSL_TMRGet #define VL_TMRGetEvent VSL_TMRGetEvent /*============================ BELOW this line are APIs for internal VersaLogic Use only ======================== ============================ Do not publish this in a released header =======================*/ /* Raw OS agnostic I/O routines - used if you decide to access the ADC/DAC/DIO devices yourself */ VL_OSALIB_API unsigned long VSL_FindProducts(); VL_OSALIB_API unsigned char OSAInput8(unsigned short); VL_OSALIB_API unsigned short OSAInput16(unsigned short); VL_OSALIB_API unsigned long OSAInput32(unsigned short); VL_OSALIB_API void OSAOutput8(unsigned short, unsigned char); VL_OSALIB_API void OSAOutput16(unsigned short, unsigned short); VL_OSALIB_API void OSAOutput32(unsigned short, unsigned long); VL_OSALIB_API void OSAWaitSPIBusyClear(); VL_OSALIB_API void OSAWaitPCIBusyClear(); VL_OSALIB_API void OSAWaitADCBusyClear(); VL_OSALIB_API void OSAWaitPCIADCBusyClear(); VL_OSALIB_API unsigned char OSADIORegRead (unsigned char Device, unsigned char Address); VL_OSALIB_API void OSADIORegWrite(unsigned char Device, unsigned char Address, unsigned char Value); /* Some general support routines used to keep your code OS agnostic */ VL_OSALIB_API void OSASleep(unsigned long); /* SPI access routine - these routines will do all of the work talking to the SPI/SPX devices for you */ VL_OSALIB_API unsigned char SPXDIOGetChannelLevel(unsigned char Channel); VL_OSALIB_API void SPXDIOSetChannelLevel(unsigned char Channel, unsigned char Level); VL_OSALIB_API void SPXDIOSetChannelDirection(unsigned char Channel, unsigned char Direction); VL_OSALIB_API unsigned char PCIAXDIOGetChannelLevel(unsigned char Channel); VL_OSALIB_API void PCIAXDIOSetChannelLevel(unsigned char Channel, unsigned char Level); VL_OSALIB_API void PCIAXDIOSetChannelDirection(unsigned char Channel, unsigned char Direction); VL_OSALIB_API unsigned char PCIU2DIOGetChannelLevel(unsigned char Channel); VL_OSALIB_API void PCIU2DIOSetChannelLevel(unsigned char Channel, unsigned char Level); VL_OSALIB_API void PCIU2DIOSetChannelDirection(unsigned char Channel, unsigned char Direction); #ifdef WIN32 BOOL U2_cfgRead( unsigned char bReg, unsigned char *pbValue ); BOOL U2_cfgWrite( unsigned char bReg, unsigned char bValue ); #else _Bool U2_cfgRead( unsigned char bReg, unsigned char *pbValue ); _Bool U2_cfgWrite( unsigned char bReg, unsigned char bValue ); #endif VL_OSALIB_API void *OSADIOGetInterruptEnableObject(unsigned char Channel, unsigned char Level); VL_OSALIB_API void *OSADIOInterruptDisable(unsigned char Channel); VL_OSALIB_API double OSASPIAnalogInput(unsigned char ClkIdle, unsigned char Irq, unsigned char DataEdge, unsigned char Auto, unsigned char FrameLength, unsigned char ClkSpeed, unsigned char Range, unsigned char Channel, unsigned char ShiftDirection); VL_OSALIB_API unsigned short OSAPCIAnalogInput(unsigned char ClkIdle, unsigned char Irq, unsigned char DataEdge, unsigned char Auto, unsigned char FrameLength, unsigned char ClkSpeed, unsigned char Range, unsigned char Channel, unsigned char ShiftDirection); VL_OSALIB_API void OSASPIAnalogOutput(unsigned char ClkIdle, unsigned char Irq, unsigned char DataEdge, unsigned char Auto, unsigned char FrameLength, unsigned char ClkSpeed, unsigned char Channel, unsigned short ADOutput, unsigned char ShiftDirection); VL_OSALIB_API unsigned long long OSAReadMSR(unsigned long MSRNumber); VL_OSALIB_API void OSAReadCPUID(int *CPUInfo, unsigned long InfoType); /* private VersaLogic routine for debug */ VL_OSALIB_API void OSADIODumpRegs(); unsigned long FindMPEe_U2(void); VL_OSALIB_API unsigned char GetDriverIRQ(void); /* Some bit defines for talking to the ADC/DAC/DIO devices */ #define VSL_PCI_DRV 0x02 #define VSL_SPI_DRV 0x01 /* board IDs - read from bits 0-6 of offset 0 */ #define VL_BOARD_EPIC_25 0x0B #define VL_BOARD_EBX_41 0x0C #define VL_BOARD_EBX_37 0x05 #define VL_BOARD_EBX_17EA 0x09 #define VL_BOARD_EBX_17EB 0x09 #define VL_BOARD_EPM_21 0x03 #define VL_BOARD_EPM_24 0x07 #define VL_BOARD_EPIC_36 0x04 #define VL_BOARD_EPM_30 0x0F #define VL_BOARD_MPE_A1A2 0x0E #define VSL_ADC_TYPE_A2 0x02 #define VSL_ADC_TYPE_A1 0x01 #define DIO_INPUT 0x01 #define DIO_OUTPUT 0x00 #define TIMER_TEST_ON 0x40 #define DIO_IODIRA_OFF 0x00 #define DIO_IODIRB_OFF 0x01 #define DIO_GPIOA_OFF 0x12 #define DIO_GPIOB_OFF 0x13 #define DIO_INTFA_OFF 0x0E #define DIO_INTFB_OFF 0x0F #define DIO_CAPA_OFF 0x10 #define DIO_CAPB_OFF 0x11 #define DIO_INTCONA_OFF 0x08 #define DIO_INTCONB_OFF 0x09 #define DIO_INTENA_OFF 0x04 #define DIO_INTENB_OFF 0x05 #define DIO_IOCONA_OFF 0x0A #define DIO_IOCONB_OFF 0x0B #define DIO_DEV0 0x40 #define DIO_DEV1 0x42 #define DIO_DIRA_OFF 0x00 #define DIO_DIRB_OFF 0x01 #define DIO_WRITE 0x00 #define DIO_READ 0x01 #define DIO_CHANNEL_LOW 0x00 #define DIO_CHANNEL_HIGH 0x01 #define DIO_ICON_OFF 0x0A #define DIO_HA_ENABLE 0x08 #define SPI_IDLE_HIGH 0x80 #define SPI_IDLE_LOW 0x00 #define SPI_EDGE_FALLING 0x40 #define SPI_EDGE_RISING 0x00 #define SPI_FRAME_8 0x00 #define SPI_FRAME_16 0x10 #define SPI_FRAME_24 0x20 #define SPI_FRAME_32 0x30 #define SPI_SS_MANUAL 0x08 #define SPI_SS_AUTO 0x00 #define SPI_IAD1857E 0x05 #define SPI_IAD1857E_HIGH 0x03 #define SPI_I23S17 0x06 #define SPI_DA2634E 0x07 #define SPI_DA2634E_HIGH 0x04 #define SPX_CS_SS0 0x01 #define SPX_CS_SS1 0x02 #define SPX_CS_SS2 0x03 #define SPX_CS_SS3 0x04 #define DIO_CS_SS0 0x40 #define DIO_CS_SS1 0x50 #define DIO_CS_SS2 0x60 #define DIO_CS_SS3 0x70 #define AO_CS_SS0 0x40 #define AO_CS_SS1 0x50 #define AO_CS_SS2 0x60 #define AO_CS_SS3 0x70 #define AI_CS_SS0 0x04 #define AI_CS_SS1 0x05 #define AI_CS_SS2 0x06 #define AI_CS_SS3 0x07 #define SPX_AD7490_SS0 0x0a #define SPX_AD7490_SS1 0x0b #define SPX_AD7490_SS2 0x0c #define SPX_AD7490_SS3 0x0d #define SPX_AD7927_SS0 0x02 #define SPX_AD7927_SS1 0x03 #define SPX_AD7927_SS2 0x08 #define SPX_AD7927_SS3 0x09 #define SPI_CLK_1MHz 0x00 #define SPI_CLK_2MHz 0x10 #define SPI_CLK_4MHz 0x20 #define SPI_CLK_8MHz 0x30 #define SPI_DIR_LEFT 0x00 #define SPI_DIR_RIGHT 0x04 #define IRQ_CONTROL_OFF 0x03 #define IRQ_STATUS_OFF 0x04 #define SPI_CONTROL_OFF 0x08 #define SPI_STATUS_OFF 0x09 #define SPI_DATA0_OFF 0x0A #define SPI_DATA1_OFF 0x0B #define SPI_DATA2_OFF 0x0C #define SPI_DATA3_OFF 0x0D #define SPI_CUSTOM_OFF 0x0E #define SPI_ADCONSTAT_OFF 0x0F #define TMR_TCNTRL 0x05 #define TMR_TBASEMS 0x06 #define TMR_TBASELS 0x07 #define PCI_IRQ_STATUS_OFF 0x8004 #define PCI_GPIO_CFG 0x8005 #define PCI_GPIO_OUT 0x8006 #define PCI_GPIO_IN 0x8007 #define PCI_CONTROL_OFF 0x8008 #define PCI_STATUS_OFF 0x8009 #define PCI_DATA0_OFF 0x800A #define PCI_DATA1_OFF 0x800B #define PCI_DATA2_OFF 0x800C #define PCI_DATA3_OFF 0x800D #define PCI_CUSTOM_OFF 0x800E #define PCI_ADCONSTAT_OFF 0x800F #define SPI_SER_IRQ_EN 0x04 #define AI_RAW 0x00 #define AI_VOLTS 0x01 #define SPI_AI_CHANNEL_1 0x00 #define SPI_AI_CHANNEL_2 0x40 #define SPI_AI_CHANNEL_3 0x10 #define SPI_AI_CHANNEL_4 0x50 #define SPI_AI_CHANNEL_5 0x20 #define SPI_AI_CHANNEL_6 0x60 #define SPI_AI_CHANNEL_7 0x30 #define SPI_AI_CHANNEL_8 0x70 #define SPI_AI_CHANNEL_9 0x01 #define SPI_AI_CHANNEL_10 0x41 #define SPI_AI_CHANNEL_11 0x11 #define SPI_AI_CHANNEL_12 0x51 #define SPI_AI_CHANNEL_13 0x21 #define SPI_AI_CHANNEL_14 0x61 #define SPI_AI_CHANNEL_15 0x31 #define SPI_AI_CHANNEL_16 0x71 #define SPX_AI_SS0_CHANNEL_1 0x04 #define SPX_AI_SS0_CHANNEL_2 0x14 #define SPX_AI_SS0_CHANNEL_3 0x24 #define SPX_AI_SS0_CHANNEL_4 0x34 #define SPX_AI_SS0_CHANNEL_5 0x44 #define SPX_AI_SS0_CHANNEL_6 0x54 #define SPX_AI_SS0_CHANNEL_7 0x64 #define SPX_AI_SS0_CHANNEL_8 0x74 #define SPX_AI_SS1_CHANNEL_1 0x05 #define SPX_AI_SS1_CHANNEL_2 0x15 #define SPX_AI_SS1_CHANNEL_3 0x25 #define SPX_AI_SS1_CHANNEL_4 0x35 #define SPX_AI_SS1_CHANNEL_5 0x45 #define SPX_AI_SS1_CHANNEL_6 0x55 #define SPX_AI_SS1_CHANNEL_7 0x65 #define SPX_AI_SS1_CHANNEL_8 0x75 #define SPX_AI_SS2_CHANNEL_1 0x06 #define SPX_AI_SS2_CHANNEL_2 0x16 #define SPX_AI_SS2_CHANNEL_3 0x26 #define SPX_AI_SS2_CHANNEL_4 0x36 #define SPX_AI_SS2_CHANNEL_5 0x46 #define SPX_AI_SS2_CHANNEL_6 0x56 #define SPX_AI_SS2_CHANNEL_7 0x66 #define SPX_AI_SS2_CHANNEL_8 0x76 #define SPX_AI_SS3_CHANNEL_1 0x07 #define SPX_AI_SS3_CHANNEL_2 0x17 #define SPX_AI_SS3_CHANNEL_3 0x27 #define SPX_AI_SS3_CHANNEL_4 0x37 #define SPX_AI_SS3_CHANNEL_5 0x47 #define SPX_AI_SS3_CHANNEL_6 0x57 #define SPX_AI_SS3_CHANNEL_7 0x67 #define SPX_AI_SS3_CHANNEL_8 0x77 #define SPX_AD7490_AI_SS0_CHANNEL_1 0x0a #define SPX_AD7490_AI_SS0_CHANNEL_2 0x1a #define SPX_AD7490_AI_SS0_CHANNEL_3 0x2a #define SPX_AD7490_AI_SS0_CHANNEL_4 0x3a #define SPX_AD7490_AI_SS0_CHANNEL_5 0x4a #define SPX_AD7490_AI_SS0_CHANNEL_6 0x5a #define SPX_AD7490_AI_SS0_CHANNEL_7 0x6a #define SPX_AD7490_AI_SS0_CHANNEL_8 0x7a #define SPX_AD7490_AI_SS0_CHANNEL_9 0x8a #define SPX_AD7490_AI_SS0_CHANNEL_10 0x9a #define SPX_AD7490_AI_SS0_CHANNEL_11 0xaa #define SPX_AD7490_AI_SS0_CHANNEL_12 0xba #define SPX_AD7490_AI_SS0_CHANNEL_13 0xca #define SPX_AD7490_AI_SS0_CHANNEL_14 0xda #define SPX_AD7490_AI_SS0_CHANNEL_15 0xea #define SPX_AD7490_AI_SS0_CHANNEL_16 0xfa #define SPX_AD7490_AI_SS1_CHANNEL_1 0x0b #define SPX_AD7490_AI_SS1_CHANNEL_2 0x1b #define SPX_AD7490_AI_SS1_CHANNEL_3 0x2b #define SPX_AD7490_AI_SS1_CHANNEL_4 0x3b #define SPX_AD7490_AI_SS1_CHANNEL_5 0x4b #define SPX_AD7490_AI_SS1_CHANNEL_6 0x5b #define SPX_AD7490_AI_SS1_CHANNEL_7 0x6b #define SPX_AD7490_AI_SS1_CHANNEL_8 0x7b #define SPX_AD7490_AI_SS1_CHANNEL_9 0x8b #define SPX_AD7490_AI_SS1_CHANNEL_10 0x9b #define SPX_AD7490_AI_SS1_CHANNEL_11 0xab #define SPX_AD7490_AI_SS1_CHANNEL_12 0xbb #define SPX_AD7490_AI_SS1_CHANNEL_13 0xcb #define SPX_AD7490_AI_SS1_CHANNEL_14 0xdb #define SPX_AD7490_AI_SS1_CHANNEL_15 0xeb #define SPX_AD7490_AI_SS1_CHANNEL_16 0xfb #define SPX_AD7490_AI_SS2_CHANNEL_1 0x0c #define SPX_AD7490_AI_SS2_CHANNEL_2 0x1c #define SPX_AD7490_AI_SS2_CHANNEL_3 0x2c #define SPX_AD7490_AI_SS2_CHANNEL_4 0x3c #define SPX_AD7490_AI_SS2_CHANNEL_5 0x4c #define SPX_AD7490_AI_SS2_CHANNEL_6 0x5c #define SPX_AD7490_AI_SS2_CHANNEL_7 0x6c #define SPX_AD7490_AI_SS2_CHANNEL_8 0x7c #define SPX_AD7490_AI_SS2_CHANNEL_9 0x8c #define SPX_AD7490_AI_SS2_CHANNEL_10 0x9c #define SPX_AD7490_AI_SS2_CHANNEL_11 0xac #define SPX_AD7490_AI_SS2_CHANNEL_12 0xbc #define SPX_AD7490_AI_SS2_CHANNEL_13 0xcc #define SPX_AD7490_AI_SS2_CHANNEL_14 0xdc #define SPX_AD7490_AI_SS2_CHANNEL_15 0xec #define SPX_AD7490_AI_SS2_CHANNEL_16 0xfc #define SPX_AD7490_AI_SS3_CHANNEL_1 0x0d #define SPX_AD7490_AI_SS3_CHANNEL_2 0x1d #define SPX_AD7490_AI_SS3_CHANNEL_3 0x2d #define SPX_AD7490_AI_SS3_CHANNEL_4 0x3d #define SPX_AD7490_AI_SS3_CHANNEL_5 0x4d #define SPX_AD7490_AI_SS3_CHANNEL_6 0x5d #define SPX_AD7490_AI_SS3_CHANNEL_7 0x6d #define SPX_AD7490_AI_SS3_CHANNEL_8 0x7d #define SPX_AD7490_AI_SS3_CHANNEL_9 0x8d #define SPX_AD7490_AI_SS3_CHANNEL_10 0x9d #define SPX_AD7490_AI_SS3_CHANNEL_11 0xad #define SPX_AD7490_AI_SS3_CHANNEL_12 0xbd #define SPX_AD7490_AI_SS3_CHANNEL_13 0xcd #define SPX_AD7490_AI_SS3_CHANNEL_14 0xdd #define SPX_AD7490_AI_SS3_CHANNEL_15 0xed #define SPX_AD7490_AI_SS3_CHANNEL_16 0xfd #define SPX_AD7927_AI_SS0_CHANNEL_1 0x02 #define SPX_AD7927_AI_SS0_CHANNEL_2 0x12 #define SPX_AD7927_AI_SS0_CHANNEL_3 0x22 #define SPX_AD7927_AI_SS0_CHANNEL_4 0x32 #define SPX_AD7927_AI_SS0_CHANNEL_5 0x42 #define SPX_AD7927_AI_SS0_CHANNEL_6 0x52 #define SPX_AD7927_AI_SS0_CHANNEL_7 0x62 #define SPX_AD7927_AI_SS0_CHANNEL_8 0x72 #define SPX_AD7927_AI_SS1_CHANNEL_1 0x03 #define SPX_AD7927_AI_SS1_CHANNEL_2 0x13 #define SPX_AD7927_AI_SS1_CHANNEL_3 0x23 #define SPX_AD7927_AI_SS1_CHANNEL_4 0x33 #define SPX_AD7927_AI_SS1_CHANNEL_5 0x43 #define SPX_AD7927_AI_SS1_CHANNEL_6 0x53 #define SPX_AD7927_AI_SS1_CHANNEL_7 0x63 #define SPX_AD7927_AI_SS1_CHANNEL_8 0x73 #define SPX_AD7927_AI_SS2_CHANNEL_1 0x08 #define SPX_AD7927_AI_SS2_CHANNEL_2 0x18 #define SPX_AD7927_AI_SS2_CHANNEL_3 0x28 #define SPX_AD7927_AI_SS2_CHANNEL_4 0x38 #define SPX_AD7927_AI_SS2_CHANNEL_5 0x48 #define SPX_AD7927_AI_SS2_CHANNEL_6 0x58 #define SPX_AD7927_AI_SS2_CHANNEL_7 0x68 #define SPX_AD7927_AI_SS2_CHANNEL_8 0x78 #define SPX_AD7927_AI_SS3_CHANNEL_1 0x09 #define SPX_AD7927_AI_SS3_CHANNEL_2 0x19 #define SPX_AD7927_AI_SS3_CHANNEL_3 0x29 #define SPX_AD7927_AI_SS3_CHANNEL_4 0x39 #define SPX_AD7927_AI_SS3_CHANNEL_5 0x49 #define SPX_AD7927_AI_SS3_CHANNEL_6 0x59 #define SPX_AD7927_AI_SS3_CHANNEL_7 0x69 #define SPX_AD7927_AI_SS3_CHANNEL_8 0x79 #define SPI_AO_CHANNEL_1 0x00 #define SPI_AO_CHANNEL_2 0x01 #define SPI_AO_CHANNEL_3 0x02 #define SPI_AO_CHANNEL_4 0x03 #define SPI_AO_CHANNEL_5 0x04 #define SPI_AO_CHANNEL_6 0x05 #define SPI_AO_CHANNEL_7 0x06 #define SPI_AO_CHANNEL_8 0x07 #define SPX_AO_SS0_CHANNEL_1 0x40 #define SPX_AO_SS0_CHANNEL_2 0x41 #define SPX_AO_SS0_CHANNEL_3 0x42 #define SPX_AO_SS0_CHANNEL_4 0x43 #define SPX_AO_SS0_CHANNEL_5 0x44 #define SPX_AO_SS0_CHANNEL_6 0x45 #define SPX_AO_SS0_CHANNEL_7 0x46 #define SPX_AO_SS0_CHANNEL_8 0x47 #define SPX_AO_SS1_CHANNEL_1 0x50 #define SPX_AO_SS1_CHANNEL_2 0x51 #define SPX_AO_SS1_CHANNEL_3 0x52 #define SPX_AO_SS1_CHANNEL_4 0x53 #define SPX_AO_SS1_CHANNEL_5 0x54 #define SPX_AO_SS1_CHANNEL_6 0x55 #define SPX_AO_SS1_CHANNEL_7 0x56 #define SPX_AO_SS1_CHANNEL_8 0x57 #define SPX_AO_SS2_CHANNEL_1 0x60 #define SPX_AO_SS2_CHANNEL_2 0x61 #define SPX_AO_SS2_CHANNEL_3 0x62 #define SPX_AO_SS2_CHANNEL_4 0x63 #define SPX_AO_SS2_CHANNEL_5 0x64 #define SPX_AO_SS2_CHANNEL_6 0x65 #define SPX_AO_SS2_CHANNEL_7 0x66 #define SPX_AO_SS2_CHANNEL_8 0x67 #define SPX_AO_SS3_CHANNEL_1 0x70 #define SPX_AO_SS3_CHANNEL_2 0x71 #define SPX_AO_SS3_CHANNEL_3 0x72 #define SPX_AO_SS3_CHANNEL_4 0x73 #define SPX_AO_SS3_CHANNEL_5 0x74 #define SPX_AO_SS3_CHANNEL_6 0x75 #define SPX_AO_SS3_CHANNEL_7 0x76 #define SPX_AO_SS3_CHANNEL_8 0x77 #define PCI_AI_CHANNEL_1 0x0E #define PCI_AI_CHANNEL_2 0x4E #define PCI_AI_CHANNEL_3 0x1E #define PCI_AI_CHANNEL_4 0x5E #define PCI_AI_CHANNEL_5 0x2E #define PCI_AI_CHANNEL_6 0x6E #define PCI_AI_CHANNEL_7 0x3E #define PCI_AI_CHANNEL_8 0x7E #define DIO_CHANNEL_1 0x00 #define DIO_CHANNEL_2 0x01 #define DIO_CHANNEL_3 0x02 #define DIO_CHANNEL_4 0x03 #define DIO_CHANNEL_5 0x04 #define DIO_CHANNEL_6 0x05 #define DIO_CHANNEL_7 0x06 #define DIO_CHANNEL_8 0x07 #define DIO_CHANNEL_9 0x08 #define DIO_CHANNEL_10 0x09 #define DIO_CHANNEL_11 0x0a #define DIO_CHANNEL_12 0x0b #define DIO_CHANNEL_13 0x0c #define DIO_CHANNEL_14 0x0d #define DIO_CHANNEL_15 0x0e #define DIO_CHANNEL_16 0x0f #define DIO_CHANNEL_17 0x10 #define DIO_CHANNEL_18 0x11 #define DIO_CHANNEL_19 0x12 #define DIO_CHANNEL_20 0x13 #define DIO_CHANNEL_21 0x14 #define DIO_CHANNEL_22 0x15 #define DIO_CHANNEL_23 0x16 #define DIO_CHANNEL_24 0x17 #define DIO_CHANNEL_25 0x18 #define DIO_CHANNEL_26 0x19 #define DIO_CHANNEL_27 0x1a #define DIO_CHANNEL_28 0x1b #define DIO_CHANNEL_29 0x1c #define DIO_CHANNEL_30 0x1d #define DIO_CHANNEL_31 0x1e #define DIO_CHANNEL_32 0x1f #define DIO_SS0_CHANNEL_1 0x40 #define DIO_SS0_CHANNEL_2 0x41 #define DIO_SS0_CHANNEL_3 0x42 #define DIO_SS0_CHANNEL_4 0x43 #define DIO_SS0_CHANNEL_5 0x44 #define DIO_SS0_CHANNEL_6 0x45 #define DIO_SS0_CHANNEL_7 0x46 #define DIO_SS0_CHANNEL_8 0x47 #define DIO_SS0_CHANNEL_9 0x48 #define DIO_SS0_CHANNEL_10 0x49 #define DIO_SS0_CHANNEL_11 0x4a #define DIO_SS0_CHANNEL_12 0x4b #define DIO_SS0_CHANNEL_13 0x4c #define DIO_SS0_CHANNEL_14 0x4d #define DIO_SS0_CHANNEL_15 0x4e #define DIO_SS0_CHANNEL_16 0x4f #define DIO_SS1_CHANNEL_1 0x50 #define DIO_SS1_CHANNEL_2 0x51 #define DIO_SS1_CHANNEL_3 0x52 #define DIO_SS1_CHANNEL_4 0x53 #define DIO_SS1_CHANNEL_5 0x54 #define DIO_SS1_CHANNEL_6 0x55 #define DIO_SS1_CHANNEL_7 0x56 #define DIO_SS1_CHANNEL_8 0x57 #define DIO_SS1_CHANNEL_9 0x58 #define DIO_SS1_CHANNEL_10 0x59 #define DIO_SS1_CHANNEL_11 0x5a #define DIO_SS1_CHANNEL_12 0x5b #define DIO_SS1_CHANNEL_13 0x5c #define DIO_SS1_CHANNEL_14 0x5d #define DIO_SS1_CHANNEL_15 0x5e #define DIO_SS1_CHANNEL_16 0x5f #define DIO_SS2_CHANNEL_1 0x60 #define DIO_SS2_CHANNEL_2 0x61 #define DIO_SS2_CHANNEL_3 0x62 #define DIO_SS2_CHANNEL_4 0x63 #define DIO_SS2_CHANNEL_5 0x64 #define DIO_SS2_CHANNEL_6 0x65 #define DIO_SS2_CHANNEL_7 0x66 #define DIO_SS2_CHANNEL_8 0x67 #define DIO_SS2_CHANNEL_9 0x68 #define DIO_SS2_CHANNEL_10 0x69 #define DIO_SS2_CHANNEL_11 0x6a #define DIO_SS2_CHANNEL_12 0x6b #define DIO_SS2_CHANNEL_13 0x6c #define DIO_SS2_CHANNEL_14 0x6d #define DIO_SS2_CHANNEL_15 0x6e #define DIO_SS2_CHANNEL_16 0x6f #define DIO_SS3_CHANNEL_1 0x70 #define DIO_SS3_CHANNEL_2 0x71 #define DIO_SS3_CHANNEL_3 0x72 #define DIO_SS3_CHANNEL_4 0x73 #define DIO_SS3_CHANNEL_5 0x74 #define DIO_SS3_CHANNEL_6 0x75 #define DIO_SS3_CHANNEL_7 0x76 #define DIO_SS3_CHANNEL_8 0x77 #define DIO_SS3_CHANNEL_9 0x78 #define DIO_SS3_CHANNEL_10 0x79 #define DIO_SS3_CHANNEL_11 0x7a #define DIO_SS3_CHANNEL_12 0x7b #define DIO_SS3_CHANNEL_13 0x7c #define DIO_SS3_CHANNEL_14 0x7d #define DIO_SS3_CHANNEL_15 0x7e #define DIO_SS3_CHANNEL_16 0x7f #define DIO_AX_CHANNEL_1 0x80 #define DIO_AX_CHANNEL_2 0x81 #define DIO_AX_CHANNEL_3 0x82 #define AX_CHANNEL_MASK 0x0F #define DIO_U2_CHANNEL_1 0xA0 #define DIO_U2_CHANNEL_2 0xA1 #define DIO_U2_CHANNEL_3 0xA2 #define DIO_U2_CHANNEL_4 0xA3 #define DIO_U2_CHANNEL_5 0xA4 #define DIO_U2_CHANNEL_6 0xA5 #define DIO_U2_CHANNEL_7 0xA6 #define DIO_U2_CHANNEL_8 0xA7 #define DIO_U2_CHANNEL_9 0xA8 #define DIO_U2_CHANNEL_10 0xA9 #define DIO_U2_CHANNEL_11 0xAA #define DIO_U2_CHANNEL_12 0xAB #define DIO_U2_CHANNEL_13 0xAC #define U2_CHANNEL_MASK 0x0F #define EXAR_DVID 0x84 #define DIO_U2_BASE 0x080 #define DIO_U2_DREV 0x08C #define DIO_U2_DVID 0x08D #define DIO_U2_REGB 0x08E #define DIO_U2_MPIOINT_7_0 0x08F #define DIO_U2_MPIOINT_15_8 0x095 #define DIO_U2_MPIOLVL_7_0 0x090 #define DIO_U2_MPIOLVL_15_8 0x096 #define DIO_U2_MPIO3T_7_0 0x091 #define DIO_U2_MPIO3T_15_8 0x097 #define DIO_U2_MPIOINV_7_0 0x092 #define DIO_U2_MPIOINV_15_8 0x098 #define DIO_U2_MPIOSEL_7_0 0x093 #define DIO_U2_MPIOSEL_15_8 0x099 #define DIO_U2_MPIOOD_7_0 0x094 #define DIO_U2_MPIOOD_15_8 0x09A #define SPI_RANGE_PM5V 0x00 #define SPI_RANGE_PM10V 0x04 #define SPI_RANGE_0_5V 0x08 #define SPI_RANGE_0_10V 0x0C #define PCI_RANGE_PM5V 0x00 #define PCI_RANGE_PM10V 0x04 #define PCI_RANGE_0_5V 0x08 #define PCI_RANGE_0_10V 0x0C #define SPI_BUSY 0x01 #define ADC_BUSY 0x04 #define SPI_START_CONVRS 0x01 #define AD7490_LOAD_CTRL 0x80 #define AD7490_PWR_NORM 0x03 #define AD7490_RANGE_SINGLE 0x20 #define AD7490_RANGE_DOUBLE 0x00 #define AD7490_CODE_BINARY 0x10 #define TMR8254_DEFAULT_BASE 0x10 // always 16 bytes past the base address of the FPGA registers #define TMR8254_COUNTER0 TMR8254_DEFAULT_BASE // always 16 bytes past the base address of the FPGA registers #define TMR8254_COUNTER1 TMR8254_DEFAULT_BASE+1 #define TMR8254_COUNTER2 TMR8254_DEFAULT_BASE+2 #define TMR8254_CONTROL TMR8254_DEFAULT_BASE+3 #define TMR8254_MODE0 0x00 #define TMR8254_MODE1 0x02 #define TMR8254_MODE2 0x04 #define TMR8254_MODE3 0x06 #define TMR8254_MODE4 0x08 #define TMR8254_MODE5 0x0a #define TMR8254_CNT0 0x00 #define TMR8254_CNT1 0x40 #define TMR8254_CNT2 0x80 #define TMR8254_CNTRB 0xc0 #define TMR8254_CNT_LATCH 0x00 #define TMR8254_STS_LATCH_OFF 0x10 #define TMR8254_16BIT 0x10 #define TMR8254_LATCH 0x00 #define TMR8254_RW_LSB 0x10 #define TMR8254_RW_MSB 0x20 #define TMR8254_RW_BOTH 0x30 #define TMR8254_TM0SEL_EX 0x04 #define TMR8254_TM1SEL_EX 0x08 #define TMR8254_TIM0GATE 0x20 #define TMR8254_TIM1GATE 0x40 #define TMR8254_TIM2GATE 0x80 #define TMR8254_TM12MODE16 0x10 #define VL_TIMER_MODE0 0 #define VL_TIMER_MODE1 1 #define VL_TIMER_MODE2 2 #define VL_TIMER_MODE3 3 #define VL_TIMER_MODE4 4 #define VL_TIMER_MODE5 5 #define TMR8254_BCD 0x01 #define VL_MAX_8254_TIMERS 3 #define FPGA_TMR #define DTSMASK 0x7f0000 #define TJMAX 100 #ifdef __cplusplus } #endif