library ieee;
use ieee.std_logic_1164.all;

entity active_low_1_to_8_decoder is	  	
	port (
		enable_n		: in  std_logic;
		sel_adr		: in  std_logic_vector(2 downto 0);
		output_0_n	: out std_logic;	
		output_1_n	: out std_logic;	
		output_2_n	: out std_logic;	
		output_3_n	: out std_logic;	
		output_4_n	: out std_logic;	
		output_5_n	: out std_logic;
		output_6_n	: out std_logic;	
		output_7_n	: out std_logic					
	);
end active_low_1_to_8_decoder;

architecture synthesis of active_low_1_to_8_decoder is
begin
	decoder : process (enable_n, sel_adr)
	begin
		output_0_n	<= '1';	
		output_1_n	<= '1';
		output_2_n	<= '1';
		output_3_n	<= '1';
		output_4_n	<= '1';
		output_5_n     <= '1';
		output_6_n	<= '1';
		output_7_n     <= '1';		
		if enable_n = '0' then
			case sel_adr is
				when "000" => output_0_n <= '0';
				when "001" => output_1_n <= '0';
				when "010" => output_2_n <= '0';
				when "011" => output_3_n <= '0';
				when "100" => output_4_n <= '0';
				when "101" => output_5_n <= '0';
				when "110" => output_6_n <= '0';
				when "111" => output_7_n <= '0';
				when others => null;
			end case;
		end if;
	end process;
end synthesis;