library ieee;
use ieee.std_logic_1164.all;

entity bus_tristate_buffer is	  	
	generic	(  
		width 	: integer := 8
	);
	port (
		oe		: in  std_logic;
		ip		: in  std_logic_vector(width - 1 downto 0);	
		op		: out std_logic_vector(width - 1 downto 0)		
	);
end bus_tristate_buffer;

architecture synthesis of bus_tristate_buffer is
begin
	op <= ip when oe = '1' else (others => 'Z');
end synthesis;