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<!DOCTYPE document SYSTEM "file:///C:/Xilinx/xpla3/data/xmlReportxpla3.dtd">
<document><ascFile>sidearm_glue_logic.rpt</ascFile><devFile>C:/Xilinx/xpla3/data/xcr3512xl.chp</devFile><mfdFile>sidearm_glue_logic.mfd</mfdFile><htmlFile logo="coolrunner_logo.jpg" pin_legend="pinlegend.htm" logic_legend="logiclegend.htm"/><header pkg="FT256" date=" 1-24-2004" time="  2:44PM" speed="-10" design="sidearm_glue_logic" device="XCR3512XL" status="1" eqnType="1" version="1.0" statusStr="Successful" swVersion="G.26"/><inputs id="attention_arm_ipad"/><inputs id="cpu_address_in_ipads0_SPECSIG"/><inputs id="cpu_address_in_ipads10_SPECSIG"/><inputs id="cpu_address_in_ipads1_SPECSIG"/><inputs id="cpu_address_in_ipads2_SPECSIG"/><inputs id="cpu_address_in_ipads3_SPECSIG"/><inputs id="cpu_address_in_ipads4_SPECSIG"/><inputs id="cpu_address_in_ipads5_SPECSIG"/><inputs id="cpu_address_in_ipads6_SPECSIG"/><inputs id="cpu_address_in_ipads7_SPECSIG"/><inputs id="cpu_address_in_ipads8_SPECSIG"/><inputs id="cpu_address_in_ipads9_SPECSIG"/><inputs id="cf_bvd_1_ipad"/><inputs id="cf_bvd_2_ipad"/><inputs id="cf_cd1_n_ipad"/><inputs id="cf_cd2_n_ipad"/><inputs id="cpu_data_iopads0PIN_SPECSIG"/><inputs id="cpu_rnw_ipad"/><inputs id="cpu_pktsel_ipad"/><inputs id="cpu_pce2_n_ipad"/><inputs id="cpu_pce1_n_ipad"/><inputs id="cpu_data_iopads10PIN_SPECSIG"/><inputs id="cpu_data_iopads11PIN_SPECSIG"/><inputs id="cpu_data_iopads12PIN_SPECSIG"/><inputs id="cpu_data_iopads13PIN_SPECSIG"/><inputs id="cpu_data_iopads14PIN_SPECSIG"/><inputs id="cpu_data_iopads15PIN_SPECSIG"/><inputs id="cpu_data_iopads1PIN_SPECSIG"/><inputs id="cpu_data_iopads2PIN_SPECSIG"/><inputs id="cpu_data_iopads3PIN_SPECSIG"/><inputs id="cpu_data_iopads4PIN_SPECSIG"/><inputs id="cpu_data_iopads5PIN_SPECSIG"/><inputs id="cpu_data_iopads6PIN_SPECSIG"/><inputs id="cpu_data_iopads7PIN_SPECSIG"/><inputs id="cpu_data_iopads8PIN_SPECSIG"/><inputs id="cpu_data_iopads9PIN_SPECSIG"/><inputs id="cf_iois16_n_ipad"/><inputs id="cpu_pior_n_ipad"/><inputs id="cpu_piow_n_ipad"/><inputs id="cpu_poe_n_ipad"/><inputs id="cpu_preg_n_ipad"/><inputs id="cpu_pwe_n_ipad"/><inputs id="cf_rdy_bsy_ipad"/><inputs id="cpu_gpio_21_ipad"/><inputs id="cf_wait_n_ipad"/><inputs id="cpu_address_in_ipads11_SPECSIG"/><inputs id="cpu_address_in_ipads12_SPECSIG"/><inputs id="cpu_cs3_n_ipad"/><inputs id="cpu_cs4_n_ipad"/><inputs id="cpu_cs5_n_ipad"/><inputs id="cpu_uart_cs_n_ipad"/><inputs id="cf_data_iopads0PIN_SPECSIG"/><inputs id="uart_data_iopads0PIN_SPECSIG"/><inputs id="cf_data_iopads10PIN_SPECSIG"/><inputs id="cf_data_iopads11PIN_SPECSIG"/><inputs id="cf_data_iopads12PIN_SPECSIG"/><inputs id="cf_data_iopads13PIN_SPECSIG"/><inputs id="cf_data_iopads14PIN_SPECSIG"/><inputs id="cf_data_iopads15PIN_SPECSIG"/><inputs id="cf_data_iopads1PIN_SPECSIG"/><inputs id="uart_data_iopads1PIN_SPECSIG"/><inputs id="cf_data_iopads2PIN_SPECSIG"/><inputs id="uart_data_iopads2PIN_SPECSIG"/><inputs id="cf_data_iopads3PIN_SPECSIG"/><inputs id="uart_data_iopads3PIN_SPECSIG"/><inputs id="cf_data_iopads4PIN_SPECSIG"/><inputs id="uart_data_iopads4PIN_SPECSIG"/><inputs id="cf_data_iopads5PIN_SPECSIG"/><inputs id="uart_data_iopads5PIN_SPECSIG"/><inputs id="cf_data_iopads6PIN_SPECSIG"/><inputs id="uart_data_iopads6PIN_SPECSIG"/><inputs id="cf_data_iopads7PIN_SPECSIG"/><inputs id="uart_data_iopads7PIN_SPECSIG"/><inputs id="cf_data_iopads8PIN_SPECSIG"/><inputs id="cf_data_iopads9PIN_SPECSIG"/><inputs id="cpu_dqm0_n_ipad"/><inputs id="cpu_dqm1_n_ipad"/><inputs id="ethernet_lanled_ipad"/><inputs id="uarts_0_thru_7_interrupt_ipad"/><inputs id="uarts_8_thru_15_interrupt_ipad"/><inputs id="spi_interrupt_ipad"/><inputs id="rtc_irq_n_ipad"/><inputs id="sr_ri_ipad"/><inputs id="lr_ri_ipad"/><inputs id="cpu_gpio_08_ipad"/><inputs id="cpu_gpio_09_ipad"/><inputs id="cpu_gpio_10_ipad"/><inputs id="cpu_gpio_11_ipad"/><inputs id="cpu_gpio_12_ipad"/><inputs id="cpu_gpio_13_ipad"/><inputs id="cpu_gpio_14_ipad"/><inputs id="cpu_gpio_15_ipad"/><inputs id="cpu_gpio_18_ipad"/><inputs id="ethernet_interrupt_ipad"/><inputs id="cpu_gpio_27_ipad"/><inputs id="cpu_khz32_ipad"/><inputs id="cpu_oe_n_ipad"/><inputs id="cpu_rclk_ipad"/><inputs id="cpu_reset_in_n_ipad"/><inputs id="cpu_we_n_ipad"/><inputs id="cts_n_00_ipad"/><inputs id="cts_n_01_ipad"/><inputs id="cts_n_02_ipad"/><inputs id="cts_n_03_ipad"/><inputs id="cts_n_04_ipad"/><inputs id="cts_n_05_ipad"/><inputs id="cts_n_06_ipad"/><inputs id="cts_n_07_ipad"/><inputs id="cts_n_08_ipad"/><inputs id="cts_n_09_ipad"/><inputs id="cts_n_10_ipad"/><inputs id="cts_n_11_ipad"/><inputs id="rtc_khz32_ipad"/><inputs id="power_on_reset_n_ipad"/><inputs id="spi_frame_n_ipad"/><inputs id="xPUP_0"/><global_inputs id="uart_osc_ipad" use="GCK"/><pin id="FB1_MC1_PINC14" use="IO_SPECSIG" slew="SLOW" pinnum="C14" signal="cpu_data_iopads2_SPECSIG"/><pin id="FB1_MC2_PIND13" use="IO_SPECSIG" slew="SLOW" pinnum="D13" signal="cpu_data_iopads3_SPECSIG"/><pin id="FB1_MC4_PINA15" use="IO_SPECSIG" slew="SLOW" pinnum="A15" signal="cpu_data_iopads4_SPECSIG"/><pin id="FB1_MC14_PINB15" use="IO_SPECSIG" slew="SLOW" pinnum="B15" signal="cpu_data_iopads5_SPECSIG"/><pin id="FB1_MC15_PINB14" use="IO_SPECSIG" slew="SLOW" pinnum="B14" signal="cpu_data_iopads6_SPECSIG"/><pin id="FB1_MC16_PINC13" use="IO_SPECSIG" slew="SLOW" pinnum="C13" signal="cpu_data_iopads7_SPECSIG"/><pin id="FB2_MC1_PINE12" use="IO_SPECSIG" slew="SLOW" pinnum="E12" signal="cpu_data_iopads9_SPECSIG"/><pin id="FB2_MC3_PINA16" use="IO_SPECSIG" slew="SLOW" pinnum="A16" signal="cpu_data_iopads1_SPECSIG"/><pin id="FB2_MC4_PINC15" use="O" slew="SLOW" pinnum="C15" signal="cf_address_opads3_SPECSIG"/><pin id="FB2_MC13_PINB16" use="O" slew="SLOW" pinnum="B16" signal="cf_address_opads2_SPECSIG"/><pin id="FB2_MC14_PIND14" use="O" slew="SLOW" pinnum="D14" signal="cf_address_opads1_SPECSIG"/><pin id="FB2_MC16_PIND15" use="O" slew="SLOW" pinnum="D15" signal="cf_address_opads10_SPECSIG"/><pin id="FB3_MC1_PINA14" use="O" slew="SLOW" pinnum="A14" signal="cf_reset_opad"/><pin id="FB3_MC2_PINE11" use="O" slew="SLOW" pinnum="E11" signal="cpu_gpio_17_opad"/><pin id="FB3_MC4_PINA13" use="O" slew="SLOW" pinnum="A13" signal="cpu_gpio_24_opad"/><pin id="FB3_MC13_PIND12" use="O" slew="SLOW" pinnum="D12" signal="cpu_gpio_25_opad"/><pin id="FB3_MC15_PINB13" use="O" slew="SLOW" pinnum="B13" signal="cpu_gpio_02_opad"/><pin id="FB3_MC16_PINC12" use="O" slew="SLOW" pinnum="C12" signal="cpu_gpio_03_opad"/><pin id="FB4_MC1_PINE13" use="O" slew="SLOW" pinnum="E13" signal="cf_address_opads0_SPECSIG"/><pin id="FB4_MC3_PINC16" use="O" slew="SLOW" pinnum="C16" signal="cpu_gpio_23_opad"/><pin id="FB4_MC4_PINF12" use="O" slew="SLOW" pinnum="F12" signal="cf_pce2_n_opad"/><pin id="FB4_MC14_PIND16" use="O" slew="SLOW" pinnum="D16" signal="cf_pce1_n_opad"/><pin id="FB4_MC15_PINE14" use="O" slew="SLOW" pinnum="E14" signal="cf_csel_n_opad"/><pin id="FB4_MC16_PINE15" use="O" slew="SLOW" pinnum="E15" signal="dummy_signal_opad"/><pin id="FB5_MC1_PINA12" use="O" slew="SLOW" pinnum="A12" signal="cpu_gpio_19_opad"/><pin id="FB5_MC3_PIND11" use="O" slew="SLOW" pinnum="D11" signal="cpu_gpio_20_opad"/><pin id="FB5_MC13_PINA11" use="O" slew="SLOW" pinnum="A11" signal="cpu_gpio_22_opad"/><pin id="FB5_MC14_PINE10" use="I" pinnum="E10" signal="cpu_gpio_10_ipad"/><pin id="FB5_MC15_PINB12" use="I" pinnum="B12" signal="cpu_gpio_09_ipad"/><pin id="FB5_MC16_PINC11" use="I" pinnum="C11" signal="cpu_gpio_08_ipad"/><pin id="FB6_MC1_PINF13" use="O" slew="SLOW" pinnum="F13" signal="uart_address_opads0_SPECSIG"/><pin id="FB6_MC3_PINE16" use="IO_SPECSIG" slew="SLOW" pinnum="E16" signal="cf_data_iopads0_SPECSIG"/><pin id="FB6_MC13_PINF15" use="IO_SPECSIG" slew="SLOW" pinnum="F15" signal="cf_data_iopads11_SPECSIG"/><pin id="FB6_MC14_PING12" use="IO_SPECSIG" slew="SLOW" pinnum="G12" signal="cf_data_iopads12_SPECSIG"/><pin id="FB6_MC15_PINF14" use="IO_SPECSIG" slew="SLOW" pinnum="F14" signal="cf_data_iopads10_SPECSIG"/><pin id="FB6_MC16_PING15" use="IO_SPECSIG" slew="SLOW" pinnum="G15" signal="cf_data_iopads13_SPECSIG"/><pin id="FB7_MC1_PINB11" use="O" slew="SLOW" pinnum="B11" signal="cpu_gpio_07_opad"/><pin id="FB7_MC2_PIND10" use="O" slew="SLOW" pinnum="D10" signal="cpu_gpio_01_opad"/><pin id="FB7_MC3_PINA10" use="O" slew="SLOW" pinnum="A10" signal="cpu_gpio_00_opad"/><pin id="FB7_MC4_PINC10" pinnum="C10"/><pin id="FB7_MC15_PINA9" use="O" slew="SLOW" pinnum="A9" signal="cpu_ready_opad"/><pin id="FB7_MC16_PIND9" use="O" slew="SLOW" pinnum="D9" signal="uart_address_opads4_SPECSIG"/><pin id="FB8_MC1_PING13" use="IO_SPECSIG" slew="SLOW" pinnum="G13" signal="cf_data_iopads14_SPECSIG"/><pin id="FB8_MC3_PINF16" use="IO_SPECSIG" slew="SLOW" pinnum="F16" signal="cf_data_iopads15_SPECSIG"/><pin id="FB8_MC13_PING14" use="IO_SPECSIG" slew="SLOW" pinnum="G14" signal="cpu_data_iopads0_SPECSIG"/><pin id="FB8_MC14_PING16" use="IO_SPECSIG" slew="SLOW" pinnum="G16" signal="cpu_data_iopads10_SPECSIG"/><pin id="FB8_MC15_PINH13" use="IO_SPECSIG" slew="SLOW" pinnum="H13" signal="cpu_data_iopads11_SPECSIG"/><pin id="FB8_MC16_PINH12" use="IO_SPECSIG" slew="SLOW" pinnum="H12" signal="cpu_data_iopads12_SPECSIG"/><pin id="FB9_MC1_PINP16" use="O" slew="SLOW" pinnum="P16" signal="uart_address_opads6_SPECSIG"/><pin id="FB9_MC2_PINN14" use="IO_SPECSIG" slew="SLOW" pinnum="N14" signal="cf_data_iopads7_SPECSIG"/><pin id="FB9_MC3_PINR16" use="O" slew="SLOW" pinnum="R16" signal="uart_address_opads7_SPECSIG"/><pin id="FB9_MC13_PINM13" use="IO_SPECSIG" slew="SLOW" pinnum="M13" signal="cf_data_iopads8_SPECSIG"/><pin id="FB9_MC14_PINP15" use="IO_SPECSIG" slew="SLOW" pinnum="P15" signal="cf_data_iopads9_SPECSIG"/><pin id="FB9_MC15_PINL12" use="IO_SPECSIG" slew="SLOW" pinnum="L12" signal="cf_data_iopads4_SPECSIG"/><pin id="FB9_MC16_PINN16" use="O" slew="SLOW" pinnum="N16" signal="uart_address_opads3_SPECSIG"/><pin id="FB10_MC1_PINN13" use="IO_SPECSIG" slew="SLOW" pinnum="N13" signal="cf_data_iopads6_SPECSIG"/><pin id="FB10_MC2_PINR15" use="O" slew="SLOW" pinnum="R15" signal="uart_address_opads5_SPECSIG"/><pin id="FB10_MC3_PINM12" use="IO_SPECSIG" slew="SLOW" pinnum="M12" signal="cf_data_iopads5_SPECSIG"/><pin id="FB10_MC13_PINT16" use="O" slew="SLOW" pinnum="T16" signal="cf_poe_n_opad"/><pin id="FB10_MC14_PINP14" use="O" slew="SLOW" pinnum="P14" signal="cf_piow_n_opad"/><pin id="FB10_MC15_PINT15" use="O" slew="SLOW" pinnum="T15" signal="cf_pior_n_opad"/><pin id="FB10_MC16_PINP13" use="O" slew="SLOW" pinnum="P13" signal="cf_address_opads9_SPECSIG"/><pin id="FB11_MC1_PINM14" use="IO_SPECSIG" slew="SLOW" pinnum="M14" signal="cf_data_iopads3_SPECSIG"/><pin id="FB11_MC2_PINM16" use="IO_SPECSIG" slew="SLOW" pinnum="M16" signal="cf_data_iopads2_SPECSIG"/><pin id="FB11_MC3_PINL13" use="O" slew="SLOW" pinnum="L13" signal="uart_address_opads2_SPECSIG"/><pin id="FB11_MC4_PINN15" use="O" slew="SLOW" pinnum="N15" signal="cpu_pwait_n_opad"/><pin id="FB11_MC14_PINM15" use="O" slew="SLOW" pinnum="M15" signal="cpu_iois16_n_opad"/><pin id="FB11_MC15_PINL16" use="O" slew="SLOW" pinnum="L16" signal="cf_pwe_n_opad"/><pin id="FB11_MC16_PINK12" use="O" slew="SLOW" pinnum="K12" signal="cf_preg_n_opad"/><pin id="FB12_MC1_PINR14" use="O" slew="SLOW" pinnum="R14" signal="cf_address_opads8_SPECSIG"/><pin id="FB12_MC2_PINN12" use="O" slew="SLOW" pinnum="N12" signal="cf_address_opads7_SPECSIG"/><pin id="FB12_MC3_PINT14" use="O" slew="SLOW" pinnum="T14" signal="cf_address_opads6_SPECSIG"/><pin id="FB12_MC13_PINM11" use="O" slew="SLOW" pinnum="M11" signal="cf_address_opads5_SPECSIG"/><pin id="FB12_MC14_PINR13" use="O" slew="SLOW" pinnum="R13" signal="cf_address_opads4_SPECSIG"/><pin id="FB12_MC15_PINP12" use="O" slew="SLOW" pinnum="P12" signal="spi_cs_7_n_opad"/><pin id="FB12_MC16_PINT13" use="O" slew="SLOW" pinnum="T13" signal="sr_power_on_opad"/><pin id="FB13_MC1_PINL15" use="IO_SPECSIG" slew="SLOW" pinnum="L15" signal="cf_data_iopads1_SPECSIG"/><pin id="FB13_MC3_PINK13" use="O" slew="SLOW" pinnum="K13" signal="uart_address_opads1_SPECSIG"/><pin id="FB13_MC4_PINK16" use="O" slew="SLOW" pinnum="K16" signal="spi_cs_5_n_opad"/><pin id="FB13_MC13_PINK14" use="O" slew="SLOW" pinnum="K14" signal="spi_cs_4_n_opad"/><pin id="FB13_MC14_PINK15" use="O" slew="SLOW" pinnum="K15" signal="spi_cs_3_n_opad"/><pin id="FB13_MC15_PINL14" use="O" slew="SLOW" pinnum="L14" signal="spi_cs_2_n_opad"/><pin id="FB13_MC16_PINJ16" use="O" slew="SLOW" pinnum="J16" signal="spi_cs_1_n_opad"/><pin id="FB14_MC1_PINN11" use="O" slew="SLOW" pinnum="N11" signal="spi_cs_6_n_opad"/><pin id="FB14_MC2_PINR12" use="I" pinnum="R12" signal="spi_interrupt_ipad"/><pin id="FB14_MC3_PINT12" use="O" slew="SLOW" pinnum="T12" signal="uplink_tx_enable_opad"/><pin id="FB14_MC4_PINR11" use="I" pinnum="R11" signal="ethernet_lanled_ipad"/><pin id="FB14_MC13_PINM10" use="O" slew="SLOW" pinnum="M10" signal="uplink_rx_enable_n_opad"/><pin id="FB14_MC14_PINP11" use="I" pinnum="P11" signal="power_on_reset_n_ipad"/><pin id="FB14_MC16_PINN10" use="I" pinnum="N10" signal="lr_ri_ipad"/><pin id="FB15_MC1_PINJ13" pinnum="J13"/><pin id="FB15_MC2_PINJ15" use="O" slew="SLOW" pinnum="J15" signal="spi_cs_0_n_opad"/><pin id="FB15_MC3_PINJ14" use="IO_SPECSIG" slew="SLOW" pinnum="J14" signal="cpu_data_iopads8_SPECSIG"/><pin id="FB15_MC13_PINH16" use="IO_SPECSIG" slew="SLOW" pinnum="H16" signal="cpu_data_iopads15_SPECSIG"/><pin id="FB15_MC15_PINH14" use="IO_SPECSIG" slew="SLOW" pinnum="H14" signal="cpu_data_iopads14_SPECSIG"/><pin id="FB15_MC16_PINH15" use="IO_SPECSIG" slew="SLOW" pinnum="H15" signal="cpu_data_iopads13_SPECSIG"/><pin id="FB16_MC1_PINT11" use="O" slew="SLOW" pinnum="T11" signal="uart_cs0_n_opad"/><pin id="FB16_MC2_PINR10" use="O" slew="SLOW" pinnum="R10" signal="uart_cs1_n_opad"/><pin id="FB16_MC3_PINP10" use="O" slew="SLOW" pinnum="P10" signal="uart_rd_n_opad"/><pin id="FB16_MC4_PINT10" use="O" slew="SLOW" pinnum="T10" signal="uart_wr_n_opad"/><pin id="FB16_MC14_PINN9" use="I" pinnum="N9" signal="cpu_address_in_ipads8_SPECSIG"/><pin id="FB16_MC15_PINR9" use="I" pinnum="R9" signal="cpu_oe_n_ipad"/><pin id="FB16_MC16_PINP9" use="I" pinnum="P9" signal="cpu_we_n_ipad"/><pin id="FB17_MC1_PINB1" use="I" pinnum="B1" signal="cpu_address_in_ipads6_SPECSIG"/><pin id="FB17_MC2_PINB2" use="I" pinnum="B2" signal="cpu_address_in_ipads7_SPECSIG"/><pin id="FB17_MC3_PINC3" use="I" pinnum="C3" signal="cpu_gpio_18_ipad"/><pin id="FB17_MC13_PIND4" use="I" pinnum="D4" signal="cpu_gpio_21_ipad"/><pin id="FB17_MC14_PINA2" use="I" pinnum="A2" signal="cpu_gpio_27_ipad"/><pin id="FB17_MC15_PINA1" use="I" pinnum="A1" signal="cpu_pce1_n_ipad"/><pin id="FB17_MC16_PINB3" use="I" pinnum="B3" signal="cpu_pce2_n_ipad"/><pin id="FB18_MC1_PINC1" use="I" pinnum="C1" signal="cpu_address_in_ipads5_SPECSIG"/><pin id="FB18_MC2_PIND3" use="I" pinnum="D3" signal="cpu_address_in_ipads4_SPECSIG"/><pin id="FB18_MC3_PINC2" use="I" pinnum="C2" signal="cpu_address_in_ipads3_SPECSIG"/><pin id="FB18_MC4_PINF5" use="I" pinnum="F5" signal="cpu_address_in_ipads2_SPECSIG"/><pin id="FB18_MC14_PIND1" use="I" pinnum="D1" signal="cpu_address_in_ipads1_SPECSIG"/><pin id="FB18_MC16_PINE4" use="I" pinnum="E4" signal="cpu_address_in_ipads12_SPECSIG"/><pin id="FB19_MC1_PINC4" use="I" pinnum="C4" signal="cpu_pior_n_ipad"/><pin id="FB19_MC3_PINA3" use="I" pinnum="A3" signal="cpu_piow_n_ipad"/><pin id="FB19_MC4_PIND5" use="I" pinnum="D5" signal="cpu_pktsel_ipad"/><pin id="FB19_MC13_PINB4" use="I" pinnum="B4" signal="cpu_poe_n_ipad"/><pin id="FB19_MC14_PINE6" use="O" slew="SLOW" pinnum="E6" signal="cpu_gpio_26_opad"/><pin id="FB19_MC15_PINA4" use="O" slew="SLOW" pinnum="A4" signal="reset_out_n_opad"/><pin id="FB19_MC16_PINC5" use="O" slew="SLOW" pinnum="C5" signal="ethernet_sleep_n_opad"/><pin id="FB20_MC1_PIND2" use="I" pinnum="D2" signal="cpu_address_in_ipads9_SPECSIG"/><pin id="FB20_MC2_PINE3" use="I" pinnum="E3" signal="cpu_cs3_n_ipad"/><pin id="FB20_MC4_PINE1" use="I" pinnum="E1" signal="cpu_cs4_n_ipad"/><pin id="FB20_MC14_PINF4" use="I" pinnum="F4" signal="cpu_cs5_n_ipad"/><pin id="FB20_MC15_PINF1" use="I" pinnum="F1" signal="cpu_dqm0_n_ipad"/><pin id="FB20_MC16_PING5" use="I" pinnum="G5" signal="cpu_dqm1_n_ipad"/><pin id="FB21_MC1_PINB5" use="I" pinnum="B5" signal="cts_n_04_ipad"/><pin id="FB21_MC2_PIND6" use="I" pinnum="D6" signal="cts_n_03_ipad"/><pin id="FB21_MC3_PINA5" use="I" pinnum="A5" signal="cts_n_02_ipad"/><pin id="FB21_MC13_PINC6" use="I" pinnum="C6" signal="cts_n_01_ipad"/><pin id="FB21_MC14_PINB6" use="I" pinnum="B6" signal="cts_n_00_ipad"/><pin id="FB21_MC15_PINE7" use="I" pinnum="E7" signal="sr_ri_ipad"/><pin id="FB21_MC16_PINA6" use="O" slew="SLOW" pinnum="A6" signal="cpu_gpio_16_opad"/><pin id="FB22_MC1_PINE2" use="O" slew="SLOW" pinnum="E2" signal="cpu_gpio_04_opad"/><pin id="FB22_MC2_PINF3" use="O" slew="SLOW" pinnum="F3" signal="cpu_gpio_05_opad"/><pin id="FB22_MC4_PINF2" use="O" slew="SLOW" pinnum="F2" signal="cpu_gpio_06_opad"/><pin id="FB22_MC14_PING4" use="I" pinnum="G4" signal="cpu_preg_n_ipad"/><pin id="FB22_MC15_PING1" use="I" pinnum="G1" signal="cpu_pwe_n_ipad"/><pin id="FB22_MC16_PING3" use="I" pinnum="G3" signal="cpu_reset_in_n_ipad"/><pin id="FB23_MC1_PIND7" use="I" pinnum="D7" signal="cpu_gpio_15_ipad"/><pin id="FB23_MC2_PINB7" use="I" pinnum="B7" signal="cpu_gpio_14_ipad"/><pin id="FB23_MC3_PINC7" use="I" pinnum="C7" signal="cpu_gpio_13_ipad"/><pin id="FB23_MC4_PINC8" use="I" pinnum="C8" signal="cpu_gpio_12_ipad"/><pin id="FB23_MC14_PINA7" pinnum="A7"/><pin id="FB23_MC15_PIND8" use="I" pinnum="D8" signal="cpu_gpio_11_ipad"/><pin id="FB23_MC16_PINB8" use="O" slew="SLOW" pinnum="B8" signal="cf_power_on_opad"/><pin id="FB24_MC1_PINH1" use="I" pinnum="H1" signal="cpu_rnw_ipad"/><pin id="FB24_MC2_PINH4" use="I" pinnum="H4" signal="cpu_uart_cs_n_ipad"/><pin id="FB24_MC3_PING2" use="I" pinnum="G2" signal="ethernet_interrupt_ipad"/><pin id="FB24_MC4_PINH3" use="O" slew="SLOW" pinnum="H3" signal="net_reset_opad"/><pin id="FB24_MC13_PINJ1" use="I" pinnum="J1" signal="cts_n_11_ipad"/><pin id="FB24_MC16_PINJ3" use="I" pinnum="J3" signal="cts_n_10_ipad"/><pin id="FB25_MC1_PINP2" use="O" slew="SLOW" pinnum="P2" signal="test_opads13_SPECSIG"/><pin id="FB25_MC2_PINP3" use="O" slew="SLOW" pinnum="P3" signal="test_opads14_SPECSIG"/><pin id="FB25_MC4_PINT1" use="I" pinnum="T1" signal="attention_arm_ipad"/><pin id="FB25_MC14_PINN3" use="O" slew="SLOW" pinnum="N3" signal="test_opads11_SPECSIG"/><pin id="FB25_MC15_PINR1" use="O" slew="SLOW" pinnum="R1" signal="test_opads15_SPECSIG"/><pin id="FB25_MC16_PINM4" use="O" slew="SLOW" pinnum="M4" signal="test_opads9_SPECSIG"/><pin id="FB26_MC1_PINM5" use="I" pinnum="M5" signal="uarts_8_thru_15_interrupt_ipad"/><pin id="FB26_MC2_PINN4" use="O" slew="SLOW" pinnum="N4" signal="uart_reset_n_opad"/><pin id="FB26_MC3_PINR2" pinnum="R2"/><pin id="FB26_MC4_PINT2" use="I" pinnum="T2" signal="spi_frame_n_ipad"/><pin id="FB26_MC13_PINP4" use="I" pinnum="P4" signal="cts_n_05_ipad"/><pin id="FB26_MC15_PINR3" use="I" pinnum="R3" signal="cts_n_06_ipad"/><pin id="FB26_MC16_PINN5" use="I" pinnum="N5" signal="cts_n_07_ipad"/><pin id="FB27_MC1_PINP1" use="O" slew="SLOW" pinnum="P1" signal="test_opads12_SPECSIG"/><pin id="FB27_MC3_PINL5" use="O" slew="SLOW" pinnum="L5" signal="test_opads5_SPECSIG"/><pin id="FB27_MC4_PINN2" use="O" slew="SLOW" pinnum="N2" signal="test_opads10_SPECSIG"/><pin id="FB27_MC14_PINM3" use="O" slew="SLOW" pinnum="M3" signal="test_opads8_SPECSIG"/><pin id="FB27_MC15_PINL4" use="O" slew="SLOW" pinnum="L4" signal="test_opads4_SPECSIG"/><pin id="FB27_MC16_PINM2" use="O" slew="SLOW" pinnum="M2" signal="test_opads7_SPECSIG"/><pin id="FB28_MC1_PINT3" use="I" pinnum="T3" signal="cts_n_08_ipad"/><pin id="FB28_MC2_PINM6" use="I" pinnum="M6" signal="cts_n_09_ipad"/><pin id="FB28_MC3_PINR4" use="IO_SPECSIG" slew="SLOW" pinnum="R4" signal="uart_data_iopads7_SPECSIG"/><pin id="FB28_MC4_PINP5" use="IO_SPECSIG" slew="SLOW" pinnum="P5" signal="uart_data_iopads6_SPECSIG"/><pin id="FB28_MC14_PINT4" use="IO_SPECSIG" slew="SLOW" pinnum="T4" signal="uart_data_iopads5_SPECSIG"/><pin id="FB28_MC15_PINN6" use="IO_SPECSIG" slew="SLOW" pinnum="N6" signal="uart_data_iopads4_SPECSIG"/><pin id="FB28_MC16_PINR5" use="IO_SPECSIG" slew="SLOW" pinnum="R5" signal="uart_data_iopads3_SPECSIG"/><pin id="FB29_MC1_PINL2" use="O" slew="SLOW" pinnum="L2" signal="test_opads2_SPECSIG"/><pin id="FB29_MC3_PINM1" use="O" slew="SLOW" pinnum="M1" signal="test_opads6_SPECSIG"/><pin id="FB29_MC4_PINK5" use="O" slew="SLOW" pinnum="K5" signal="test_opads1_SPECSIG"/><pin id="FB29_MC13_PINL3" use="O" slew="SLOW" pinnum="L3" signal="test_opads3_SPECSIG"/><pin id="FB29_MC14_PINK4" use="O" slew="SLOW" pinnum="K4" signal="test_opads0_SPECSIG"/><pin id="FB29_MC16_PINL1" use="I" pinnum="L1" signal="uarts_0_thru_7_interrupt_ipad"/><pin id="FB30_MC1_PINT6" use="IO_SPECSIG" slew="SLOW" pinnum="T6" signal="uart_data_iopads2_SPECSIG"/><pin id="FB30_MC2_PINT5" use="IO_SPECSIG" slew="SLOW" pinnum="T5" signal="uart_data_iopads1_SPECSIG"/><pin id="FB30_MC3_PINM7" use="IO_SPECSIG" slew="SLOW" pinnum="M7" signal="uart_data_iopads0_SPECSIG"/><pin id="FB30_MC13_PINR6" use="O" slew="SLOW" pinnum="R6" signal="lr_power_on_opad"/><pin id="FB30_MC14_PINN7" use="I" pinnum="N7" signal="cf_bvd_2_ipad"/><pin id="FB30_MC15_PINT7" use="I" pinnum="T7" signal="cf_cd1_n_ipad"/><pin id="FB30_MC16_PINP6" use="I" pinnum="P6" signal="cf_cd2_n_ipad"/><pin id="FB31_MC1_PINK2" use="O" slew="SLOW" pinnum="K2" signal="uart_clock_opad"/><pin id="FB31_MC2_PINK3" pinnum="K3"/><pin id="FB31_MC3_PINK1" pinnum="K1"/><pin id="FB31_MC4_PINJ4" pinnum="J4"/><pin id="FB31_MC14_PINJ2" pinnum="J2"/><pin id="FB31_MC15_PINJ5" use="I" pinnum="J5" signal="rtc_irq_n_ipad"/><pin id="FB31_MC16_PINH2" pinnum="H2"/><pin id="FB32_MC1_PINR7" use="I" pinnum="R7" signal="cf_iois16_n_ipad"/><pin id="FB32_MC2_PINP7" use="I" pinnum="P7" signal="cf_rdy_bsy_ipad"/><pin id="FB32_MC3_PINT8" use="I" pinnum="T8" signal="cf_wait_n_ipad"/><pin id="FB32_MC4_PINN8" use="I" pinnum="N8" signal="cpu_address_in_ipads0_SPECSIG"/><pin id="FB32_MC14_PINR8" use="I" pinnum="R8" signal="cpu_address_in_ipads10_SPECSIG"/><pin id="FB32_MC15_PINP8" use="I" pinnum="P8" signal="cpu_address_in_ipads11_SPECSIG"/><pin id="FB32_MC16_PINT9" use="I" pinnum="T9" signal="cf_bvd_1_ipad"/><pin id="GLOBAL_PIN4" use="GCK" pinnum="B10" signal="uart_osc_ipad"/><pin id="NOFB_NOMC_PINC9" use="I" pinnum="C9" signal="rtc_khz32_ipad"/><pin id="NOFB_NOMC_PINA8" use="I" pinnum="A8" signal="cpu_rclk_ipad"/><pin id="NOFB_NOMC_PINB9" use="I" pinnum="B9" signal="cpu_khz32_ipad"/><uct id="UCT2" bct="FB1_bct7"/><fblock id="FB1" pinUse="6"><macrocell id="FB1_MC1" pin="FB1_MC1_PINC14" sigUse="4" signal="cpu_data_iopads2_SPECSIG"><eq_pterm ptindx="FB1_0"/><eq_pterm ptindx="FB1_1"/></macrocell><macrocell id="FB1_MC2" pin="FB1_MC2_PIND13" sigUse="4" signal="cpu_data_iopads3_SPECSIG"><eq_pterm ptindx="FB1_2"/><eq_pterm ptindx="FB1_3"/></macrocell><macrocell id="FB1_MC3"/><macrocell id="FB1_MC4" pin="FB1_MC4_PINA15" sigUse="4" signal="cpu_data_iopads4_SPECSIG"><eq_pterm ptindx="FB1_4"/><eq_pterm ptindx="FB1_5"/></macrocell><macrocell id="FB1_MC5"/><macrocell id="FB1_MC6"/><macrocell id="FB1_MC7"/><macrocell id="FB1_MC8"/><macrocell id="FB1_MC9"/><macrocell id="FB1_MC10"/><macrocell id="FB1_MC11"/><macrocell id="FB1_MC12" sigUse="4" signal="_n0003"><eq_pterm ptindx="FB1_15"/><eq_pterm ptindx="FB1_16"/></macrocell><macrocell id="FB1_MC13" sigUse="3" signal="N_PZ_169"><eq_pterm ptindx="FB1_14"/><eq_pterm ptindx="FB1_13"/></macrocell><macrocell id="FB1_MC14" pin="FB1_MC14_PINB15" sigUse="4" signal="cpu_data_iopads5_SPECSIG"><eq_pterm ptindx="FB1_6"/><eq_pterm ptindx="FB1_8"/></macrocell><macrocell id="FB1_MC15" pin="FB1_MC15_PINB14" sigUse="4" signal="cpu_data_iopads6_SPECSIG"><eq_pterm ptindx="FB1_9"/><eq_pterm ptindx="FB1_10"/></macrocell><macrocell id="FB1_MC16" pin="FB1_MC16_PINC13" sigUse="4" signal="cpu_data_iopads7_SPECSIG"><eq_pterm ptindx="FB1_11"/><eq_pterm ptindx="FB1_12"/></macrocell><fbinput id="FB1_I1" signal="N_PZ_169"/><fbinput id="FB1_I2" signal="_n0003"/><fbinput id="FB1_I3" fbk="PIN" signal="cf_data_iopads2PIN_SPECSIG"/><fbinput id="FB1_I4" fbk="PIN" signal="cf_data_iopads3PIN_SPECSIG"/><fbinput id="FB1_I5" fbk="PIN" signal="cf_data_iopads4PIN_SPECSIG"/><fbinput id="FB1_I6" fbk="PIN" signal="cf_data_iopads5PIN_SPECSIG"/><fbinput id="FB1_I7" fbk="PIN" signal="cf_data_iopads6PIN_SPECSIG"/><fbinput id="FB1_I8" fbk="PIN" signal="cf_data_iopads7PIN_SPECSIG"/><fbinput id="FB1_I9" signal="cpu_pce1_n_ipad"/><fbinput id="FB1_I10" signal="cpu_pce2_n_ipad"/><fbinput id="FB1_I11" signal="cpu_pktsel_ipad"/><fbinput id="FB1_I12" signal="cpu_rnw_ipad"/><fbinput id="FB1_I13" signal="cpu_uart_cs_n_ipad"/><fbinput id="FB1_I14" fbk="PIN" signal="uart_data_iopads2PIN_SPECSIG"/><fbinput id="FB1_I15" fbk="PIN" signal="uart_data_iopads3PIN_SPECSIG"/><fbinput id="FB1_I16" fbk="PIN" signal="uart_data_iopads4PIN_SPECSIG"/><fbinput id="FB1_I17" fbk="PIN" signal="uart_data_iopads5PIN_SPECSIG"/><fbinput id="FB1_I18" fbk="PIN" signal="uart_data_iopads6PIN_SPECSIG"/><fbinput id="FB1_I19" fbk="PIN" signal="uart_data_iopads7PIN_SPECSIG"/><PAL><pterm id="FB1_0"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads2PIN_SPECSIG"/></pterm><pterm id="FB1_1"><signal id="cpu_uart_cs_n_ipad" negated="ON"/><signal id="uart_data_iopads2PIN_SPECSIG"/></pterm><pterm id="FB1_2"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads3PIN_SPECSIG"/></pterm><pterm id="FB1_3"><signal id="cpu_uart_cs_n_ipad" negated="ON"/><signal id="uart_data_iopads3PIN_SPECSIG"/></pterm><pterm id="FB1_4"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads4PIN_SPECSIG"/></pterm><pterm id="FB1_5"><signal id="cpu_uart_cs_n_ipad" negated="ON"/><signal id="uart_data_iopads4PIN_SPECSIG"/></pterm><pterm id="FB1_6"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads5PIN_SPECSIG"/></pterm><pterm id="FB1_7"><signal id="N_PZ_169"/></pterm><pterm id="FB1_8"><signal id="cpu_uart_cs_n_ipad" negated="ON"/><signal id="uart_data_iopads5PIN_SPECSIG"/></pterm><pterm id="FB1_9"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads6PIN_SPECSIG"/></pterm><pterm id="FB1_10"><signal id="cpu_uart_cs_n_ipad" negated="ON"/><signal id="uart_data_iopads6PIN_SPECSIG"/></pterm><pterm id="FB1_11"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads7PIN_SPECSIG"/></pterm><pterm id="FB1_12"><signal id="cpu_uart_cs_n_ipad" negated="ON"/><signal id="uart_data_iopads7PIN_SPECSIG"/></pterm><pterm id="FB1_13"><signal id="cpu_rnw_ipad"/><signal id="cpu_uart_cs_n_ipad" negated="ON"/></pterm><pterm id="FB1_14"><signal id="_n0003"/></pterm><pterm id="FB1_15"><signal id="cpu_rnw_ipad"/><signal id="cpu_pktsel_ipad"/><signal id="cpu_pce2_n_ipad" negated="ON"/></pterm><pterm id="FB1_16"><signal id="cpu_rnw_ipad"/><signal id="cpu_pktsel_ipad"/><signal id="cpu_pce1_n_ipad" negated="ON"/></pterm></PAL><bct id="FB1_bct7"><eq_pterm ptindx="FB1_7"/></bct><equation id="cpu_data_iopads2_SPECSIG"><d2><eq_pterm ptindx="FB1_0"/><eq_pterm ptindx="FB1_1"/></d2><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads3_SPECSIG"><d2><eq_pterm ptindx="FB1_2"/><eq_pterm ptindx="FB1_3"/></d2><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads4_SPECSIG"><d2><eq_pterm ptindx="FB1_4"/><eq_pterm ptindx="FB1_5"/></d2><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="_n0003"><d2><eq_pterm ptindx="FB1_15"/><eq_pterm ptindx="FB1_16"/></d2></equation><equation id="N_PZ_169"><d2><eq_pterm ptindx="FB1_14"/><eq_pterm ptindx="FB1_13"/></d2></equation><equation id="cpu_data_iopads5_SPECSIG"><d2><eq_pterm ptindx="FB1_6"/><eq_pterm ptindx="FB1_8"/></d2><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads6_SPECSIG"><d2><eq_pterm ptindx="FB1_9"/><eq_pterm ptindx="FB1_10"/></d2><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads7_SPECSIG"><d2><eq_pterm ptindx="FB1_11"/><eq_pterm ptindx="FB1_12"/></d2><oe><eq_pterm ptindx="FB1_7"/></oe></equation></fblock><fblock id="FB2" pinUse="6"><macrocell id="FB2_MC1" pin="FB2_MC1_PINE12" sigUse="2" signal="cpu_data_iopads9_SPECSIG"><eq_pterm ptindx="FB2_8"/></macrocell><macrocell id="FB2_MC2"/><macrocell id="FB2_MC3" pin="FB2_MC3_PINA16" sigUse="3" signal="cpu_data_iopads1_SPECSIG"><eq_pterm ptindx="FB2_0"/><eq_pterm ptindx="FB2_1"/></macrocell><macrocell id="FB2_MC4" pin="FB2_MC4_PINC15" sigUse="1" signal="cf_address_opads3_SPECSIG"><eq_pterm ptindx="FB2_14"/></macrocell><macrocell id="FB2_MC5"/><macrocell id="FB2_MC6"/><macrocell id="FB2_MC7"/><macrocell id="FB2_MC8"/><macrocell id="FB2_MC9"/><macrocell id="FB2_MC10"/><macrocell id="FB2_MC11"/><macrocell id="FB2_MC12"/><macrocell id="FB2_MC13" pin="FB2_MC13_PINB16" sigUse="1" signal="cf_address_opads2_SPECSIG"><eq_pterm ptindx="FB2_32"/></macrocell><macrocell id="FB2_MC14" pin="FB2_MC14_PIND14" sigUse="1" signal="cf_address_opads1_SPECSIG"><eq_pterm ptindx="FB2_34"/></macrocell><macrocell id="FB2_MC15"/><macrocell id="FB2_MC16" pin="FB2_MC16_PIND15" sigUse="1" signal="cf_address_opads10_SPECSIG"><eq_pterm ptindx="FB2_38"/></macrocell><fbinput id="FB2_I1" fbk="PIN" signal="cf_data_iopads1PIN_SPECSIG"/><fbinput id="FB2_I2" fbk="PIN" signal="cf_data_iopads9PIN_SPECSIG"/><fbinput id="FB2_I3" signal="cpu_address_in_ipads10_SPECSIG"/><fbinput id="FB2_I4" signal="cpu_address_in_ipads1_SPECSIG"/><fbinput id="FB2_I5" signal="cpu_address_in_ipads2_SPECSIG"/><fbinput id="FB2_I6" signal="cpu_address_in_ipads3_SPECSIG"/><fbinput id="FB2_I7" signal="cpu_uart_cs_n_ipad"/><fbinput id="FB2_I8" fbk="PIN" signal="uart_data_iopads1PIN_SPECSIG"/><PAL><pterm id="FB2_0"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads1PIN_SPECSIG"/></pterm><pterm id="FB2_1"><signal id="cpu_uart_cs_n_ipad" negated="ON"/><signal id="uart_data_iopads1PIN_SPECSIG"/></pterm><pterm id="FB2_8"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads9PIN_SPECSIG"/></pterm><pterm id="FB2_14"><signal id="cpu_address_in_ipads3_SPECSIG"/></pterm><pterm id="FB2_32"><signal id="cpu_address_in_ipads2_SPECSIG"/></pterm><pterm id="FB2_34"><signal id="cpu_address_in_ipads1_SPECSIG"/></pterm><pterm id="FB2_38"><signal id="cpu_address_in_ipads10_SPECSIG"/></pterm></PAL><equation id="cpu_data_iopads9_SPECSIG"><d1><eq_pterm ptindx="FB2_8"/></d1><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads1_SPECSIG"><d2><eq_pterm ptindx="FB2_0"/><eq_pterm ptindx="FB2_1"/></d2><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cf_address_opads3_SPECSIG"><d1><eq_pterm ptindx="FB2_14"/></d1></equation><equation id="cf_address_opads2_SPECSIG"><d1><eq_pterm ptindx="FB2_32"/></d1></equation><equation id="cf_address_opads1_SPECSIG"><d1><eq_pterm ptindx="FB2_34"/></d1></equation><equation id="cf_address_opads10_SPECSIG"><d1><eq_pterm ptindx="FB2_38"/></d1></equation></fblock><fblock id="FB3" pinUse="6"><macrocell id="FB3_MC1" pin="FB3_MC1_PINA14" sigUse="1" signal="cf_reset_opad"><eq_pterm ptindx="FB3_8"/></macrocell><macrocell id="FB3_MC2" pin="FB3_MC2_PINE11" sigUse="0" signal="cpu_gpio_17_opad"/><macrocell id="FB3_MC3"/><macrocell id="FB3_MC4" pin="FB3_MC4_PINA13" sigUse="0" signal="cpu_gpio_24_opad"/><macrocell id="FB3_MC5"/><macrocell id="FB3_MC6"/><macrocell id="FB3_MC7"/><macrocell id="FB3_MC8"/><macrocell id="FB3_MC9"/><macrocell id="FB3_MC10"/><macrocell id="FB3_MC11"/><macrocell id="FB3_MC12"/><macrocell id="FB3_MC13" pin="FB3_MC13_PIND12" sigUse="0" signal="cpu_gpio_25_opad"/><macrocell id="FB3_MC14"/><macrocell id="FB3_MC15" pin="FB3_MC15_PINB13" sigUse="1" signal="cpu_gpio_02_opad"><eq_pterm ptindx="FB3_36"/></macrocell><macrocell id="FB3_MC16" pin="FB3_MC16_PINC12" sigUse="1" signal="cpu_gpio_03_opad"><eq_pterm ptindx="FB3_38"/></macrocell><fbinput id="FB3_I1" signal="cpu_gpio_21_ipad"/><fbinput id="FB3_I2" signal="uarts_0_thru_7_interrupt_ipad"/><fbinput id="FB3_I3" signal="uarts_8_thru_15_interrupt_ipad"/><PAL><pterm id="FB3_8"><signal id="cpu_gpio_21_ipad"/></pterm><pterm id="FB3_36"><signal id="uarts_0_thru_7_interrupt_ipad"/></pterm><pterm id="FB3_38"><signal id="uarts_8_thru_15_interrupt_ipad"/></pterm></PAL><equation id="cf_reset_opad"><d1><eq_pterm ptindx="FB3_8"/></d1></equation><equation id="cpu_gpio_17_opad"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="cpu_gpio_24_opad"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="cpu_gpio_25_opad"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="cpu_gpio_02_opad"><d1><eq_pterm ptindx="FB3_36"/></d1></equation><equation id="cpu_gpio_03_opad"><d1><eq_pterm ptindx="FB3_38"/></d1></equation></fblock><fblock id="FB4" pinUse="6"><macrocell id="FB4_MC1" pin="FB4_MC1_PINE13" sigUse="1" signal="cf_address_opads0_SPECSIG"><eq_pterm ptindx="FB4_8"/></macrocell><macrocell id="FB4_MC2"/><macrocell id="FB4_MC3" pin="FB4_MC3_PINC16" sigUse="2" signal="cpu_gpio_23_opad"><eq_pterm ptindx="FB4_12"/></macrocell><macrocell id="FB4_MC4" pin="FB4_MC4_PINF12" sigUse="1" signal="cf_pce2_n_opad"><eq_pterm ptindx="FB4_14"/></macrocell><macrocell id="FB4_MC5"/><macrocell id="FB4_MC6"/><macrocell id="FB4_MC7"/><macrocell id="FB4_MC8"/><macrocell id="FB4_MC9"/><macrocell id="FB4_MC10"/><macrocell id="FB4_MC11"/><macrocell id="FB4_MC12"/><macrocell id="FB4_MC13"/><macrocell id="FB4_MC14" pin="FB4_MC14_PIND16" sigUse="1" signal="cf_pce1_n_opad"><eq_pterm ptindx="FB4_34"/></macrocell><macrocell id="FB4_MC15" pin="FB4_MC15_PINE14" sigUse="0" signal="cf_csel_n_opad"/><macrocell id="FB4_MC16" pin="FB4_MC16_PINE15" sigUse="27" signal="dummy_signal_opad"><eq_pterm ptindx="FB4_38"/></macrocell><fbinput id="FB4_I1" signal="cf_cd1_n_ipad"/><fbinput id="FB4_I2" signal="cf_cd2_n_ipad"/><fbinput id="FB4_I3" signal="cf_wait_n_ipad"/><fbinput id="FB4_I4" signal="cpu_address_in_ipads0_SPECSIG"/><fbinput id="FB4_I5" signal="cpu_address_in_ipads11_SPECSIG"/><fbinput id="FB4_I6" signal="cpu_address_in_ipads12_SPECSIG"/><fbinput id="FB4_I7" signal="cpu_cs3_n_ipad"/><fbinput id="FB4_I8" signal="cpu_cs4_n_ipad"/><fbinput id="FB4_I9" signal="cpu_cs5_n_ipad"/><fbinput id="FB4_I10" signal="cpu_dqm0_n_ipad"/><fbinput id="FB4_I11" signal="cpu_dqm1_n_ipad"/><fbinput id="FB4_I12" signal="cpu_gpio_15_ipad"/><fbinput id="FB4_I13" signal="cpu_gpio_18_ipad"/><fbinput id="FB4_I14" signal="cpu_khz32_ipad"/><fbinput id="FB4_I15" signal="cpu_pce1_n_ipad"/><fbinput id="FB4_I16" signal="cpu_pce2_n_ipad"/><fbinput id="FB4_I17" signal="cpu_preg_n_ipad"/><fbinput id="FB4_I18" signal="cpu_rclk_ipad"/><fbinput id="FB4_I19" signal="cpu_reset_in_n_ipad"/><fbinput id="FB4_I20" signal="cts_n_00_ipad"/><fbinput id="FB4_I21" signal="cts_n_01_ipad"/><fbinput id="FB4_I22" signal="cts_n_02_ipad"/><fbinput id="FB4_I23" signal="cts_n_03_ipad"/><fbinput id="FB4_I24" signal="cts_n_04_ipad"/><fbinput id="FB4_I25" signal="cts_n_05_ipad"/><fbinput id="FB4_I26" signal="cts_n_06_ipad"/><fbinput id="FB4_I27" signal="cts_n_07_ipad"/><fbinput id="FB4_I28" signal="cts_n_08_ipad"/><fbinput id="FB4_I29" signal="cts_n_09_ipad"/><fbinput id="FB4_I30" signal="cts_n_10_ipad"/><fbinput id="FB4_I31" signal="cts_n_11_ipad"/><fbinput id="FB4_I32" signal="rtc_khz32_ipad"/><PAL><pterm id="FB4_8"><signal id="cpu_address_in_ipads0_SPECSIG"/></pterm><pterm id="FB4_12"><signal id="cf_cd2_n_ipad" negated="ON"/><signal id="cf_cd1_n_ipad" negated="ON"/></pterm><pterm id="FB4_14"><signal id="cpu_pce2_n_ipad"/></pterm><pterm id="FB4_34"><signal id="cpu_pce1_n_ipad"/></pterm><pterm id="FB4_38"><signal id="cpu_preg_n_ipad"/><signal id="cf_wait_n_ipad"/><signal id="rtc_khz32_ipad"/><signal id="cpu_reset_in_n_ipad"/><signal id="cpu_rclk_ipad"/><signal id="cpu_khz32_ipad"/><signal id="cpu_gpio_18_ipad"/><signal id="cpu_gpio_15_ipad"/><signal id="cts_n_11_ipad"/><signal id="cpu_dqm1_n_ipad"/><signal id="cpu_dqm0_n_ipad"/><signal id="cpu_cs5_n_ipad"/><signal id="cpu_cs4_n_ipad"/><signal id="cpu_cs3_n_ipad"/><signal id="cpu_address_in_ipads12_SPECSIG"/><signal id="cpu_address_in_ipads11_SPECSIG"/><signal id="cts_n_10_ipad"/><signal id="cts_n_09_ipad"/><signal id="cts_n_08_ipad"/><signal id="cts_n_07_ipad"/><signal id="cts_n_06_ipad"/><signal id="cts_n_05_ipad"/><signal id="cts_n_04_ipad"/><signal id="cts_n_03_ipad"/><signal id="cts_n_02_ipad"/><signal id="cts_n_01_ipad"/><signal id="cts_n_00_ipad"/></pterm></PAL><equation id="cf_address_opads0_SPECSIG"><d1><eq_pterm ptindx="FB4_8"/></d1></equation><equation id="cpu_gpio_23_opad" negated="ON"><d1><eq_pterm ptindx="FB4_12"/></d1></equation><equation id="cf_pce2_n_opad"><d1><eq_pterm ptindx="FB4_14"/></d1></equation><equation id="cf_pce1_n_opad"><d1><eq_pterm ptindx="FB4_34"/></d1></equation><equation id="cf_csel_n_opad"><d2><eq_pterm ptindx="VCC"/></d2></equation><equation id="dummy_signal_opad"><d1><eq_pterm ptindx="FB4_38"/></d1></equation></fblock><fblock id="FB5" pinUse="6"><macrocell id="FB5_MC1" pin="FB5_MC1_PINA12" sigUse="1" signal="cpu_gpio_19_opad"><eq_pterm ptindx="FB5_8"/></macrocell><macrocell id="FB5_MC2"/><macrocell id="FB5_MC3" pin="FB5_MC3_PIND11" sigUse="1" signal="cpu_gpio_20_opad"><eq_pterm ptindx="FB5_12"/></macrocell><macrocell id="FB5_MC4"/><macrocell id="FB5_MC5"/><macrocell id="FB5_MC6"/><macrocell id="FB5_MC7"/><macrocell id="FB5_MC8"/><macrocell id="FB5_MC9"/><macrocell id="FB5_MC10"/><macrocell id="FB5_MC11"/><macrocell id="FB5_MC12"/><macrocell id="FB5_MC13" pin="FB5_MC13_PINA11" sigUse="1" signal="cpu_gpio_22_opad"><eq_pterm ptindx="FB5_32"/></macrocell><macrocell id="FB5_MC14" pin="FB5_MC14_PINE10"/><macrocell id="FB5_MC15" pin="FB5_MC15_PINB12"/><macrocell id="FB5_MC16" pin="FB5_MC16_PINC11"/><fbinput id="FB5_I1" signal="cf_bvd_1_ipad"/><fbinput id="FB5_I2" signal="cf_bvd_2_ipad"/><fbinput id="FB5_I3" signal="cf_rdy_bsy_ipad"/><PAL><pterm id="FB5_8"><signal id="cf_bvd_1_ipad"/></pterm><pterm id="FB5_12"><signal id="cf_bvd_2_ipad"/></pterm><pterm id="FB5_32"><signal id="cf_rdy_bsy_ipad"/></pterm></PAL><equation id="cpu_gpio_19_opad"><d1><eq_pterm ptindx="FB5_8"/></d1></equation><equation id="cpu_gpio_20_opad"><d1><eq_pterm ptindx="FB5_12"/></d1></equation><equation id="cpu_gpio_22_opad"><d1><eq_pterm ptindx="FB5_32"/></d1></equation></fblock><fblock id="FB6" pinUse="6"><macrocell id="FB6_MC1" pin="FB6_MC1_PINF13" sigUse="1" signal="uart_address_opads0_SPECSIG"><eq_pterm ptindx="FB6_8"/></macrocell><macrocell id="FB6_MC2"/><macrocell id="FB6_MC3" pin="FB6_MC3_PINE16" sigUse="2" signal="cf_data_iopads0_SPECSIG"><eq_pterm ptindx="FB6_12"/></macrocell><macrocell id="FB6_MC4"/><macrocell id="FB6_MC5"/><macrocell id="FB6_MC6"/><macrocell id="FB6_MC7"/><macrocell id="FB6_MC8"/><macrocell id="FB6_MC9"/><macrocell id="FB6_MC10"/><macrocell id="FB6_MC11"/><macrocell id="FB6_MC12"/><macrocell id="FB6_MC13" pin="FB6_MC13_PINF15" sigUse="2" signal="cf_data_iopads11_SPECSIG"><eq_pterm ptindx="FB6_32"/></macrocell><macrocell id="FB6_MC14" pin="FB6_MC14_PING12" sigUse="2" signal="cf_data_iopads12_SPECSIG"><eq_pterm ptindx="FB6_34"/></macrocell><macrocell id="FB6_MC15" pin="FB6_MC15_PINF14" sigUse="2" signal="cf_data_iopads10_SPECSIG"><eq_pterm ptindx="FB6_36"/></macrocell><macrocell id="FB6_MC16" pin="FB6_MC16_PING15" sigUse="2" signal="cf_data_iopads13_SPECSIG"><eq_pterm ptindx="FB6_38"/></macrocell><fbinput id="FB6_I1" signal="_n0003"/><fbinput id="FB6_I2" signal="cpu_address_in_ipads1_SPECSIG"/><fbinput id="FB6_I3" fbk="PIN" signal="cpu_data_iopads0PIN_SPECSIG"/><fbinput id="FB6_I4" fbk="PIN" signal="cpu_data_iopads10PIN_SPECSIG"/><fbinput id="FB6_I5" fbk="PIN" signal="cpu_data_iopads11PIN_SPECSIG"/><fbinput id="FB6_I6" fbk="PIN" signal="cpu_data_iopads12PIN_SPECSIG"/><fbinput id="FB6_I7" fbk="PIN" signal="cpu_data_iopads13PIN_SPECSIG"/><PAL><pterm id="FB6_0"><signal id="_n0003"/></pterm><pterm id="FB6_8"><signal id="cpu_address_in_ipads1_SPECSIG"/></pterm><pterm id="FB6_12"><signal id="cpu_data_iopads0PIN_SPECSIG"/></pterm><pterm id="FB6_32"><signal id="cpu_data_iopads11PIN_SPECSIG"/></pterm><pterm id="FB6_34"><signal id="cpu_data_iopads12PIN_SPECSIG"/></pterm><pterm id="FB6_36"><signal id="cpu_data_iopads10PIN_SPECSIG"/></pterm><pterm id="FB6_38"><signal id="cpu_data_iopads13PIN_SPECSIG"/></pterm></PAL><equation id="uart_address_opads0_SPECSIG"><d1><eq_pterm ptindx="FB6_8"/></d1></equation><equation id="cf_data_iopads0_SPECSIG"><d1><eq_pterm ptindx="FB6_12"/></d1><oe><eq_pterm ptindx="FB6_0"/></oe></equation><equation id="cf_data_iopads11_SPECSIG"><d1><eq_pterm ptindx="FB6_32"/></d1><oe><eq_pterm ptindx="FB6_0"/></oe></equation><equation id="cf_data_iopads12_SPECSIG"><d1><eq_pterm ptindx="FB6_34"/></d1><oe><eq_pterm ptindx="FB6_0"/></oe></equation><equation id="cf_data_iopads10_SPECSIG"><d1><eq_pterm ptindx="FB6_36"/></d1><oe><eq_pterm ptindx="FB6_0"/></oe></equation><equation id="cf_data_iopads13_SPECSIG"><d1><eq_pterm ptindx="FB6_38"/></d1><oe><eq_pterm ptindx="FB6_0"/></oe></equation></fblock><fblock id="FB7" pinUse="5"><macrocell id="FB7_MC1" pin="FB7_MC1_PINB11" sigUse="1" signal="cpu_gpio_07_opad"><eq_pterm ptindx="FB7_8"/></macrocell><macrocell id="FB7_MC2" pin="FB7_MC2_PIND10" sigUse="1" signal="cpu_gpio_01_opad"><eq_pterm ptindx="FB7_10"/></macrocell><macrocell id="FB7_MC3" pin="FB7_MC3_PINA10" sigUse="1" signal="cpu_gpio_00_opad"><eq_pterm ptindx="FB7_12"/></macrocell><macrocell id="FB7_MC4" pin="FB7_MC4_PINC10"/><macrocell id="FB7_MC5"/><macrocell id="FB7_MC6"/><macrocell id="FB7_MC7"/><macrocell id="FB7_MC8"/><macrocell id="FB7_MC9"/><macrocell id="FB7_MC10"/><macrocell id="FB7_MC11"/><macrocell id="FB7_MC12"/><macrocell id="FB7_MC13"/><macrocell id="FB7_MC14"/><macrocell id="FB7_MC15" pin="FB7_MC15_PINA9" sigUse="0" signal="cpu_ready_opad"/><macrocell id="FB7_MC16" pin="FB7_MC16_PIND9" sigUse="1" signal="uart_address_opads4_SPECSIG"><eq_pterm ptindx="FB7_38"/></macrocell><fbinput id="FB7_I1" signal="attention_arm_ipad"/><fbinput id="FB7_I2" signal="cpu_address_in_ipads5_SPECSIG"/><fbinput id="FB7_I3" signal="ethernet_lanled_ipad"/><fbinput id="FB7_I4" signal="lr_ri_ipad"/><PAL><pterm id="FB7_8"><signal id="lr_ri_ipad"/></pterm><pterm id="FB7_10"><signal id="ethernet_lanled_ipad"/></pterm><pterm id="FB7_12"><signal id="attention_arm_ipad"/></pterm><pterm id="FB7_38"><signal id="cpu_address_in_ipads5_SPECSIG"/></pterm></PAL><equation id="cpu_gpio_07_opad"><d1><eq_pterm ptindx="FB7_8"/></d1></equation><equation id="cpu_gpio_01_opad"><d1><eq_pterm ptindx="FB7_10"/></d1></equation><equation id="cpu_gpio_00_opad"><d1><eq_pterm ptindx="FB7_12"/></d1></equation><equation id="cpu_ready_opad"><d2><eq_pterm ptindx="VCC"/></d2></equation><equation id="uart_address_opads4_SPECSIG"><d1><eq_pterm ptindx="FB7_38"/></d1></equation></fblock><fblock id="FB8" pinUse="6"><macrocell id="FB8_MC1" pin="FB8_MC1_PING13" sigUse="2" signal="cf_data_iopads14_SPECSIG"><eq_pterm ptindx="FB8_8"/></macrocell><macrocell id="FB8_MC2"/><macrocell id="FB8_MC3" pin="FB8_MC3_PINF16" sigUse="2" signal="cf_data_iopads15_SPECSIG"><eq_pterm ptindx="FB8_12"/></macrocell><macrocell id="FB8_MC4"/><macrocell id="FB8_MC5"/><macrocell id="FB8_MC6"/><macrocell id="FB8_MC7"/><macrocell id="FB8_MC8"/><macrocell id="FB8_MC9"/><macrocell id="FB8_MC10"/><macrocell id="FB8_MC11"/><macrocell id="FB8_MC12"/><macrocell id="FB8_MC13" pin="FB8_MC13_PING14" sigUse="3" signal="cpu_data_iopads0_SPECSIG"><eq_pterm ptindx="FB8_1"/><eq_pterm ptindx="FB8_2"/></macrocell><macrocell id="FB8_MC14" pin="FB8_MC14_PING16" sigUse="2" signal="cpu_data_iopads10_SPECSIG"><eq_pterm ptindx="FB8_34"/></macrocell><macrocell id="FB8_MC15" pin="FB8_MC15_PINH13" sigUse="2" signal="cpu_data_iopads11_SPECSIG"><eq_pterm ptindx="FB8_36"/></macrocell><macrocell id="FB8_MC16" pin="FB8_MC16_PINH12" sigUse="2" signal="cpu_data_iopads12_SPECSIG"><eq_pterm ptindx="FB8_38"/></macrocell><fbinput id="FB8_I1" signal="_n0003"/><fbinput id="FB8_I2" fbk="PIN" signal="cf_data_iopads0PIN_SPECSIG"/><fbinput id="FB8_I3" fbk="PIN" signal="cf_data_iopads10PIN_SPECSIG"/><fbinput id="FB8_I4" fbk="PIN" signal="cf_data_iopads11PIN_SPECSIG"/><fbinput id="FB8_I5" fbk="PIN" signal="cf_data_iopads12PIN_SPECSIG"/><fbinput id="FB8_I6" fbk="PIN" signal="cpu_data_iopads14PIN_SPECSIG"/><fbinput id="FB8_I7" fbk="PIN" signal="cpu_data_iopads15PIN_SPECSIG"/><fbinput id="FB8_I8" signal="cpu_uart_cs_n_ipad"/><fbinput id="FB8_I9" fbk="PIN" signal="uart_data_iopads0PIN_SPECSIG"/><PAL><pterm id="FB8_0"><signal id="_n0003"/></pterm><pterm id="FB8_1"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads0PIN_SPECSIG"/></pterm><pterm id="FB8_2"><signal id="cpu_uart_cs_n_ipad" negated="ON"/><signal id="uart_data_iopads0PIN_SPECSIG"/></pterm><pterm id="FB8_8"><signal id="cpu_data_iopads14PIN_SPECSIG"/></pterm><pterm id="FB8_12"><signal id="cpu_data_iopads15PIN_SPECSIG"/></pterm><pterm id="FB8_34"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads10PIN_SPECSIG"/></pterm><pterm id="FB8_36"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads11PIN_SPECSIG"/></pterm><pterm id="FB8_38"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads12PIN_SPECSIG"/></pterm></PAL><equation id="cf_data_iopads14_SPECSIG"><d1><eq_pterm ptindx="FB8_8"/></d1><oe><eq_pterm ptindx="FB8_0"/></oe></equation><equation id="cf_data_iopads15_SPECSIG"><d1><eq_pterm ptindx="FB8_12"/></d1><oe><eq_pterm ptindx="FB8_0"/></oe></equation><equation id="cpu_data_iopads0_SPECSIG"><d2><eq_pterm ptindx="FB8_1"/><eq_pterm ptindx="FB8_2"/></d2><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads10_SPECSIG"><d1><eq_pterm ptindx="FB8_34"/></d1><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads11_SPECSIG"><d1><eq_pterm ptindx="FB8_36"/></d1><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads12_SPECSIG"><d1><eq_pterm ptindx="FB8_38"/></d1><oe><eq_pterm ptindx="FB1_7"/></oe></equation></fblock><fblock id="FB9" pinUse="7"><macrocell id="FB9_MC1" pin="FB9_MC1_PINP16" sigUse="1" signal="uart_address_opads6_SPECSIG"><eq_pterm ptindx="FB9_8"/></macrocell><macrocell id="FB9_MC2" pin="FB9_MC2_PINN14" sigUse="2" signal="cf_data_iopads7_SPECSIG"><eq_pterm ptindx="FB9_10"/></macrocell><macrocell id="FB9_MC3" pin="FB9_MC3_PINR16" sigUse="1" signal="uart_address_opads7_SPECSIG"><eq_pterm ptindx="FB9_12"/></macrocell><macrocell id="FB9_MC4"/><macrocell id="FB9_MC5"/><macrocell id="FB9_MC6"/><macrocell id="FB9_MC7"/><macrocell id="FB9_MC8"/><macrocell id="FB9_MC9"/><macrocell id="FB9_MC10"/><macrocell id="FB9_MC11"/><macrocell id="FB9_MC12"/><macrocell id="FB9_MC13" pin="FB9_MC13_PINM13" sigUse="2" signal="cf_data_iopads8_SPECSIG"><eq_pterm ptindx="FB9_32"/></macrocell><macrocell id="FB9_MC14" pin="FB9_MC14_PINP15" sigUse="2" signal="cf_data_iopads9_SPECSIG"><eq_pterm ptindx="FB9_34"/></macrocell><macrocell id="FB9_MC15" pin="FB9_MC15_PINL12" sigUse="2" signal="cf_data_iopads4_SPECSIG"><eq_pterm ptindx="FB9_36"/></macrocell><macrocell id="FB9_MC16" pin="FB9_MC16_PINN16" sigUse="1" signal="uart_address_opads3_SPECSIG"><eq_pterm ptindx="FB9_38"/></macrocell><fbinput id="FB9_I1" signal="_n0003"/><fbinput id="FB9_I2" signal="cpu_address_in_ipads4_SPECSIG"/><fbinput id="FB9_I3" signal="cpu_address_in_ipads7_SPECSIG"/><fbinput id="FB9_I4" signal="cpu_address_in_ipads8_SPECSIG"/><fbinput id="FB9_I5" fbk="PIN" signal="cpu_data_iopads4PIN_SPECSIG"/><fbinput id="FB9_I6" fbk="PIN" signal="cpu_data_iopads7PIN_SPECSIG"/><fbinput id="FB9_I7" fbk="PIN" signal="cpu_data_iopads8PIN_SPECSIG"/><fbinput id="FB9_I8" fbk="PIN" signal="cpu_data_iopads9PIN_SPECSIG"/><PAL><pterm id="FB9_0"><signal id="_n0003"/></pterm><pterm id="FB9_8"><signal id="cpu_address_in_ipads7_SPECSIG"/></pterm><pterm id="FB9_10"><signal id="cpu_data_iopads7PIN_SPECSIG"/></pterm><pterm id="FB9_12"><signal id="cpu_address_in_ipads8_SPECSIG"/></pterm><pterm id="FB9_32"><signal id="cpu_data_iopads8PIN_SPECSIG"/></pterm><pterm id="FB9_34"><signal id="cpu_data_iopads9PIN_SPECSIG"/></pterm><pterm id="FB9_36"><signal id="cpu_data_iopads4PIN_SPECSIG"/></pterm><pterm id="FB9_38"><signal id="cpu_address_in_ipads4_SPECSIG"/></pterm></PAL><equation id="uart_address_opads6_SPECSIG"><d1><eq_pterm ptindx="FB9_8"/></d1></equation><equation id="cf_data_iopads7_SPECSIG"><d1><eq_pterm ptindx="FB9_10"/></d1><oe><eq_pterm ptindx="FB9_0"/></oe></equation><equation id="uart_address_opads7_SPECSIG"><d1><eq_pterm ptindx="FB9_12"/></d1></equation><equation id="cf_data_iopads8_SPECSIG"><d1><eq_pterm ptindx="FB9_32"/></d1><oe><eq_pterm ptindx="FB9_0"/></oe></equation><equation id="cf_data_iopads9_SPECSIG"><d1><eq_pterm ptindx="FB9_34"/></d1><oe><eq_pterm ptindx="FB9_0"/></oe></equation><equation id="cf_data_iopads4_SPECSIG"><d1><eq_pterm ptindx="FB9_36"/></d1><oe><eq_pterm ptindx="FB9_0"/></oe></equation><equation id="uart_address_opads3_SPECSIG"><d1><eq_pterm ptindx="FB9_38"/></d1></equation></fblock><fblock id="FB10" pinUse="7"><macrocell id="FB10_MC1" pin="FB10_MC1_PINN13" sigUse="2" signal="cf_data_iopads6_SPECSIG"><eq_pterm ptindx="FB10_8"/></macrocell><macrocell id="FB10_MC2" pin="FB10_MC2_PINR15" sigUse="1" signal="uart_address_opads5_SPECSIG"><eq_pterm ptindx="FB10_10"/></macrocell><macrocell id="FB10_MC3" pin="FB10_MC3_PINM12" sigUse="2" signal="cf_data_iopads5_SPECSIG"><eq_pterm ptindx="FB10_12"/></macrocell><macrocell id="FB10_MC4"/><macrocell id="FB10_MC5"/><macrocell id="FB10_MC6"/><macrocell id="FB10_MC7"/><macrocell id="FB10_MC8"/><macrocell id="FB10_MC9"/><macrocell id="FB10_MC10"/><macrocell id="FB10_MC11"/><macrocell id="FB10_MC12"/><macrocell id="FB10_MC13" pin="FB10_MC13_PINT16" sigUse="1" signal="cf_poe_n_opad"><eq_pterm ptindx="FB10_32"/></macrocell><macrocell id="FB10_MC14" pin="FB10_MC14_PINP14" sigUse="1" signal="cf_piow_n_opad"><eq_pterm ptindx="FB10_34"/></macrocell><macrocell id="FB10_MC15" pin="FB10_MC15_PINT15" sigUse="1" signal="cf_pior_n_opad"><eq_pterm ptindx="FB10_36"/></macrocell><macrocell id="FB10_MC16" pin="FB10_MC16_PINP13" sigUse="1" signal="cf_address_opads9_SPECSIG"><eq_pterm ptindx="FB10_38"/></macrocell><fbinput id="FB10_I1" signal="_n0003"/><fbinput id="FB10_I2" signal="cpu_address_in_ipads6_SPECSIG"/><fbinput id="FB10_I3" signal="cpu_address_in_ipads9_SPECSIG"/><fbinput id="FB10_I4" fbk="PIN" signal="cpu_data_iopads5PIN_SPECSIG"/><fbinput id="FB10_I5" fbk="PIN" signal="cpu_data_iopads6PIN_SPECSIG"/><fbinput id="FB10_I6" signal="cpu_pior_n_ipad"/><fbinput id="FB10_I7" signal="cpu_piow_n_ipad"/><fbinput id="FB10_I8" signal="cpu_poe_n_ipad"/><PAL><pterm id="FB10_0"><signal id="_n0003"/></pterm><pterm id="FB10_8"><signal id="cpu_data_iopads6PIN_SPECSIG"/></pterm><pterm id="FB10_10"><signal id="cpu_address_in_ipads6_SPECSIG"/></pterm><pterm id="FB10_12"><signal id="cpu_data_iopads5PIN_SPECSIG"/></pterm><pterm id="FB10_32"><signal id="cpu_poe_n_ipad"/></pterm><pterm id="FB10_34"><signal id="cpu_piow_n_ipad"/></pterm><pterm id="FB10_36"><signal id="cpu_pior_n_ipad"/></pterm><pterm id="FB10_38"><signal id="cpu_address_in_ipads9_SPECSIG"/></pterm></PAL><equation id="cf_data_iopads6_SPECSIG"><d1><eq_pterm ptindx="FB10_8"/></d1><oe><eq_pterm ptindx="FB10_0"/></oe></equation><equation id="uart_address_opads5_SPECSIG"><d1><eq_pterm ptindx="FB10_10"/></d1></equation><equation id="cf_data_iopads5_SPECSIG"><d1><eq_pterm ptindx="FB10_12"/></d1><oe><eq_pterm ptindx="FB10_0"/></oe></equation><equation id="cf_poe_n_opad"><d1><eq_pterm ptindx="FB10_32"/></d1></equation><equation id="cf_piow_n_opad"><d1><eq_pterm ptindx="FB10_34"/></d1></equation><equation id="cf_pior_n_opad"><d1><eq_pterm ptindx="FB10_36"/></d1></equation><equation id="cf_address_opads9_SPECSIG"><d1><eq_pterm ptindx="FB10_38"/></d1></equation></fblock><fblock id="FB11" pinUse="7"><macrocell id="FB11_MC1" pin="FB11_MC1_PINM14" sigUse="2" signal="cf_data_iopads3_SPECSIG"><eq_pterm ptindx="FB11_8"/></macrocell><macrocell id="FB11_MC2" pin="FB11_MC2_PINM16" sigUse="2" signal="cf_data_iopads2_SPECSIG"><eq_pterm ptindx="FB11_10"/></macrocell><macrocell id="FB11_MC3" pin="FB11_MC3_PINL13" sigUse="1" signal="uart_address_opads2_SPECSIG"><eq_pterm ptindx="FB11_12"/></macrocell><macrocell id="FB11_MC4" pin="FB11_MC4_PINN15" sigUse="1" signal="cpu_pwait_n_opad"><eq_pterm ptindx="FB11_14"/></macrocell><macrocell id="FB11_MC5"/><macrocell id="FB11_MC6"/><macrocell id="FB11_MC7"/><macrocell id="FB11_MC8"/><macrocell id="FB11_MC9"/><macrocell id="FB11_MC10"/><macrocell id="FB11_MC11"/><macrocell id="FB11_MC12"/><macrocell id="FB11_MC13"/><macrocell id="FB11_MC14" pin="FB11_MC14_PINM15" sigUse="1" signal="cpu_iois16_n_opad"><eq_pterm ptindx="FB11_34"/></macrocell><macrocell id="FB11_MC15" pin="FB11_MC15_PINL16" sigUse="1" signal="cf_pwe_n_opad"><eq_pterm ptindx="FB11_36"/></macrocell><macrocell id="FB11_MC16" pin="FB11_MC16_PINK12" sigUse="1" signal="cf_preg_n_opad"><eq_pterm ptindx="FB11_38"/></macrocell><fbinput id="FB11_I1" signal="_n0003"/><fbinput id="FB11_I2" signal="cf_iois16_n_ipad"/><fbinput id="FB11_I3" signal="cf_wait_n_ipad"/><fbinput id="FB11_I4" signal="cpu_address_in_ipads3_SPECSIG"/><fbinput id="FB11_I5" fbk="PIN" signal="cpu_data_iopads2PIN_SPECSIG"/><fbinput id="FB11_I6" fbk="PIN" signal="cpu_data_iopads3PIN_SPECSIG"/><fbinput id="FB11_I7" signal="cpu_preg_n_ipad"/><fbinput id="FB11_I8" signal="cpu_pwe_n_ipad"/><PAL><pterm id="FB11_0"><signal id="_n0003"/></pterm><pterm id="FB11_8"><signal id="cpu_data_iopads3PIN_SPECSIG"/></pterm><pterm id="FB11_10"><signal id="cpu_data_iopads2PIN_SPECSIG"/></pterm><pterm id="FB11_12"><signal id="cpu_address_in_ipads3_SPECSIG"/></pterm><pterm id="FB11_14"><signal id="cf_wait_n_ipad"/></pterm><pterm id="FB11_34"><signal id="cf_iois16_n_ipad"/></pterm><pterm id="FB11_36"><signal id="cpu_pwe_n_ipad"/></pterm><pterm id="FB11_38"><signal id="cpu_preg_n_ipad"/></pterm></PAL><equation id="cf_data_iopads3_SPECSIG"><d1><eq_pterm ptindx="FB11_8"/></d1><oe><eq_pterm ptindx="FB11_0"/></oe></equation><equation id="cf_data_iopads2_SPECSIG"><d1><eq_pterm ptindx="FB11_10"/></d1><oe><eq_pterm ptindx="FB11_0"/></oe></equation><equation id="uart_address_opads2_SPECSIG"><d1><eq_pterm ptindx="FB11_12"/></d1></equation><equation id="cpu_pwait_n_opad"><d1><eq_pterm ptindx="FB11_14"/></d1></equation><equation id="cpu_iois16_n_opad"><d1><eq_pterm ptindx="FB11_34"/></d1></equation><equation id="cf_pwe_n_opad"><d1><eq_pterm ptindx="FB11_36"/></d1></equation><equation id="cf_preg_n_opad"><d1><eq_pterm ptindx="FB11_38"/></d1></equation></fblock><fblock id="FB12" pinUse="7"><macrocell id="FB12_MC1" pin="FB12_MC1_PINR14" sigUse="1" signal="cf_address_opads8_SPECSIG"><eq_pterm ptindx="FB12_8"/></macrocell><macrocell id="FB12_MC2" pin="FB12_MC2_PINN12" sigUse="1" signal="cf_address_opads7_SPECSIG"><eq_pterm ptindx="FB12_10"/></macrocell><macrocell id="FB12_MC3" pin="FB12_MC3_PINT14" sigUse="1" signal="cf_address_opads6_SPECSIG"><eq_pterm ptindx="FB12_12"/></macrocell><macrocell id="FB12_MC4"/><macrocell id="FB12_MC5"/><macrocell id="FB12_MC6"/><macrocell id="FB12_MC7"/><macrocell id="FB12_MC8"/><macrocell id="FB12_MC9"/><macrocell id="FB12_MC10"/><macrocell id="FB12_MC11"/><macrocell id="FB12_MC12"/><macrocell id="FB12_MC13" pin="FB12_MC13_PINM11" sigUse="1" signal="cf_address_opads5_SPECSIG"><eq_pterm ptindx="FB12_32"/></macrocell><macrocell id="FB12_MC14" pin="FB12_MC14_PINR13" sigUse="1" signal="cf_address_opads4_SPECSIG"><eq_pterm ptindx="FB12_34"/></macrocell><macrocell id="FB12_MC15" pin="FB12_MC15_PINP12" sigUse="4" signal="spi_cs_7_n_opad"><eq_pterm ptindx="FB12_36"/></macrocell><macrocell id="FB12_MC16" pin="FB12_MC16_PINT13" sigUse="1" signal="sr_power_on_opad"><eq_pterm ptindx="FB12_38"/></macrocell><fbinput id="FB12_I1" signal="cpu_address_in_ipads4_SPECSIG"/><fbinput id="FB12_I2" signal="cpu_address_in_ipads5_SPECSIG"/><fbinput id="FB12_I3" signal="cpu_address_in_ipads6_SPECSIG"/><fbinput id="FB12_I4" signal="cpu_address_in_ipads7_SPECSIG"/><fbinput id="FB12_I5" signal="cpu_address_in_ipads8_SPECSIG"/><fbinput id="FB12_I6" signal="cpu_gpio_08_ipad"/><fbinput id="FB12_I7" signal="cpu_gpio_09_ipad"/><fbinput id="FB12_I8" signal="cpu_gpio_10_ipad"/><fbinput id="FB12_I9" signal="cpu_gpio_13_ipad"/><fbinput id="FB12_I10" signal="spi_frame_n_ipad"/><PAL><pterm id="FB12_8"><signal id="cpu_address_in_ipads8_SPECSIG"/></pterm><pterm id="FB12_10"><signal id="cpu_address_in_ipads7_SPECSIG"/></pterm><pterm id="FB12_12"><signal id="cpu_address_in_ipads6_SPECSIG"/></pterm><pterm id="FB12_32"><signal id="cpu_address_in_ipads5_SPECSIG"/></pterm><pterm id="FB12_34"><signal id="cpu_address_in_ipads4_SPECSIG"/></pterm><pterm id="FB12_36"><signal id="spi_frame_n_ipad" negated="ON"/><signal id="cpu_gpio_10_ipad"/><signal id="cpu_gpio_09_ipad"/><signal id="cpu_gpio_08_ipad"/></pterm><pterm id="FB12_38"><signal id="cpu_gpio_13_ipad"/></pterm></PAL><equation id="cf_address_opads8_SPECSIG"><d1><eq_pterm ptindx="FB12_8"/></d1></equation><equation id="cf_address_opads7_SPECSIG"><d1><eq_pterm ptindx="FB12_10"/></d1></equation><equation id="cf_address_opads6_SPECSIG"><d1><eq_pterm ptindx="FB12_12"/></d1></equation><equation id="cf_address_opads5_SPECSIG"><d1><eq_pterm ptindx="FB12_32"/></d1></equation><equation id="cf_address_opads4_SPECSIG"><d1><eq_pterm ptindx="FB12_34"/></d1></equation><equation id="spi_cs_7_n_opad" negated="ON"><d1><eq_pterm ptindx="FB12_36"/></d1></equation><equation id="sr_power_on_opad"><d1><eq_pterm ptindx="FB12_38"/></d1></equation></fblock><fblock id="FB13" pinUse="7"><macrocell id="FB13_MC1" pin="FB13_MC1_PINL15" sigUse="2" signal="cf_data_iopads1_SPECSIG"><eq_pterm ptindx="FB13_8"/></macrocell><macrocell id="FB13_MC2"/><macrocell id="FB13_MC3" pin="FB13_MC3_PINK13" sigUse="1" signal="uart_address_opads1_SPECSIG"><eq_pterm ptindx="FB13_12"/></macrocell><macrocell id="FB13_MC4" pin="FB13_MC4_PINK16" sigUse="4" signal="spi_cs_5_n_opad"><eq_pterm ptindx="FB13_14"/></macrocell><macrocell id="FB13_MC5"/><macrocell id="FB13_MC6"/><macrocell id="FB13_MC7"/><macrocell id="FB13_MC8"/><macrocell id="FB13_MC9"/><macrocell id="FB13_MC10"/><macrocell id="FB13_MC11"/><macrocell id="FB13_MC12"/><macrocell id="FB13_MC13" pin="FB13_MC13_PINK14" sigUse="4" signal="spi_cs_4_n_opad"><eq_pterm ptindx="FB13_32"/></macrocell><macrocell id="FB13_MC14" pin="FB13_MC14_PINK15" sigUse="4" signal="spi_cs_3_n_opad"><eq_pterm ptindx="FB13_34"/></macrocell><macrocell id="FB13_MC15" pin="FB13_MC15_PINL14" sigUse="4" signal="spi_cs_2_n_opad"><eq_pterm ptindx="FB13_36"/></macrocell><macrocell id="FB13_MC16" pin="FB13_MC16_PINJ16" sigUse="4" signal="spi_cs_1_n_opad"><eq_pterm ptindx="FB13_38"/></macrocell><fbinput id="FB13_I1" signal="_n0003"/><fbinput id="FB13_I2" signal="cpu_address_in_ipads2_SPECSIG"/><fbinput id="FB13_I3" fbk="PIN" signal="cpu_data_iopads1PIN_SPECSIG"/><fbinput id="FB13_I4" signal="cpu_gpio_08_ipad"/><fbinput id="FB13_I5" signal="cpu_gpio_09_ipad"/><fbinput id="FB13_I6" signal="cpu_gpio_10_ipad"/><fbinput id="FB13_I7" signal="spi_frame_n_ipad"/><PAL><pterm id="FB13_0"><signal id="_n0003"/></pterm><pterm id="FB13_8"><signal id="cpu_data_iopads1PIN_SPECSIG"/></pterm><pterm id="FB13_12"><signal id="cpu_address_in_ipads2_SPECSIG"/></pterm><pterm id="FB13_14"><signal id="spi_frame_n_ipad" negated="ON"/><signal id="cpu_gpio_10_ipad"/><signal id="cpu_gpio_09_ipad" negated="ON"/><signal id="cpu_gpio_08_ipad"/></pterm><pterm id="FB13_32"><signal id="spi_frame_n_ipad" negated="ON"/><signal id="cpu_gpio_10_ipad"/><signal id="cpu_gpio_09_ipad" negated="ON"/><signal id="cpu_gpio_08_ipad" negated="ON"/></pterm><pterm id="FB13_34"><signal id="spi_frame_n_ipad" negated="ON"/><signal id="cpu_gpio_10_ipad" negated="ON"/><signal id="cpu_gpio_09_ipad"/><signal id="cpu_gpio_08_ipad"/></pterm><pterm id="FB13_36"><signal id="spi_frame_n_ipad" negated="ON"/><signal id="cpu_gpio_10_ipad" negated="ON"/><signal id="cpu_gpio_09_ipad"/><signal id="cpu_gpio_08_ipad" negated="ON"/></pterm><pterm id="FB13_38"><signal id="spi_frame_n_ipad" negated="ON"/><signal id="cpu_gpio_10_ipad" negated="ON"/><signal id="cpu_gpio_09_ipad" negated="ON"/><signal id="cpu_gpio_08_ipad"/></pterm></PAL><equation id="cf_data_iopads1_SPECSIG"><d1><eq_pterm ptindx="FB13_8"/></d1><oe><eq_pterm ptindx="FB13_0"/></oe></equation><equation id="uart_address_opads1_SPECSIG"><d1><eq_pterm ptindx="FB13_12"/></d1></equation><equation id="spi_cs_5_n_opad" negated="ON"><d1><eq_pterm ptindx="FB13_14"/></d1></equation><equation id="spi_cs_4_n_opad" negated="ON"><d1><eq_pterm ptindx="FB13_32"/></d1></equation><equation id="spi_cs_3_n_opad" negated="ON"><d1><eq_pterm ptindx="FB13_34"/></d1></equation><equation id="spi_cs_2_n_opad" negated="ON"><d1><eq_pterm ptindx="FB13_36"/></d1></equation><equation id="spi_cs_1_n_opad" negated="ON"><d1><eq_pterm ptindx="FB13_38"/></d1></equation></fblock><fblock id="FB14" pinUse="7"><macrocell id="FB14_MC1" pin="FB14_MC1_PINN11" sigUse="4" signal="spi_cs_6_n_opad"><eq_pterm ptindx="FB14_8"/></macrocell><macrocell id="FB14_MC2" pin="FB14_MC2_PINR12"/><macrocell id="FB14_MC3" pin="FB14_MC3_PINT12" sigUse="1" signal="uplink_tx_enable_opad"><eq_pterm ptindx="FB14_12"/></macrocell><macrocell id="FB14_MC4" pin="FB14_MC4_PINR11"/><macrocell id="FB14_MC5"/><macrocell id="FB14_MC6"/><macrocell id="FB14_MC7"/><macrocell id="FB14_MC8"/><macrocell id="FB14_MC9"/><macrocell id="FB14_MC10"/><macrocell id="FB14_MC11"/><macrocell id="FB14_MC12"/><macrocell id="FB14_MC13" pin="FB14_MC13_PINM10" sigUse="1" signal="uplink_rx_enable_n_opad"><eq_pterm ptindx="FB14_32"/></macrocell><macrocell id="FB14_MC14" pin="FB14_MC14_PINP11"/><macrocell id="FB14_MC15"/><macrocell id="FB14_MC16" pin="FB14_MC16_PINN10"/><fbinput id="FB14_I1" signal="cpu_gpio_08_ipad"/><fbinput id="FB14_I2" signal="cpu_gpio_09_ipad"/><fbinput id="FB14_I3" signal="cpu_gpio_10_ipad"/><fbinput id="FB14_I4" signal="cpu_gpio_11_ipad"/><fbinput id="FB14_I5" signal="cpu_gpio_12_ipad"/><fbinput id="FB14_I6" signal="spi_frame_n_ipad"/><PAL><pterm id="FB14_8"><signal id="spi_frame_n_ipad" negated="ON"/><signal id="cpu_gpio_10_ipad"/><signal id="cpu_gpio_09_ipad"/><signal id="cpu_gpio_08_ipad" negated="ON"/></pterm><pterm id="FB14_12"><signal id="cpu_gpio_12_ipad"/></pterm><pterm id="FB14_32"><signal id="cpu_gpio_11_ipad"/></pterm></PAL><equation id="spi_cs_6_n_opad" negated="ON"><d1><eq_pterm ptindx="FB14_8"/></d1></equation><equation id="uplink_tx_enable_opad"><d1><eq_pterm ptindx="FB14_12"/></d1></equation><equation id="uplink_rx_enable_n_opad" negated="ON"><d1><eq_pterm ptindx="FB14_32"/></d1></equation></fblock><fblock id="FB15" pinUse="5"><macrocell id="FB15_MC1" pin="FB15_MC1_PINJ13"/><macrocell id="FB15_MC2" pin="FB15_MC2_PINJ15" sigUse="4" signal="spi_cs_0_n_opad"><eq_pterm ptindx="FB15_10"/></macrocell><macrocell id="FB15_MC3" pin="FB15_MC3_PINJ14" sigUse="2" signal="cpu_data_iopads8_SPECSIG"><eq_pterm ptindx="FB15_12"/></macrocell><macrocell id="FB15_MC4"/><macrocell id="FB15_MC5"/><macrocell id="FB15_MC6"/><macrocell id="FB15_MC7"/><macrocell id="FB15_MC8"/><macrocell id="FB15_MC9"/><macrocell id="FB15_MC10"/><macrocell id="FB15_MC11"/><macrocell id="FB15_MC12"/><macrocell id="FB15_MC13" pin="FB15_MC13_PINH16" sigUse="2" signal="cpu_data_iopads15_SPECSIG"><eq_pterm ptindx="FB15_32"/></macrocell><macrocell id="FB15_MC14"/><macrocell id="FB15_MC15" pin="FB15_MC15_PINH14" sigUse="2" signal="cpu_data_iopads14_SPECSIG"><eq_pterm ptindx="FB15_36"/></macrocell><macrocell id="FB15_MC16" pin="FB15_MC16_PINH15" sigUse="2" signal="cpu_data_iopads13_SPECSIG"><eq_pterm ptindx="FB15_38"/></macrocell><fbinput id="FB15_I1" fbk="PIN" signal="cf_data_iopads13PIN_SPECSIG"/><fbinput id="FB15_I2" fbk="PIN" signal="cf_data_iopads14PIN_SPECSIG"/><fbinput id="FB15_I3" fbk="PIN" signal="cf_data_iopads15PIN_SPECSIG"/><fbinput id="FB15_I4" fbk="PIN" signal="cf_data_iopads8PIN_SPECSIG"/><fbinput id="FB15_I5" signal="cpu_gpio_08_ipad"/><fbinput id="FB15_I6" signal="cpu_gpio_09_ipad"/><fbinput id="FB15_I7" signal="cpu_gpio_10_ipad"/><fbinput id="FB15_I8" signal="cpu_uart_cs_n_ipad"/><fbinput id="FB15_I9" signal="spi_frame_n_ipad"/><PAL><pterm id="FB15_10"><signal id="spi_frame_n_ipad" negated="ON"/><signal id="cpu_gpio_10_ipad" negated="ON"/><signal id="cpu_gpio_09_ipad" negated="ON"/><signal id="cpu_gpio_08_ipad" negated="ON"/></pterm><pterm id="FB15_12"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads8PIN_SPECSIG"/></pterm><pterm id="FB15_32"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads15PIN_SPECSIG"/></pterm><pterm id="FB15_36"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads14PIN_SPECSIG"/></pterm><pterm id="FB15_38"><signal id="cpu_uart_cs_n_ipad"/><signal id="cf_data_iopads13PIN_SPECSIG"/></pterm></PAL><equation id="spi_cs_0_n_opad" negated="ON"><d1><eq_pterm ptindx="FB15_10"/></d1></equation><equation id="cpu_data_iopads8_SPECSIG"><d1><eq_pterm ptindx="FB15_12"/></d1><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads15_SPECSIG"><d1><eq_pterm ptindx="FB15_32"/></d1><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads14_SPECSIG"><d1><eq_pterm ptindx="FB15_36"/></d1><oe><eq_pterm ptindx="FB1_7"/></oe></equation><equation id="cpu_data_iopads13_SPECSIG"><d1><eq_pterm ptindx="FB15_38"/></d1><oe><eq_pterm ptindx="FB1_7"/></oe></equation></fblock><fblock id="FB16" pinUse="7"><macrocell id="FB16_MC1" pin="FB16_MC1_PINT11" sigUse="2" signal="uart_cs0_n_opad"><eq_pterm ptindx="FB16_8"/></macrocell><macrocell id="FB16_MC2" pin="FB16_MC2_PINR10" sigUse="2" signal="uart_cs1_n_opad"><eq_pterm ptindx="FB16_10"/></macrocell><macrocell id="FB16_MC3" pin="FB16_MC3_PINP10" sigUse="1" signal="uart_rd_n_opad"><eq_pterm ptindx="FB16_12"/></macrocell><macrocell id="FB16_MC4" pin="FB16_MC4_PINT10" sigUse="1" signal="uart_wr_n_opad"><eq_pterm ptindx="FB16_14"/></macrocell><macrocell id="FB16_MC5"/><macrocell id="FB16_MC6"/><macrocell id="FB16_MC7"/><macrocell id="FB16_MC8"/><macrocell id="FB16_MC9"/><macrocell id="FB16_MC10"/><macrocell id="FB16_MC11"/><macrocell id="FB16_MC12"/><macrocell id="FB16_MC13"/><macrocell id="FB16_MC14" pin="FB16_MC14_PINN9"/><macrocell id="FB16_MC15" pin="FB16_MC15_PINR9"/><macrocell id="FB16_MC16" pin="FB16_MC16_PINP9"/><fbinput id="FB16_I1" signal="cpu_address_in_ipads9_SPECSIG"/><fbinput id="FB16_I2" signal="cpu_oe_n_ipad"/><fbinput id="FB16_I3" signal="cpu_uart_cs_n_ipad"/><fbinput id="FB16_I4" signal="cpu_we_n_ipad"/><PAL><pterm id="FB16_8"><signal id="cpu_address_in_ipads9_SPECSIG" negated="ON"/><signal id="cpu_uart_cs_n_ipad" negated="ON"/></pterm><pterm id="FB16_10"><signal id="cpu_address_in_ipads9_SPECSIG"/><signal id="cpu_uart_cs_n_ipad" negated="ON"/></pterm><pterm id="FB16_12"><signal id="cpu_oe_n_ipad"/></pterm><pterm id="FB16_14"><signal id="cpu_we_n_ipad"/></pterm></PAL><equation id="uart_cs0_n_opad" negated="ON"><d1><eq_pterm ptindx="FB16_8"/></d1></equation><equation id="uart_cs1_n_opad" negated="ON"><d1><eq_pterm ptindx="FB16_10"/></d1></equation><equation id="uart_rd_n_opad"><d1><eq_pterm ptindx="FB16_12"/></d1></equation><equation id="uart_wr_n_opad"><d1><eq_pterm ptindx="FB16_14"/></d1></equation></fblock><fblock id="FB17" pinUse="7"><macrocell id="FB17_MC1" pin="FB17_MC1_PINB1"/><macrocell id="FB17_MC2" pin="FB17_MC2_PINB2"/><macrocell id="FB17_MC3" pin="FB17_MC3_PINC3"/><macrocell id="FB17_MC4"/><macrocell id="FB17_MC5"/><macrocell id="FB17_MC6"/><macrocell id="FB17_MC7"/><macrocell id="FB17_MC8"/><macrocell id="FB17_MC9"/><macrocell id="FB17_MC10"/><macrocell id="FB17_MC11"/><macrocell id="FB17_MC12"/><macrocell id="FB17_MC13" pin="FB17_MC13_PIND4"/><macrocell id="FB17_MC14" pin="FB17_MC14_PINA2"/><macrocell id="FB17_MC15" pin="FB17_MC15_PINA1"/><macrocell id="FB17_MC16" pin="FB17_MC16_PINB3"/><PAL/></fblock><fblock id="FB18" pinUse="6"><macrocell id="FB18_MC1" pin="FB18_MC1_PINC1"/><macrocell id="FB18_MC2" pin="FB18_MC2_PIND3"/><macrocell id="FB18_MC3" pin="FB18_MC3_PINC2"/><macrocell id="FB18_MC4" pin="FB18_MC4_PINF5"/><macrocell id="FB18_MC5"/><macrocell id="FB18_MC6"/><macrocell id="FB18_MC7"/><macrocell id="FB18_MC8"/><macrocell id="FB18_MC9"/><macrocell id="FB18_MC10"/><macrocell id="FB18_MC11"/><macrocell id="FB18_MC12"/><macrocell id="FB18_MC13"/><macrocell id="FB18_MC14" pin="FB18_MC14_PIND1"/><macrocell id="FB18_MC15"/><macrocell id="FB18_MC16" pin="FB18_MC16_PINE4"/><PAL/></fblock><fblock id="FB19" pinUse="7"><macrocell id="FB19_MC1" pin="FB19_MC1_PINC4"/><macrocell id="FB19_MC2"/><macrocell id="FB19_MC3" pin="FB19_MC3_PINA3"/><macrocell id="FB19_MC4" pin="FB19_MC4_PIND5"/><macrocell id="FB19_MC5"/><macrocell id="FB19_MC6"/><macrocell id="FB19_MC7"/><macrocell id="FB19_MC8"/><macrocell id="FB19_MC9"/><macrocell id="FB19_MC10"/><macrocell id="FB19_MC11"/><macrocell id="FB19_MC12"/><macrocell id="FB19_MC13" pin="FB19_MC13_PINB4"/><macrocell id="FB19_MC14" pin="FB19_MC14_PINE6" sigUse="1" signal="cpu_gpio_26_opad"><eq_pterm ptindx="FB19_34"/></macrocell><macrocell id="FB19_MC15" pin="FB19_MC15_PINA4" sigUse="1" signal="reset_out_n_opad"><eq_pterm ptindx="FB19_36"/></macrocell><macrocell id="FB19_MC16" pin="FB19_MC16_PINC5" sigUse="1" signal="ethernet_sleep_n_opad"><eq_pterm ptindx="FB19_38"/></macrocell><fbinput id="FB19_I1" signal="cpu_gpio_27_ipad"/><fbinput id="FB19_I2" signal="ethernet_interrupt_ipad"/><fbinput id="FB19_I3" signal="power_on_reset_n_ipad"/><PAL><pterm id="FB19_34"><signal id="ethernet_interrupt_ipad"/></pterm><pterm id="FB19_36"><signal id="power_on_reset_n_ipad"/></pterm><pterm id="FB19_38"><signal id="cpu_gpio_27_ipad"/></pterm></PAL><equation id="cpu_gpio_26_opad"><d1><eq_pterm ptindx="FB19_34"/></d1></equation><equation id="reset_out_n_opad"><d1><eq_pterm ptindx="FB19_36"/></d1></equation><equation id="ethernet_sleep_n_opad"><d1><eq_pterm ptindx="FB19_38"/></d1></equation></fblock><fblock id="FB20" pinUse="6"><macrocell id="FB20_MC1" pin="FB20_MC1_PIND2"/><macrocell id="FB20_MC2" pin="FB20_MC2_PINE3"/><macrocell id="FB20_MC3"/><macrocell id="FB20_MC4" pin="FB20_MC4_PINE1"/><macrocell id="FB20_MC5"/><macrocell id="FB20_MC6"/><macrocell id="FB20_MC7"/><macrocell id="FB20_MC8"/><macrocell id="FB20_MC9"/><macrocell id="FB20_MC10"/><macrocell id="FB20_MC11"/><macrocell id="FB20_MC12"/><macrocell id="FB20_MC13"/><macrocell id="FB20_MC14" pin="FB20_MC14_PINF4"/><macrocell id="FB20_MC15" pin="FB20_MC15_PINF1"/><macrocell id="FB20_MC16" pin="FB20_MC16_PING5"/><PAL/></fblock><fblock id="FB21" pinUse="7"><macrocell id="FB21_MC1" pin="FB21_MC1_PINB5"/><macrocell id="FB21_MC2" pin="FB21_MC2_PIND6"/><macrocell id="FB21_MC3" pin="FB21_MC3_PINA5"/><macrocell id="FB21_MC4"/><macrocell id="FB21_MC5"/><macrocell id="FB21_MC6"/><macrocell id="FB21_MC7"/><macrocell id="FB21_MC8"/><macrocell id="FB21_MC9"/><macrocell id="FB21_MC10"/><macrocell id="FB21_MC11"/><macrocell id="FB21_MC12"/><macrocell id="FB21_MC13" pin="FB21_MC13_PINC6"/><macrocell id="FB21_MC14" pin="FB21_MC14_PINB6"/><macrocell id="FB21_MC15" pin="FB21_MC15_PINE7"/><macrocell id="FB21_MC16" pin="FB21_MC16_PINA6" sigUse="0" signal="cpu_gpio_16_opad"/><PAL/><equation id="cpu_gpio_16_opad"><d2><eq_pterm ptindx="GND"/></d2></equation></fblock><fblock id="FB22" pinUse="6"><macrocell id="FB22_MC1" pin="FB22_MC1_PINE2" sigUse="1" signal="cpu_gpio_04_opad"><eq_pterm ptindx="FB22_8"/></macrocell><macrocell id="FB22_MC2" pin="FB22_MC2_PINF3" sigUse="1" signal="cpu_gpio_05_opad"><eq_pterm ptindx="FB22_10"/></macrocell><macrocell id="FB22_MC3"/><macrocell id="FB22_MC4" pin="FB22_MC4_PINF2" sigUse="1" signal="cpu_gpio_06_opad"><eq_pterm ptindx="FB22_14"/></macrocell><macrocell id="FB22_MC5"/><macrocell id="FB22_MC6"/><macrocell id="FB22_MC7"/><macrocell id="FB22_MC8"/><macrocell id="FB22_MC9"/><macrocell id="FB22_MC10"/><macrocell id="FB22_MC11"/><macrocell id="FB22_MC12"/><macrocell id="FB22_MC13"/><macrocell id="FB22_MC14" pin="FB22_MC14_PING4"/><macrocell id="FB22_MC15" pin="FB22_MC15_PING1"/><macrocell id="FB22_MC16" pin="FB22_MC16_PING3"/><fbinput id="FB22_I1" signal="rtc_irq_n_ipad"/><fbinput id="FB22_I2" signal="spi_interrupt_ipad"/><fbinput id="FB22_I3" signal="sr_ri_ipad"/><PAL><pterm id="FB22_8"><signal id="spi_interrupt_ipad"/></pterm><pterm id="FB22_10"><signal id="rtc_irq_n_ipad"/></pterm><pterm id="FB22_14"><signal id="sr_ri_ipad"/></pterm></PAL><equation id="cpu_gpio_04_opad"><d1><eq_pterm ptindx="FB22_8"/></d1></equation><equation id="cpu_gpio_05_opad"><d1><eq_pterm ptindx="FB22_10"/></d1></equation><equation id="cpu_gpio_06_opad"><d1><eq_pterm ptindx="FB22_14"/></d1></equation></fblock><fblock id="FB23" pinUse="6"><macrocell id="FB23_MC1" pin="FB23_MC1_PIND7"/><macrocell id="FB23_MC2" pin="FB23_MC2_PINB7"/><macrocell id="FB23_MC3" pin="FB23_MC3_PINC7"/><macrocell id="FB23_MC4" pin="FB23_MC4_PINC8"/><macrocell id="FB23_MC5"/><macrocell id="FB23_MC6"/><macrocell id="FB23_MC7"/><macrocell id="FB23_MC8"/><macrocell id="FB23_MC9"/><macrocell id="FB23_MC10"/><macrocell id="FB23_MC11"/><macrocell id="FB23_MC12"/><macrocell id="FB23_MC13"/><macrocell id="FB23_MC14" pin="FB23_MC14_PINA7"/><macrocell id="FB23_MC15" pin="FB23_MC15_PIND8"/><macrocell id="FB23_MC16" pin="FB23_MC16_PINB8" sigUse="0" signal="cf_power_on_opad"/><PAL/><equation id="cf_power_on_opad"><d2><eq_pterm ptindx="VCC"/></d2></equation></fblock><fblock id="FB24" pinUse="6"><macrocell id="FB24_MC1" pin="FB24_MC1_PINH1"/><macrocell id="FB24_MC2" pin="FB24_MC2_PINH4"/><macrocell id="FB24_MC3" pin="FB24_MC3_PING2"/><macrocell id="FB24_MC4" pin="FB24_MC4_PINH3" sigUse="1" signal="net_reset_opad"><eq_pterm ptindx="FB24_14"/></macrocell><macrocell id="FB24_MC5"/><macrocell id="FB24_MC6"/><macrocell id="FB24_MC7"/><macrocell id="FB24_MC8"/><macrocell id="FB24_MC9"/><macrocell id="FB24_MC10"/><macrocell id="FB24_MC11"/><macrocell id="FB24_MC12"/><macrocell id="FB24_MC13" pin="FB24_MC13_PINJ1"/><macrocell id="FB24_MC14"/><macrocell id="FB24_MC15"/><macrocell id="FB24_MC16" pin="FB24_MC16_PINJ3"/><fbinput id="FB24_I1" signal="power_on_reset_n_ipad"/><PAL><pterm id="FB24_14"><signal id="power_on_reset_n_ipad"/></pterm></PAL><equation id="net_reset_opad" negated="ON"><d1><eq_pterm ptindx="FB24_14"/></d1></equation></fblock><fblock id="FB25" pinUse="6"><macrocell id="FB25_MC1" pin="FB25_MC1_PINP2" sigUse="0" signal="test_opads13_SPECSIG"/><macrocell id="FB25_MC2" pin="FB25_MC2_PINP3" sigUse="0" signal="test_opads14_SPECSIG"/><macrocell id="FB25_MC3"/><macrocell id="FB25_MC4" pin="FB25_MC4_PINT1"/><macrocell id="FB25_MC5"/><macrocell id="FB25_MC6"/><macrocell id="FB25_MC7"/><macrocell id="FB25_MC8"/><macrocell id="FB25_MC9"/><macrocell id="FB25_MC10"/><macrocell id="FB25_MC11"/><macrocell id="FB25_MC12"/><macrocell id="FB25_MC13"/><macrocell id="FB25_MC14" pin="FB25_MC14_PINN3" sigUse="0" signal="test_opads11_SPECSIG"/><macrocell id="FB25_MC15" pin="FB25_MC15_PINR1" sigUse="1" signal="test_opads15_SPECSIG"><eq_pterm ptindx="FB25_36"/></macrocell><macrocell id="FB25_MC16" pin="FB25_MC16_PINM4" sigUse="0" signal="test_opads9_SPECSIG"/><fbinput id="FB25_I1" signal="power_on_reset_n_ipad"/><PAL><pterm id="FB25_36"><signal id="power_on_reset_n_ipad"/></pterm></PAL><equation id="test_opads13_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads14_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads11_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads15_SPECSIG"><d1><eq_pterm ptindx="FB25_36"/></d1></equation><equation id="test_opads9_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation></fblock><fblock id="FB26" pinUse="6"><macrocell id="FB26_MC1" pin="FB26_MC1_PINM5"/><macrocell id="FB26_MC2" pin="FB26_MC2_PINN4" sigUse="1" signal="uart_reset_n_opad"><eq_pterm ptindx="FB26_10"/></macrocell><macrocell id="FB26_MC3" pin="FB26_MC3_PINR2"/><macrocell id="FB26_MC4" pin="FB26_MC4_PINT2"/><macrocell id="FB26_MC5"/><macrocell id="FB26_MC6"/><macrocell id="FB26_MC7"/><macrocell id="FB26_MC8"/><macrocell id="FB26_MC9"/><macrocell id="FB26_MC10"/><macrocell id="FB26_MC11"/><macrocell id="FB26_MC12"/><macrocell id="FB26_MC13" pin="FB26_MC13_PINP4"/><macrocell id="FB26_MC14"/><macrocell id="FB26_MC15" pin="FB26_MC15_PINR3"/><macrocell id="FB26_MC16" pin="FB26_MC16_PINN5"/><fbinput id="FB26_I1" signal="power_on_reset_n_ipad"/><PAL><pterm id="FB26_10"><signal id="power_on_reset_n_ipad"/></pterm></PAL><equation id="uart_reset_n_opad"><d1><eq_pterm ptindx="FB26_10"/></d1></equation></fblock><fblock id="FB27" pinUse="6"><macrocell id="FB27_MC1" pin="FB27_MC1_PINP1" sigUse="0" signal="test_opads12_SPECSIG"/><macrocell id="FB27_MC2"/><macrocell id="FB27_MC3" pin="FB27_MC3_PINL5" sigUse="0" signal="test_opads5_SPECSIG"/><macrocell id="FB27_MC4" pin="FB27_MC4_PINN2" sigUse="0" signal="test_opads10_SPECSIG"/><macrocell id="FB27_MC5"/><macrocell id="FB27_MC6"/><macrocell id="FB27_MC7"/><macrocell id="FB27_MC8"/><macrocell id="FB27_MC9"/><macrocell id="FB27_MC10"/><macrocell id="FB27_MC11"/><macrocell id="FB27_MC12"/><macrocell id="FB27_MC13"/><macrocell id="FB27_MC14" pin="FB27_MC14_PINM3" sigUse="0" signal="test_opads8_SPECSIG"/><macrocell id="FB27_MC15" pin="FB27_MC15_PINL4" sigUse="0" signal="test_opads4_SPECSIG"/><macrocell id="FB27_MC16" pin="FB27_MC16_PINM2" sigUse="0" signal="test_opads7_SPECSIG"/><PAL/><equation id="test_opads12_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads5_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads10_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads8_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads4_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads7_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation></fblock><fblock id="FB28" pinUse="7"><macrocell id="FB28_MC1" pin="FB28_MC1_PINT3"/><macrocell id="FB28_MC2" pin="FB28_MC2_PINM6"/><macrocell id="FB28_MC3" pin="FB28_MC3_PINR4" sigUse="2" signal="uart_data_iopads7_SPECSIG"><eq_pterm ptindx="FB28_12"/></macrocell><macrocell id="FB28_MC4" pin="FB28_MC4_PINP5" sigUse="2" signal="uart_data_iopads6_SPECSIG"><eq_pterm ptindx="FB28_14"/></macrocell><macrocell id="FB28_MC5"/><macrocell id="FB28_MC6"/><macrocell id="FB28_MC7"/><macrocell id="FB28_MC8"/><macrocell id="FB28_MC9"/><macrocell id="FB28_MC10"/><macrocell id="FB28_MC11"/><macrocell id="FB28_MC12"/><macrocell id="FB28_MC13"/><macrocell id="FB28_MC14" pin="FB28_MC14_PINT4" sigUse="2" signal="uart_data_iopads5_SPECSIG"><eq_pterm ptindx="FB28_34"/></macrocell><macrocell id="FB28_MC15" pin="FB28_MC15_PINN6" sigUse="2" signal="uart_data_iopads4_SPECSIG"><eq_pterm ptindx="FB28_36"/></macrocell><macrocell id="FB28_MC16" pin="FB28_MC16_PINR5" sigUse="2" signal="uart_data_iopads3_SPECSIG"><eq_pterm ptindx="FB28_38"/></macrocell><fbinput id="FB28_I1" fbk="PIN" signal="cpu_data_iopads3PIN_SPECSIG"/><fbinput id="FB28_I2" fbk="PIN" signal="cpu_data_iopads4PIN_SPECSIG"/><fbinput id="FB28_I3" fbk="PIN" signal="cpu_data_iopads5PIN_SPECSIG"/><fbinput id="FB28_I4" fbk="PIN" signal="cpu_data_iopads6PIN_SPECSIG"/><fbinput id="FB28_I5" fbk="PIN" signal="cpu_data_iopads7PIN_SPECSIG"/><fbinput id="FB28_I6" signal="cpu_rnw_ipad"/><PAL><pterm id="FB28_0"><signal id="cpu_rnw_ipad"/></pterm><pterm id="FB28_12"><signal id="cpu_data_iopads7PIN_SPECSIG"/></pterm><pterm id="FB28_14"><signal id="cpu_data_iopads6PIN_SPECSIG"/></pterm><pterm id="FB28_34"><signal id="cpu_data_iopads5PIN_SPECSIG"/></pterm><pterm id="FB28_36"><signal id="cpu_data_iopads4PIN_SPECSIG"/></pterm><pterm id="FB28_38"><signal id="cpu_data_iopads3PIN_SPECSIG"/></pterm></PAL><equation id="uart_data_iopads7_SPECSIG"><d1><eq_pterm ptindx="FB28_12"/></d1><oe><eq_pterm ptindx="FB28_0"/></oe></equation><equation id="uart_data_iopads6_SPECSIG"><d1><eq_pterm ptindx="FB28_14"/></d1><oe><eq_pterm ptindx="FB28_0"/></oe></equation><equation id="uart_data_iopads5_SPECSIG"><d1><eq_pterm ptindx="FB28_34"/></d1><oe><eq_pterm ptindx="FB28_0"/></oe></equation><equation id="uart_data_iopads4_SPECSIG"><d1><eq_pterm ptindx="FB28_36"/></d1><oe><eq_pterm ptindx="FB28_0"/></oe></equation><equation id="uart_data_iopads3_SPECSIG"><d1><eq_pterm ptindx="FB28_38"/></d1><oe><eq_pterm ptindx="FB28_0"/></oe></equation></fblock><fblock id="FB29" pinUse="6"><macrocell id="FB29_MC1" pin="FB29_MC1_PINL2" sigUse="0" signal="test_opads2_SPECSIG"/><macrocell id="FB29_MC2"/><macrocell id="FB29_MC3" pin="FB29_MC3_PINM1" sigUse="0" signal="test_opads6_SPECSIG"/><macrocell id="FB29_MC4" pin="FB29_MC4_PINK5" sigUse="0" signal="test_opads1_SPECSIG"/><macrocell id="FB29_MC5"/><macrocell id="FB29_MC6"/><macrocell id="FB29_MC7"/><macrocell id="FB29_MC8"/><macrocell id="FB29_MC9"/><macrocell id="FB29_MC10"/><macrocell id="FB29_MC11"/><macrocell id="FB29_MC12"/><macrocell id="FB29_MC13" pin="FB29_MC13_PINL3" sigUse="0" signal="test_opads3_SPECSIG"/><macrocell id="FB29_MC14" pin="FB29_MC14_PINK4" sigUse="0" signal="test_opads0_SPECSIG"/><macrocell id="FB29_MC15"/><macrocell id="FB29_MC16" pin="FB29_MC16_PINL1"/><PAL/><equation id="test_opads2_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads6_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads1_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads3_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation><equation id="test_opads0_SPECSIG"><d2><eq_pterm ptindx="GND"/></d2></equation></fblock><fblock id="FB30" pinUse="7"><macrocell id="FB30_MC1" pin="FB30_MC1_PINT6" sigUse="2" signal="uart_data_iopads2_SPECSIG"><eq_pterm ptindx="FB30_8"/></macrocell><macrocell id="FB30_MC2" pin="FB30_MC2_PINT5" sigUse="2" signal="uart_data_iopads1_SPECSIG"><eq_pterm ptindx="FB30_10"/></macrocell><macrocell id="FB30_MC3" pin="FB30_MC3_PINM7" sigUse="2" signal="uart_data_iopads0_SPECSIG"><eq_pterm ptindx="FB30_12"/></macrocell><macrocell id="FB30_MC4"/><macrocell id="FB30_MC5"/><macrocell id="FB30_MC6"/><macrocell id="FB30_MC7"/><macrocell id="FB30_MC8"/><macrocell id="FB30_MC9"/><macrocell id="FB30_MC10"/><macrocell id="FB30_MC11"/><macrocell id="FB30_MC12"/><macrocell id="FB30_MC13" pin="FB30_MC13_PINR6" sigUse="1" signal="lr_power_on_opad"><eq_pterm ptindx="FB30_32"/></macrocell><macrocell id="FB30_MC14" pin="FB30_MC14_PINN7"/><macrocell id="FB30_MC15" pin="FB30_MC15_PINT7"/><macrocell id="FB30_MC16" pin="FB30_MC16_PINP6"/><fbinput id="FB30_I1" fbk="PIN" signal="cpu_data_iopads0PIN_SPECSIG"/><fbinput id="FB30_I2" fbk="PIN" signal="cpu_data_iopads1PIN_SPECSIG"/><fbinput id="FB30_I3" fbk="PIN" signal="cpu_data_iopads2PIN_SPECSIG"/><fbinput id="FB30_I4" signal="cpu_gpio_14_ipad"/><fbinput id="FB30_I5" signal="cpu_rnw_ipad"/><PAL><pterm id="FB30_0"><signal id="cpu_rnw_ipad"/></pterm><pterm id="FB30_8"><signal id="cpu_data_iopads2PIN_SPECSIG"/></pterm><pterm id="FB30_10"><signal id="cpu_data_iopads1PIN_SPECSIG"/></pterm><pterm id="FB30_12"><signal id="cpu_data_iopads0PIN_SPECSIG"/></pterm><pterm id="FB30_32"><signal id="cpu_gpio_14_ipad"/></pterm></PAL><equation id="uart_data_iopads2_SPECSIG"><d1><eq_pterm ptindx="FB30_8"/></d1><oe><eq_pterm ptindx="FB30_0"/></oe></equation><equation id="uart_data_iopads1_SPECSIG"><d1><eq_pterm ptindx="FB30_10"/></d1><oe><eq_pterm ptindx="FB30_0"/></oe></equation><equation id="uart_data_iopads0_SPECSIG"><d1><eq_pterm ptindx="FB30_12"/></d1><oe><eq_pterm ptindx="FB30_0"/></oe></equation><equation id="lr_power_on_opad"><d1><eq_pterm ptindx="FB30_32"/></d1></equation></fblock><fblock id="FB31" pinUse="2"><macrocell id="FB31_MC1" pin="FB31_MC1_PINK2" sigUse="0" signal="uart_clock_opad"/><macrocell id="FB31_MC2" pin="FB31_MC2_PINK3"/><macrocell id="FB31_MC3" pin="FB31_MC3_PINK1"/><macrocell id="FB31_MC4" pin="FB31_MC4_PINJ4"/><macrocell id="FB31_MC5"/><macrocell id="FB31_MC6"/><macrocell id="FB31_MC7"/><macrocell id="FB31_MC8"/><macrocell id="FB31_MC9"/><macrocell id="FB31_MC10"/><macrocell id="FB31_MC11"/><macrocell id="FB31_MC12"/><macrocell id="FB31_MC13"/><macrocell id="FB31_MC14" pin="FB31_MC14_PINJ2"/><macrocell id="FB31_MC15" pin="FB31_MC15_PINJ5"/><macrocell id="FB31_MC16" pin="FB31_MC16_PINH2"/><PAL/><equation id="uart_clock_opad" regUse="T"><d2><eq_pterm ptindx="VCC"/></d2><clk><fastsig signal="uart_osc_ipad"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB32" pinUse="7"><macrocell id="FB32_MC1" pin="FB32_MC1_PINR7"/><macrocell id="FB32_MC2" pin="FB32_MC2_PINP7"/><macrocell id="FB32_MC3" pin="FB32_MC3_PINT8"/><macrocell id="FB32_MC4" pin="FB32_MC4_PINN8"/><macrocell id="FB32_MC5"/><macrocell id="FB32_MC6"/><macrocell id="FB32_MC7"/><macrocell id="FB32_MC8"/><macrocell id="FB32_MC9"/><macrocell id="FB32_MC10"/><macrocell id="FB32_MC11"/><macrocell id="FB32_MC12"/><macrocell id="FB32_MC13"/><macrocell id="FB32_MC14" pin="FB32_MC14_PINR8"/><macrocell id="FB32_MC15" pin="FB32_MC15_PINP8"/><macrocell id="FB32_MC16" pin="FB32_MC16_PINT9"/><PAL/></fblock><vcc/><gnd/><compOpts isp="ON" loc="ON" part="xcr3512xl-10-FT256" prld="LOW" slew="SLOW" inreg="ON" mlopt="ON" nouct="OFF" fbnand="OFF" inputs="32" keepio="OFF" pterms="28" unused="PULLUP" exhaust="OFF" wysiwyg="OFF" blkfanin="38" ignorets="OFF" optimize="DENSITY" terminate="FLOAT"/><specSig value="cpu_address_in_ipads&lt;0&gt;" signal="cpu_address_in_ipads0_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;10&gt;" signal="cpu_address_in_ipads10_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;1&gt;" signal="cpu_address_in_ipads1_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;2&gt;" signal="cpu_address_in_ipads2_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;3&gt;" signal="cpu_address_in_ipads3_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;4&gt;" signal="cpu_address_in_ipads4_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;5&gt;" signal="cpu_address_in_ipads5_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;6&gt;" signal="cpu_address_in_ipads6_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;7&gt;" signal="cpu_address_in_ipads7_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;8&gt;" signal="cpu_address_in_ipads8_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;9&gt;" signal="cpu_address_in_ipads9_SPECSIG"/><specSig value="cpu_data_iopads&lt;0&gt;.PIN" signal="cpu_data_iopads0PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;10&gt;.PIN" signal="cpu_data_iopads10PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;11&gt;.PIN" signal="cpu_data_iopads11PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;12&gt;.PIN" signal="cpu_data_iopads12PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;13&gt;.PIN" signal="cpu_data_iopads13PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;14&gt;.PIN" signal="cpu_data_iopads14PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;15&gt;.PIN" signal="cpu_data_iopads15PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;1&gt;.PIN" signal="cpu_data_iopads1PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;2&gt;.PIN" signal="cpu_data_iopads2PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;3&gt;.PIN" signal="cpu_data_iopads3PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;4&gt;.PIN" signal="cpu_data_iopads4PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;5&gt;.PIN" signal="cpu_data_iopads5PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;6&gt;.PIN" signal="cpu_data_iopads6PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;7&gt;.PIN" signal="cpu_data_iopads7PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;8&gt;.PIN" signal="cpu_data_iopads8PIN_SPECSIG"/><specSig value="cpu_data_iopads&lt;9&gt;.PIN" signal="cpu_data_iopads9PIN_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;11&gt;" signal="cpu_address_in_ipads11_SPECSIG"/><specSig value="cpu_address_in_ipads&lt;12&gt;" signal="cpu_address_in_ipads12_SPECSIG"/><specSig value="cf_data_iopads&lt;0&gt;.PIN" signal="cf_data_iopads0PIN_SPECSIG"/><specSig value="uart_data_iopads&lt;0&gt;.PIN" signal="uart_data_iopads0PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;10&gt;.PIN" signal="cf_data_iopads10PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;11&gt;.PIN" signal="cf_data_iopads11PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;12&gt;.PIN" signal="cf_data_iopads12PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;13&gt;.PIN" signal="cf_data_iopads13PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;14&gt;.PIN" signal="cf_data_iopads14PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;15&gt;.PIN" signal="cf_data_iopads15PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;1&gt;.PIN" signal="cf_data_iopads1PIN_SPECSIG"/><specSig value="uart_data_iopads&lt;1&gt;.PIN" signal="uart_data_iopads1PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;2&gt;.PIN" signal="cf_data_iopads2PIN_SPECSIG"/><specSig value="uart_data_iopads&lt;2&gt;.PIN" signal="uart_data_iopads2PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;3&gt;.PIN" signal="cf_data_iopads3PIN_SPECSIG"/><specSig value="uart_data_iopads&lt;3&gt;.PIN" signal="uart_data_iopads3PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;4&gt;.PIN" signal="cf_data_iopads4PIN_SPECSIG"/><specSig value="uart_data_iopads&lt;4&gt;.PIN" signal="uart_data_iopads4PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;5&gt;.PIN" signal="cf_data_iopads5PIN_SPECSIG"/><specSig value="uart_data_iopads&lt;5&gt;.PIN" signal="uart_data_iopads5PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;6&gt;.PIN" signal="cf_data_iopads6PIN_SPECSIG"/><specSig value="uart_data_iopads&lt;6&gt;.PIN" signal="uart_data_iopads6PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;7&gt;.PIN" signal="cf_data_iopads7PIN_SPECSIG"/><specSig value="uart_data_iopads&lt;7&gt;.PIN" signal="uart_data_iopads7PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;8&gt;.PIN" signal="cf_data_iopads8PIN_SPECSIG"/><specSig value="cf_data_iopads&lt;9&gt;.PIN" signal="cf_data_iopads9PIN_SPECSIG"/><specSig value="I/O" signal="IO_SPECSIG"/><specSig value="cpu_data_iopads&lt;2&gt;" signal="cpu_data_iopads2_SPECSIG"/><specSig value="cpu_data_iopads&lt;3&gt;" signal="cpu_data_iopads3_SPECSIG"/><specSig value="cpu_data_iopads&lt;4&gt;" signal="cpu_data_iopads4_SPECSIG"/><specSig value="cpu_data_iopads&lt;5&gt;" signal="cpu_data_iopads5_SPECSIG"/><specSig value="cpu_data_iopads&lt;6&gt;" signal="cpu_data_iopads6_SPECSIG"/><specSig value="cpu_data_iopads&lt;7&gt;" signal="cpu_data_iopads7_SPECSIG"/><specSig value="cpu_data_iopads&lt;9&gt;" signal="cpu_data_iopads9_SPECSIG"/><specSig value="cpu_data_iopads&lt;1&gt;" signal="cpu_data_iopads1_SPECSIG"/><specSig value="cf_address_opads&lt;3&gt;" signal="cf_address_opads3_SPECSIG"/><specSig value="cf_address_opads&lt;2&gt;" signal="cf_address_opads2_SPECSIG"/><specSig value="cf_address_opads&lt;1&gt;" signal="cf_address_opads1_SPECSIG"/><specSig value="cf_address_opads&lt;10&gt;" signal="cf_address_opads10_SPECSIG"/><specSig value="cf_address_opads&lt;0&gt;" signal="cf_address_opads0_SPECSIG"/><specSig value="uart_address_opads&lt;0&gt;" signal="uart_address_opads0_SPECSIG"/><specSig value="cf_data_iopads&lt;0&gt;" signal="cf_data_iopads0_SPECSIG"/><specSig value="cf_data_iopads&lt;11&gt;" signal="cf_data_iopads11_SPECSIG"/><specSig value="cf_data_iopads&lt;12&gt;" signal="cf_data_iopads12_SPECSIG"/><specSig value="cf_data_iopads&lt;10&gt;" signal="cf_data_iopads10_SPECSIG"/><specSig value="cf_data_iopads&lt;13&gt;" signal="cf_data_iopads13_SPECSIG"/><specSig value="uart_address_opads&lt;4&gt;" signal="uart_address_opads4_SPECSIG"/><specSig value="cf_data_iopads&lt;14&gt;" signal="cf_data_iopads14_SPECSIG"/><specSig value="cf_data_iopads&lt;15&gt;" signal="cf_data_iopads15_SPECSIG"/><specSig value="cpu_data_iopads&lt;0&gt;" signal="cpu_data_iopads0_SPECSIG"/><specSig value="cpu_data_iopads&lt;10&gt;" signal="cpu_data_iopads10_SPECSIG"/><specSig value="cpu_data_iopads&lt;11&gt;" signal="cpu_data_iopads11_SPECSIG"/><specSig value="cpu_data_iopads&lt;12&gt;" signal="cpu_data_iopads12_SPECSIG"/><specSig value="uart_address_opads&lt;6&gt;" signal="uart_address_opads6_SPECSIG"/><specSig value="cf_data_iopads&lt;7&gt;" signal="cf_data_iopads7_SPECSIG"/><specSig value="uart_address_opads&lt;7&gt;" signal="uart_address_opads7_SPECSIG"/><specSig value="cf_data_iopads&lt;8&gt;" signal="cf_data_iopads8_SPECSIG"/><specSig value="cf_data_iopads&lt;9&gt;" signal="cf_data_iopads9_SPECSIG"/><specSig value="cf_data_iopads&lt;4&gt;" signal="cf_data_iopads4_SPECSIG"/><specSig value="uart_address_opads&lt;3&gt;" signal="uart_address_opads3_SPECSIG"/><specSig value="cf_data_iopads&lt;6&gt;" signal="cf_data_iopads6_SPECSIG"/><specSig value="uart_address_opads&lt;5&gt;" signal="uart_address_opads5_SPECSIG"/><specSig value="cf_data_iopads&lt;5&gt;" signal="cf_data_iopads5_SPECSIG"/><specSig value="cf_address_opads&lt;9&gt;" signal="cf_address_opads9_SPECSIG"/><specSig value="cf_data_iopads&lt;3&gt;" signal="cf_data_iopads3_SPECSIG"/><specSig value="cf_data_iopads&lt;2&gt;" signal="cf_data_iopads2_SPECSIG"/><specSig value="uart_address_opads&lt;2&gt;" signal="uart_address_opads2_SPECSIG"/><specSig value="cf_address_opads&lt;8&gt;" signal="cf_address_opads8_SPECSIG"/><specSig value="cf_address_opads&lt;7&gt;" signal="cf_address_opads7_SPECSIG"/><specSig value="cf_address_opads&lt;6&gt;" signal="cf_address_opads6_SPECSIG"/><specSig value="cf_address_opads&lt;5&gt;" signal="cf_address_opads5_SPECSIG"/><specSig value="cf_address_opads&lt;4&gt;" signal="cf_address_opads4_SPECSIG"/><specSig value="cf_data_iopads&lt;1&gt;" signal="cf_data_iopads1_SPECSIG"/><specSig value="uart_address_opads&lt;1&gt;" signal="uart_address_opads1_SPECSIG"/><specSig value="cpu_data_iopads&lt;8&gt;" signal="cpu_data_iopads8_SPECSIG"/><specSig value="cpu_data_iopads&lt;15&gt;" signal="cpu_data_iopads15_SPECSIG"/><specSig value="cpu_data_iopads&lt;14&gt;" signal="cpu_data_iopads14_SPECSIG"/><specSig value="cpu_data_iopads&lt;13&gt;" signal="cpu_data_iopads13_SPECSIG"/><specSig value="test_opads&lt;13&gt;" signal="test_opads13_SPECSIG"/><specSig value="test_opads&lt;14&gt;" signal="test_opads14_SPECSIG"/><specSig value="test_opads&lt;11&gt;" signal="test_opads11_SPECSIG"/><specSig value="test_opads&lt;15&gt;" signal="test_opads15_SPECSIG"/><specSig value="test_opads&lt;9&gt;" signal="test_opads9_SPECSIG"/><specSig value="test_opads&lt;12&gt;" signal="test_opads12_SPECSIG"/><specSig value="test_opads&lt;5&gt;" signal="test_opads5_SPECSIG"/><specSig value="test_opads&lt;10&gt;" signal="test_opads10_SPECSIG"/><specSig value="test_opads&lt;8&gt;" signal="test_opads8_SPECSIG"/><specSig value="test_opads&lt;4&gt;" signal="test_opads4_SPECSIG"/><specSig value="test_opads&lt;7&gt;" signal="test_opads7_SPECSIG"/><specSig value="uart_data_iopads&lt;7&gt;" signal="uart_data_iopads7_SPECSIG"/><specSig value="uart_data_iopads&lt;6&gt;" signal="uart_data_iopads6_SPECSIG"/><specSig value="uart_data_iopads&lt;5&gt;" signal="uart_data_iopads5_SPECSIG"/><specSig value="uart_data_iopads&lt;4&gt;" signal="uart_data_iopads4_SPECSIG"/><specSig value="uart_data_iopads&lt;3&gt;" signal="uart_data_iopads3_SPECSIG"/><specSig value="test_opads&lt;2&gt;" signal="test_opads2_SPECSIG"/><specSig value="test_opads&lt;6&gt;" signal="test_opads6_SPECSIG"/><specSig value="test_opads&lt;1&gt;" signal="test_opads1_SPECSIG"/><specSig value="test_opads&lt;3&gt;" signal="test_opads3_SPECSIG"/><specSig value="test_opads&lt;0&gt;" signal="test_opads0_SPECSIG"/><specSig value="uart_data_iopads&lt;2&gt;" signal="uart_data_iopads2_SPECSIG"/><specSig value="uart_data_iopads&lt;1&gt;" signal="uart_data_iopads1_SPECSIG"/><specSig value="uart_data_iopads&lt;0&gt;" signal="uart_data_iopads0_SPECSIG"/></document>
