SetActiveLib -work
comp -include "$DSN\src\globals.vhd" 
comp -include "$DSN\src\falling_edge_detector.vhd" 
comp -include "$DSN\src\dual_rank_sync.vhd" 
comp -include "$DSN\src\reset_sync.vhd" 
comp -include "$DSN\src\registers.vhd" 
comp -include "$DSN\src\biosa.bde" 
comp -include "$DSN\src\TestBench\biosa_TB.vhd" 
asim TESTBENCH_FOR_biosa 
wave 
wave -noreg async_reset_n
wave -noreg clock
wave -noreg cs_n
wave -noreg rd_n
wave -noreg wr_n
wave -noreg address_in
wave -noreg data_in
wave -noreg data_out
# The following lines can be used for timing simulation
# acom <backannotated_vhdl_file_name>
# comp -include "$DSN\src\TestBench\biosa_TB_tim_cfg.vhd" 
# asim TIMING_FOR_biosa