library ieee;
use ieee.std_logic_1164.all;

entity dual_rank_synchronizer is
  port (
    clock      	: in  std_logic;
    reset 		: in  std_logic;
    unsynced_in : in  std_logic;
    synced_out  : out std_logic
  );
end entity dual_rank_synchronizer;

architecture synthesis of dual_rank_synchronizer is
  signal rank_1 : std_logic;
  signal rank_2 : std_logic;
begin
  synchronizers : process (clock)
  begin
    if rising_edge(clock) then
      if (reset = '1') then
        rank_1 <= '0';
        rank_2 <= '0';
      else
        rank_1 <= unsynced_in;
        rank_2 <= rank_1;
      end if;
    end if;
  end process synchronizers;
  synced_out   <= rank_2;
end synthesis;