library ieee;
use ieee.std_logic_1164.all;

entity falling_edge_detector is
  port (
    clock		: in  std_logic;
    reset		: in  std_logic;
    candidate	: in  std_logic;
    detected	: out std_logic
    );
end falling_edge_detector;

architecture synthesis of falling_edge_detector is
  signal candidate_delayed : std_logic;
begin
  ff : process(clock)
  begin
    if rising_edge(clock) then
      if reset = '1' then
        candidate_delayed <= '0';
      else
        candidate_delayed <= candidate;
	  end if; 
	end if;
  end process ff;
  detected <= candidate_delayed and not candidate;
end architecture synthesis;