-------------------------------------------------------------------------------
--
-- Title       : No Title
-- Design      : 
-- Author      : Wayne Radochonski
-- Company     : Home
--
-------------------------------------------------------------------------------
--
-- File        : c:\My_Designs\BIOSA\flasher\flasher\compile\flash_control_fsml.vhd
-- Generated   : 09/21/06 13:22:23
-- From        : c:\My_Designs\BIOSA\flasher\flasher\src\flash_control_fsml.asf
-- By          : FSM2VHDL ver. 5.0.0.9
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity flash_control_fsm is 
	port (
		clock: in STD_LOGIC;
		end_of_flashlet: in STD_LOGIC;
		full: in STD_LOGIC;
		reset: in STD_LOGIC;
		go: out STD_LOGIC;
		load_count: out STD_LOGIC);
end flash_control_fsm;

architecture synthesis of flash_control_fsm is

-- GRAY ENCODED state machine: flash_control_fsm
attribute enum_encoding: string;
type flash_control_fsm_type is (
    IDLE, FLASHLET, LOAD
);
attribute enum_encoding of flash_control_fsm_type: type is
	"00 " &		-- IDLE
	"01 " &		-- FLASHLET
	"11" ; 		-- LOAD

signal flash_control_fsm: flash_control_fsm_type;

begin

-- concurrent signals assignments

-- Diagram ACTION

----------------------------------------------------------------------
-- Machine: flash_control_fsm
----------------------------------------------------------------------
flash_control_fsm_machine: process (clock)
begin
	if clock'event and clock = '1' then
		if reset = '1' then	
			flash_control_fsm <= IDLE;
			-- Set default values for outputs, signals and variables
			-- ...
			load_count <= '0';
			go <= '0';
		else
			-- Set default values for outputs, signals and variables
			-- ...
			case flash_control_fsm is
				when IDLE =>
					load_count <= '0';
					go <= '0';
					if full = '1' then	
						flash_control_fsm <= LOAD;
					end if;
				when FLASHLET =>
					load_count <= '0';
					go <= '1';
					if full = '0' and end_of_flashlet = '1' then	
						flash_control_fsm <= IDLE;
						load_count <= '0';
						go <= '0';
					elsif full = '1' and end_of_flashlet = '1' then	
						flash_control_fsm <= FLASHLET;
						load_count <= '1';
						go <= '1';
					end if;
				when LOAD =>
					load_count <= '1';
					go <= '0';
					flash_control_fsm <= FLASHLET;
				when others =>
					null;
			end case;
		end if;
	end if;
end process;

end synthesis;