library ieee;
use ieee.std_logic_1164.all;

entity pwm is
	 port(
		 clock 		: in std_logic;
		 reset 		: in std_logic;		
		 load		: in std_logic;	  
		 enable		: in std_logic;
		 count 		: in std_logic_vector(15 downto 0);
		 on_limit 	: in std_logic_vector(15 downto 0);
		 off_limit 	: in std_logic_vector(15 downto 0);
		 pulse 		: out std_logic
	 );
end pwm;

architecture synthesis of pwm is
	component jk_ff is
		port (
		 clock 	: in 	std_logic;
		 reset 	: in 	std_logic;	
		 enable	: in	std_logic;
		 j 		: in 	std_logic;
		 k 		: in 	std_logic;
		 q_out 	: out 	std_logic
		);
	end component jk_ff;      

	signal set					: std_logic;
	signal clear				: std_logic;	 
	signal on_limit_register	: std_logic_vector(15 downto 0);
	signal off_limit_register	: std_logic_vector(15 downto 0);	   
	signal flash				: std_logic;	  
	
begin
	jk_ff_1 : jk_ff
		port map (
		  clock     	=> clock,
		  reset 		=> reset,
		  enable		=> enable,
		  j 	     	=> set,
		  k      		=> clear,
		  q_out     	=> flash
		);
		
	on_limit_reg : process( clock )
	begin		  
		if rising_edge( clock ) then	  
			if reset = '1' then	
				on_limit_register <= (others => '0');
			elsif load = '1' then
				on_limit_register <= on_limit;
			end if;
		end if;
	end process	on_limit_reg;	   
	
	off_limit_reg : process( clock )
	begin		  
		if rising_edge( clock ) then	  
			if reset = '1' then	
				off_limit_register <= (others => '0');
			elsif load = '1' then
				off_limit_register <= off_limit;
			end if;
		end if;
	end process	off_limit_reg;

	set   <= '1' when count = on_limit_register  else '0';
	clear <= '1' when count = off_limit_register else '0';	  
	pulse <= flash;

end synthesis;