library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity reset_synchronizer is
	 port(
		 clock			: in  std_logic;
		 async_reset_n	: in  std_logic;
		 sync_reset		: out std_logic
	     );
end reset_synchronizer;

architecture synthesis of reset_synchronizer is	 
signal reset_ff 	: std_logic;	
signal async_reset	: std_logic;
begin				  
	async_reset <= not async_reset_n;
	process (clock, async_reset)
	begin		 
		if async_reset = '1' then
			reset_ff <= '1';
			sync_reset <= '1';
		elsif rising_edge(clock) then	
			reset_ff <= '0';
			sync_reset <= reset_ff;
		end if;
	end process	;
end synthesis;