; bdiGDB configuration for Innovator 1610 ; --------------------------------------- ; Because the RESET signal is not routed to the Multi-ICE ; connector, it is not possible for the BDI to force a reset. ; Also it is not possible to stop the target immediatelly at ; the reset vector. To get control of the board, power-cycle it ; or press the reset button on the Processor Module and then ; enter reset at the BDI2000 Telnet interface. ; ; [INIT] ; WREG CPSR 0x000000d3 ;set superviser mode WGPR 15 0x00000000 ;set PC = 0 WCP15 0x0001 0x00050078 ;CP15 Control : disable caches ; WM16 0xfffecf00 0x0010 ;PLL lock ; WM16 0xfffece08 0x4 ;Enable ARM peripheral clock WM16 0xfffece14 0x1 ;Release OMAP CLKM reset ; WM16 0xFFFEC808 0x00F5 ;Disable ARM9 Watchdog Timer WM16 0xFFFEC808 0x00A0 ; ; ; Configure Memory Interface EMIFS for default processor pll freq @12MHz WM32 0xfffecc14 0x00003339 ;EMIFS CS1 configuration WM32 0xfffecc18 0x00003339 ;EMIFS CS2 configuration WM32 0xfffecc1c 0x88011131 ;EMIFS CS3 configuration WM32 0xfffecc80 0x00000007 ;Set operations register WM32 0xfffecc20 0x0000bbf4 ;EMIFF CS4 configuration - DDR ; ; Initialize Mobile DDR SDRAM WM32 0xfffecc84 0x00000007 ;Set CKE high via manual command register DELAY 10 ;Delay for min. 200 us WM32 0xfffecc84 0x00000001 ;Precharge all banks via manual command register WM32 0xfffecc84 0x00000002 ;Issue 2+ AUTOREFRESH commands WM32 0xfffecc84 0x00000002 WM32 0xfffecc70 0x00000033 ;MRS initialization - DDR ; WBST (9): write burst - must be 0 ; CASL (6:4): CAS Latency - must be 2 ; S/I (3): Serial - must be 0 ; PGBL (2:0): Burst length - set to burst of 8 WM32 0xfffecc78 0x00000000 ;EMRS1 refresh all banks WM32 0xfffeccc0 0x00800002 ;DDR DDL registers URD WM32 0xfffecccc 0x00800002 ;DDR DDL registers LRD WM32 0xfffecc64 0x03F00002 ;DDR DDL registers WRD; ; WM16 0xfffece10 0x0002 ;Release the DSP from reset ; ;Setup MMU and enable caches, Translation table at 0x10004000 ; 0x00000000 -> 0x10000000 SDRAM cached ; 0x10000000 -> 0x10000000 SDRAM uncached ; 0xfff00000 -> 0xfff00000 MMIO uncached ; WCP15 2 0x10004000 ;set Translation Base Address WCP15 3 0xFFFFFFFF ;set Domain Access Control WM32 0x10004000 0x10000C1E ;MMU: 0x00000000, cacheable, bufferable WM32 0x10004004 0x10100C1E ;MMU: 0x00100000, cacheable, bufferable WM32 0x10004008 0x10200C1E ;MMU: 0x00200000, cacheable, bufferable WM32 0x1000400C 0x10300C1E ;MMU: 0x00300000, cacheable, bufferable WM32 0x10004010 0x10400C1E ;MMU: 0x00400000, cacheable, bufferable WM32 0x10004014 0x10500C1E ;MMU: 0x00500000, cacheable, bufferable WM32 0x10004018 0x10600C1E ;MMU: 0x00600000, cacheable, bufferable WM32 0x1000401C 0x10700C1E ;MMU: 0x00700000, cacheable, bufferable WM32 0x10004020 0x10800C1E ;MMU: 0x00800000, cacheable, bufferable WM32 0x10004024 0x10900C1E ;MMU: 0x00900000, cacheable, bufferable WM32 0x10004028 0x10A00C1E ;MMU: 0x00A00000, cacheable, bufferable WM32 0x1000402C 0x10B00C1E ;MMU: 0x00B00000, cacheable, bufferable WM32 0x10004030 0x10C00C1E ;MMU: 0x00C00000, cacheable, bufferable WM32 0x10004034 0x10D00C1E ;MMU: 0x00D00000, cacheable, bufferable WM32 0x10004038 0x10E00C1E ;MMU: 0x00E00000, cacheable, bufferable WM32 0x1000403C 0x10F00C1E ;MMU: 0x00F00000, cacheable, bufferable ; WM32 0x10004400 0x10000C12 ;MMU: 0x10000000, non cacheable, non bufferable WM32 0x10004404 0x10100C12 ;MMU: 0x10100000, non cacheable, non bufferable WM32 0x10004408 0x10200C12 ;MMU: 0x10200000, non cacheable, non bufferable WM32 0x1000440C 0x10300C12 ;MMU: 0x10300000, non cacheable, non bufferable WM32 0x10004410 0x10400C12 ;MMU: 0x10400000, non cacheable, non bufferable WM32 0x10004414 0x10500C12 ;MMU: 0x10500000, non cacheable, non bufferable WM32 0x10004418 0x10600C12 ;MMU: 0x10600000, non cacheable, non bufferable WM32 0x1000441C 0x10700C12 ;MMU: 0x10700000, non cacheable, non bufferable WM32 0x10004420 0x10800C12 ;MMU: 0x10800000, non cacheable, non bufferable WM32 0x10004424 0x10900C12 ;MMU: 0x10900000, non cacheable, non bufferable WM32 0x10004428 0x10A00C12 ;MMU: 0x10A00000, non cacheable, non bufferable WM32 0x1000442C 0x10B00C12 ;MMU: 0x10B00000, non cacheable, non bufferable WM32 0x10004430 0x10C00C12 ;MMU: 0x10C00000, non cacheable, non bufferable WM32 0x10004434 0x10D00C12 ;MMU: 0x10D00000, non cacheable, non bufferable WM32 0x10004438 0x10E00C12 ;MMU: 0x10E00000, non cacheable, non bufferable WM32 0x1000443C 0x10F00C12 ;MMU: 0x10F00000, non cacheable, non bufferable ; WM32 0x10007FFC 0xFFF00C12 ;MMU: 0xFFF00000, non cacheable, non bufferable ; WCP15 1 0x0005107D ;enable MMU, Caches and Write Buffer ; MMAP 0x00000000 0x00FFFFFF ;enable access to cached SDRAM MMAP 0x10000000 0x10FFFFFF ;enable access to uncached SDRAM MMAP 0xFFFB0000 0xFFFEFFFF ;enable access to peripheral ; WGPR 11 0x00000020 ;set frame pointer to free RAM WM32 0x00000020 0x00000028 ;dummy stack frame ; [TARGET] CPUTYPE ARM926E CLOCK 0 4 ;JTAG clock : start with 1 MHz then use adaptive ; to use adaptive clocking you need the correct ; target cable and you have to use the JTAG adapter ; board on the Innovator Break-out-board. ;CLOCK 4 ;JTAG clock : without adaptive clocking cable SCANPRED 1 8 ;JTAG devices connected before this core SCANSUCC 1 38 ;JTAG devices connected after this core TRST OPENDRAIN ;TRST driver type (OPENDRAIN | PUSHPULL) RESET NONE ;NONE | HARD (ms) ENDIAN LITTLE ;memory model (LITTLE | BIG) VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset ;BREAKMODE HARD ;SOFT or HARD, ARM / Thumb break code BREAKMODE SOFT 0xDFFFDFFF ;SOFT or HARD, ARM / Thumb break code [HOST] IP 151.120.25.119 FILE E:\cygwin\home\bdidemo\arm\bin_sem0.exe ; for download test only FORMAT BIN 0x00008000 ;don't overwrite translation table LOAD MANUAL ;load code MANUAL or AUTO after reset [FLASH] [REGS] FILE E:\cygwin\home\bdidemo\arm\reg926e.def