; bdiGDB configuration file for AT91SAM7S-EK board
; ------------------------------------------------
;
[INIT]
WM32    0xFFFFFD44  0x00008000  ;Disable watchdog
WM32    0xFFFFFD08  0xA5000001  ;Enable user reset
;WM32    0xFFFFFF00  0x00000001  ;Cancel reset remapping
;
; Setup PLL
WM32    0xFFFFFC20  0x00000601  ;CKGR_MOR : Enabling the Main Oscillator
DELAY   20
WM32    0xFFFFFC2C  0x10480a0e  ;CKGR_PLLR: 96.1MHz (DIV=14,MUL=72+1)
DELAY   20
WM32    0xFFFFFC30  0x00000007  ;PMC_MCKR : MCK = PLL / 2 = 48MHz
DELAY   20
;
; Setup Internal Flash for 48MHz Master Clock
WM32    0xFFFFFF60  0x00300100  ;MC_FMR: Flash mode (FWS=1,FMCN=48)
;

[TARGET]
CPUTYPE     ARM7TDMI
CLOCK       1 10        ;JTAG clock (0=Adaptive, 1=16MHz, 2=8MHz, 3=4MHz)
RESET       HARD 300    ;Assert reset line for 300 ms
BREAKMODE   HARD        ;SOFT or HARD, ARM / Thumb break code
STEPMODE    HWBP

[HOST]
IP          151.120.25.119
PROMPT      SAM7S>       ;new Telnet prompt

[FLASH]
CHIPTYPE    AT91SAM7S   ;Don't forget to set MC_FMR[FMCN] and MC_FMR[FWS]
CHIPSIZE    0x10000     ;The size of one flash chip in bytes
BUSWIDTH    32          ;The width of the flash memory bus in bits (8 | 16 | 32)
;FILE        E:\temp\dump16k.bin
;FORMAT      BIN 0x00104000

FILE        E:\cygwin\home\bdidemo\at91\sam7s.bin
FORMAT      BIN 0x00100000


[REGS]
FILE	E:\cygwin\home\bdidemo\at91\regSAM7S.def