; bdiGDB configuration for TI925T (OMAP1510DC) EVM
; ------------------------------------------------
;
[INIT]
;
WREG    CPSR        0x000000d3  ;set superviser mode
WGPR    15          0x00000000  ;set PC = 0
WCP15   1           0x00000070  ;CP15 Control : disable caches
;
WM16    0xFFFEC808  0x00F5      ;Disable Watchdog Timer
WM16    0xFFFEC808  0x00A0      ;
;
WM32    0xFFFECC10  0x00212090  ;EMIFS CS0 configuration
WM32    0xFFFECC14  0x00001149  ;EMIFS CS1 configuration
WM32    0xFFFECC18  0x00004158  ;EMIFS CS2 configuration
WM32    0xFFFECC1C  0x0000fffb  ;EMIFS CS3 configuration
WM32    0xFFFECC20  0x0000a3f4  ;EMIFF SDRAM configuration
WM32    0xFFFECC24  0x00000027  ;EMIFF SDRAM MRS
;
WM16    0xFFFECE10  0x0002      ;release Megastar3 reset
;
;Setup MMU and enable cache, Translation table at 0x10004000
;Map SDRAM to 0x00000000
;
WCP15   2           0x10004000  ;set Translation Base Address
WCP15   3           0xFFFFFFFF  ;set Domain Access Control
WM32    0x10004000  0x10000C1E  ;MMU: 0x00000000, cacheable, bufferable
WM32    0x10004004  0x10100C1E  ;MMU: 0x00100000, cacheable, bufferable
WM32    0x10004008  0x10200C1E  ;MMU: 0x00200000, cacheable, bufferable
WM32    0x1000400C  0x10300C1E  ;MMU: 0x00300000, cacheable, bufferable
WM32    0x10004010  0x10400C1E  ;MMU: 0x00400000, cacheable, bufferable
WM32    0x10004014  0x10500C1E  ;MMU: 0x00500000, cacheable, bufferable
WM32    0x10004018  0x10600C1E  ;MMU: 0x00600000, cacheable, bufferable
WM32    0x1000401C  0x10700C1E  ;MMU: 0x00700000, cacheable, bufferable
WM32    0x10004020  0x10800C1E  ;MMU: 0x00800000, cacheable, bufferable
WM32    0x10004024  0x10900C1E  ;MMU: 0x00900000, cacheable, bufferable
WM32    0x10004028  0x10A00C1E  ;MMU: 0x00A00000, cacheable, bufferable
WM32    0x1000402C  0x10B00C1E  ;MMU: 0x00B00000, cacheable, bufferable
WM32    0x10004030  0x10C00C1E  ;MMU: 0x00C00000, cacheable, bufferable
WM32    0x10004034  0x10D00C1E  ;MMU: 0x00D00000, cacheable, bufferable
WM32    0x10004038  0x10E00C1E  ;MMU: 0x00E00000, cacheable, bufferable
WM32    0x1000403C  0x10F00C1E  ;MMU: 0x00F00000, cacheable, bufferable
;
WM32    0x10007FFC  0xFFF00C12  ;MMU: 0xFFF00000, non cacheable, non bufferable
;
WCP15   1           0x0000107D  ;enable MMU, Caches and Write Buffer
;
MMAP    0x00000000  0x00FFFFFF  ;enable access to mapped SDRAM
MMAP    0xFFFB0000  0xFFFEFFFF  ;enable access to peripheral
;
WGPR    11          0x00000020  ;set frame pointer to free RAM
WM32    0x00000020  0x00000028  ;dummy stack frame
;

[TARGET]
CPUTYPE     TI925T
CLOCK       1                   ;JTAG clock (0=Adaptive, 1=8MHz, 2=4MHz, 3=2MHz)
SCANPRED    1 8                 ;JTAG devices connected before this core
SCANSUCC    1 38                ;JTAG devices connected after this core
TRST        PUSHPULL            ;TRST driver type (OPENDRAIN | PUSHPULL)
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
VECTOR      CATCH 0x1f          ;catch D_Abort, P_Abort, SWI, Undef and Reset
BREAKMODE   SOFT 0xDFFFDFFF     ;SOFT or HARD, ARM / Thumb break code
;BREAKMODE   HARD


[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\bdidemo\arm\bin_sem0.exe ; for download test only
FORMAT      BIN  0x00000000
LOAD        MANUAL      ;load code MANUAL or AUTO after reset

[FLASH]

[REGS]
FILE	E:\cygwin\home\bdidemo\arm\reg925t.def