; bdiGDB configuration for TI925T (OMAP1510DC) EVM
; ------------------------------------------------
;
[INIT]
;
WREG    CPSR        0x000000d3  ;set superviser mode
WGPR    15          0x00000000  ;set PC = 0
WCP15   0x31        0x00000070  ;CP15 Control : disable caches
;
WM16    0xFFFEC808  0x00F5      ;Disable Watchdog Timer
WM16    0xFFFEC808  0x00A0      ;
;
WM32    0xFFFECC10  0x00212090  ;EMIFS CS0 configuration
WM32    0xFFFECC14  0x00001149  ;EMIFS CS1 configuration
WM32    0xFFFECC18  0x00004158  ;EMIFS CS2 configuration
WM32    0xFFFECC1C  0x0000fffb  ;EMIFS CS3 configuration
WM32    0xFFFECC20  0x0000a3f4  ;EMIFF SDRAM configuration
WM32    0xFFFECC24  0x00000027  ;EMIFF SDRAM MRS
;
WM16    0xFFFECE10  0x0002      ;release Megastar3 reset
;
MMAP    0x00000000  0x01FFFFFF  ;enable access to CS0
MMAP    0x04000000  0x05FFFFFF  ;enable access to CS1
MMAP    0x08000000  0x09FFFFFF  ;enable access to CS2
MMAP    0x0C000000  0x0DFFFFFF  ;enable access to CS3
MMAP    0x10000000  0x1FFFFFFF  ;enable access to SDRAM
MMAP    0x20000000  0x2007FFFF  ;enable access to internal RAM
MMAP    0xFFFB0000  0xFFFEFFFF  ;enable access to peripheral
;

[TARGET]
CPUTYPE     TI925T
CLOCK       1                   ;JTAG clock (0=Adaptive, 1=8MHz, 2=4MHz, 3=2MHz)
SCANPRED    1 8                 ;JTAG devices connected before this core
SCANSUCC    1 38                ;JTAG devices connected after this core
TRST        PUSHPULL            ;TRST driver type (OPENDRAIN | PUSHPULL)
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
VECTOR      CATCH 0x1f          ;catch D_Abort, P_Abort, SWI, Undef and Reset
BREAKMODE   SOFT 0xDFFFDFFF     ;SOFT or HARD, ARM / Thumb break code


[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\bdidemo\arm\bin_sem0.exe ; for download test only
FORMAT      BIN  0x10000000
LOAD        MANUAL      ;load code MANUAL or AUTO after reset

[FLASH]

[REGS]
FILE	E:\cygwin\home\bdidemo\arm\reg925t.def