------------------------------------------------------------------------------- -- -- Title : BIOSA LED Flash Control Logic -- Design : flasher -- Author : Wayne Radochonski -- Company : Home -- ------------------------------------------------------------------------------- -- -- File : c:\My_Designs\BIOSA\flasher\flasher\compile\biosa.vhd -- Generated : Fri Sep 29 08:42:57 2006 -- From : c:\My_Designs\BIOSA\flasher\flasher\src\biosa.bde -- By : Bde2Vhdl ver. 2.6 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- -- Design unit header -- library IEEE; use IEEE.std_logic_1164.all; -- other libraries declarations -- synopsys translate_off library APA; use IEEE.VITAL_Timing.all; -- synopsys translate_on entity biosa is port( async_reset_n_ipad : in STD_LOGIC; clock_ipad : in STD_LOGIC; cs_n_ipad : in STD_LOGIC; rd_n_ipad : in STD_LOGIC; wr_0_n_ipad : in std_logic; address_ipads : in STD_LOGIC_VECTOR(5 downto 2); flash_opad : out std_logic; interrupt_n_opad : out std_logic; sample_adc_opad : out std_logic; stall_n_opad : out std_logic; data_iopads : inout STD_LOGIC_VECTOR(15 downto 0) ); end biosa; architecture biosa of biosa is ---- Component declarations ----- component bus_bidirectional_buffer port ( ip : in STD_LOGIC_VECTOR(15 downto 0); oe : in STD_LOGIC; op_fb : out STD_LOGIC_VECTOR(15 downto 0); op : inout STD_LOGIC_VECTOR(15 downto 0) ); end component; component counters port ( clock : in STD_LOGIC; enable : in STD_LOGIC; flashes : in STD_LOGIC_VECTOR(15 downto 0); load : in STD_LOGIC; period : in STD_LOGIC_VECTOR(15 downto 0); reset : in STD_LOGIC; count : out STD_LOGIC_VECTOR(15 downto 0); end_of_flashlet : out STD_LOGIC ); end component; component flash_control_fsm port ( clock : in STD_LOGIC; end_of_flashlet : in STD_LOGIC; full : in STD_LOGIC; reset : in STD_LOGIC; go : out STD_LOGIC; load_count : out STD_LOGIC ); end component; component pwm port ( clock : in STD_LOGIC; count : in STD_LOGIC_VECTOR(15 downto 0); enable : in STD_LOGIC; load : in STD_LOGIC; off_limit : in STD_LOGIC_VECTOR(15 downto 0); on_limit : in STD_LOGIC_VECTOR(15 downto 0); reset : in STD_LOGIC; pulse : out STD_LOGIC ); end component; component registers port ( address : in STD_LOGIC_VECTOR(5 downto 2); clock : in STD_LOGIC; cs_n : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR(15 downto 0); done : in STD_LOGIC; rd_n : in STD_LOGIC; reset : in STD_LOGIC; wr_n : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR(15 downto 0); flash_off : out STD_LOGIC_VECTOR(15 downto 0); flash_on : out STD_LOGIC_VECTOR(15 downto 0); flashes : out STD_LOGIC_VECTOR(15 downto 0); full : out STD_LOGIC; oe : out STD_LOGIC; period : out STD_LOGIC_VECTOR(15 downto 0); sample_off : out STD_LOGIC_VECTOR(15 downto 0); sample_on : out STD_LOGIC_VECTOR(15 downto 0) ); end component; component reset_synchronizer port ( async_reset_n : in STD_LOGIC; clock : in STD_LOGIC; sync_reset : out STD_LOGIC ); end component; component pwr -- synopsys translate_off generic( InstancePath : STRING := "*"; MsgOn : BOOLEAN := True; TimingChecksOn : BOOLEAN := True; Xon : BOOLEAN := False ); -- synopsys translate_on port ( Y : out std_ulogic ); end component; ---- Signal declarations used on the diagram ---- signal drive_bus : STD_LOGIC; signal end_of_flashlet : STD_LOGIC; signal flash : STD_LOGIC; signal full : STD_LOGIC; signal go : STD_LOGIC; signal load_count : STD_LOGIC; signal reset : STD_LOGIC; signal sample_adc : STD_LOGIC; signal count : STD_LOGIC_VECTOR (15 downto 0); signal data_in : STD_LOGIC_VECTOR (15 downto 0); signal data_out : STD_LOGIC_VECTOR (15 downto 0); signal flash_off : STD_LOGIC_VECTOR (15 downto 0); signal flash_on : STD_LOGIC_VECTOR (15 downto 0); signal number : STD_LOGIC_VECTOR (15 downto 0); signal period : STD_LOGIC_VECTOR (15 downto 0); signal sample_off : STD_LOGIC_VECTOR (15 downto 0); signal sample_on : STD_LOGIC_VECTOR (15 downto 0); ---- Configuration specifications for declared components -- synopsys translate_off for U9 : pwr use entity APA.pwr; -- synopsys translate_on begin ---- Component instantiations ---- U1 : registers port map( address => address_ipads, clock => clock_ipad, cs_n => cs_n_ipad, data_in => data_in, data_out => data_out, done => load_count, flash_off => flash_off, flash_on => flash_on, flashes => number, full => full, oe => drive_bus, period => period, rd_n => rd_n_ipad, reset => reset, sample_off => sample_off, sample_on => sample_on, wr_n => wr_0_n_ipad ); U2 : reset_synchronizer port map( async_reset_n => async_reset_n_ipad, clock => clock_ipad, sync_reset => reset ); U3 : bus_bidirectional_buffer port map( ip => data_out, oe => drive_bus, op => data_iopads, op_fb => data_in ); U4 : pwm port map( clock => clock_ipad, count => count, enable => go, load => load_count, off_limit => flash_off, on_limit => flash_on, pulse => flash, reset => reset ); U5 : pwm port map( clock => clock_ipad, count => count, enable => go, load => load_count, off_limit => sample_off, on_limit => sample_on, pulse => sample_adc, reset => reset ); U6 : counters port map( clock => clock_ipad, count => count, enable => go, end_of_flashlet => end_of_flashlet, flashes => number, load => load_count, period => period, reset => reset ); U7 : flash_control_fsm port map( clock => clock_ipad, end_of_flashlet => end_of_flashlet, full => full, go => go, load_count => load_count, reset => reset ); U9 : pwr port map( Y => stall_n_opad ); ---- Terminal assignment ---- -- Output\buffer terminals flash_opad <= flash; interrupt_n_opad <= full; sample_adc_opad <= sample_adc; end biosa;