library ieee;
use ieee.std_logic_1164.all;

entity bus_bidirectional_buffer is	  	
	port (
		oe		: in    std_logic;
		ip		: in    std_logic_vector(15 downto 0);	
		op		: inout std_logic_vector(15 downto 0); 
		op_fb	: out	std_logic_vector(15 downto 0)		
	);
end bus_bidirectional_buffer;

architecture synthesis of bus_bidirectional_buffer is
begin
	op <= ip when oe = '1' else (others => 'Z');
	op_fb <= op;
end synthesis;