-------------------------------------------------------------------------------
--
-- Title       : biosa
-- Design      : analog_io
-- Author      : Unknown
-- Company     : Unknown
--
-------------------------------------------------------------------------------
--
-- File        : c:\my_designs\biosa\MotherBoard\analog_io\compile\biosa.vhd
-- Generated   : Thu Feb 15 14:16:48 2007
-- From        : c:\my_designs\biosa\MotherBoard\analog_io\src\biosa.bde
-- By          : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;


-- other libraries declarations
library ANALOG_IO;
-- synopsys translate_off 
library APA;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on 

entity biosa is
  port(
       async_reset_n_ipad : in STD_LOGIC;
       cs_n_ipad : in STD_LOGIC;
       fpga_clock_n_ipad : in std_ulogic;
       fpga_clock_p_ipad : in std_ulogic;
       rd_n_ipad : in STD_LOGIC;
       spi_dio_ipad : in STD_LOGIC;
       wr_0_n_ipad : in std_logic;
       wr_1_n_ipad : in std_logic;
       address_ipads : in STD_LOGIC_VECTOR(15 downto 0);
       dac_clock_opad : out STD_LOGIC;
       dac_cs_n_opad : out STD_LOGIC;
       dac_data_opad : out STD_LOGIC;
       interrupt_n_opad : out std_logic;
       spi_clock_opad : out STD_LOGIC;
       spi_cs_n_opad : out STD_LOGIC;
       spi_sdo_opad : out STD_LOGIC;
       stall_n_opad : out std_logic;
       data_iopads : inout STD_LOGIC_VECTOR(15 downto 0)
  );
end biosa;

architecture synthesis of biosa is

---- Component declarations -----

component bus_bidirectional_buffer
  port (
       ip_in : in STD_LOGIC_VECTOR(15 downto 0);
       oe_in : in STD_LOGIC;
       op_fb_out : out STD_LOGIC_VECTOR(15 downto 0);
       op_io : inout STD_LOGIC_VECTOR(15 downto 0)
  );
end component;
component clock_prescalar
  port (
       clock_in : in STD_LOGIC;
       mhz_20_out : out STD_LOGIC
  );
end component;
component dac_serializer
  port (
       clock_in : in STD_LOGIC;
       configuration_data_in : in STD_LOGIC_VECTOR(23 downto 0);
       enable_in : in STD_LOGIC;
       reset_in : in STD_LOGIC;
       start_in : in STD_LOGIC;
       dac_clock_out : out STD_LOGIC;
       dac_data_out : out STD_LOGIC;
       dac_select_n_out : out STD_LOGIC;
       dac_transfer_done_out : out STD_LOGIC
  );
end component;
component mxfe_configurator
  port (
       clock_in : in STD_LOGIC;
       configuration_data_in : in STD_LOGIC_VECTOR(23 downto 0);
       enable_in : in STD_LOGIC;
       mxfe_register_data_in : in STD_LOGIC;
       one_n_or_two_in : in STD_LOGIC;
       reset_in : in STD_LOGIC;
       start_in : in STD_LOGIC;
       write_n_or_read_in : in STD_LOGIC;
       configuration_clock_out : out STD_LOGIC;
       configuration_data_out : out STD_LOGIC;
       configuration_done_out : out STD_LOGIC;
       configuration_select_n_out : out STD_LOGIC;
       mxfe_register_data_out : out STD_LOGIC_VECTOR(7 downto 0)
  );
end component;
component registers
  port (
       address_in : in STD_LOGIC_VECTOR(15 downto 0);
       clock_in : in STD_LOGIC;
       cs_n_in : in STD_LOGIC;
       dac_transfer_done_in : in STD_LOGIC;
       data_in : in STD_LOGIC_VECTOR(15 downto 0);
       mxfe_configurator_done_in : in STD_LOGIC;
       mxfe_register_data_in : in STD_LOGIC_VECTOR(7 downto 0);
       rd_n_in : in STD_LOGIC;
       reset_in : in STD_LOGIC;
       wr_n_in : in STD_LOGIC;
       dac_data_out : out STD_LOGIC_VECTOR(23 downto 0);
       dac_serializer_fsm_clock_enable_out : out STD_LOGIC;
       dac_start_serializer_out : out STD_LOGIC;
       data_out : out STD_LOGIC_VECTOR(15 downto 0);
       drive_cpu_bus_out : out STD_LOGIC;
       mxfe_configuration_data_out : out STD_LOGIC_VECTOR(23 downto 0);
       mxfe_configuration_fsm_clock_enable_out : out STD_LOGIC;
       mxfe_one_n_or_two_out : out STD_LOGIC;
       mxfe_start_serializer_out : out STD_LOGIC;
       mxfe_write_n_or_read_out : out STD_LOGIC
  );
end component;
component reset_synchronizer
  port (
       async_reset_n_in : in STD_LOGIC;
       clock_in : in STD_LOGIC;
       sync_reset_out : out STD_LOGIC
  );
end component;
component glpe
-- synopsys translate_off
  generic(
       InstancePath : STRING := "*";
       MsgOn : BOOLEAN := True;
       TimingChecksOn : BOOLEAN := True;
       Xon : BOOLEAN := TRUE;
       tipd_PECLIN : VitalDelayType01 := (0.0 ns,0.0 ns);
       tipd_PECLREF : VitalDelayType01 := (0.0 ns,0.0 ns);
       tpd_PECLIN_GL : VitalDelayType01 := (0.10000000000000001 ns,0.10000000000000001 ns)
  );
-- synopsys translate_on
  port (
       PECLIN : in std_ulogic;
       PECLREF : in std_ulogic;
       GL : out std_ulogic
  );
end component;
component pwr
-- synopsys translate_off
  generic(
       InstancePath : STRING := "*";
       MsgOn : BOOLEAN := True;
       TimingChecksOn : BOOLEAN := True;
       Xon : BOOLEAN := False
  );
-- synopsys translate_on
  port (
       Y : out std_ulogic
  );
end component;

---- Signal declarations used on the diagram ----

signal configuration_busy : STD_LOGIC;
signal dac_clock_enable : STD_LOGIC;
signal dac_start : STD_LOGIC;
signal dac_transfer_busy : STD_LOGIC;
signal drive_cpu_bus : STD_LOGIC;
signal mhz_20_clock : STD_LOGIC;
signal mhz_80_clock : STD_LOGIC;
signal mxfe_clock_enable : STD_LOGIC;
signal mxfe_start : STD_LOGIC;
signal NET509 : STD_LOGIC;
signal one_n_or_two : STD_LOGIC;
signal reset : STD_LOGIC;
signal write_n : STD_LOGIC;
signal write_n_or_read : STD_LOGIC;
signal dac_data : STD_LOGIC_VECTOR (23 downto 0);
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);
signal mxfe_configuration_data : STD_LOGIC_VECTOR (23 downto 0);
signal mxfe_register_data : STD_LOGIC_VECTOR (7 downto 0);

---- Configuration specifications for declared components 

-- synopsys translate_off
for U6 : glpe use entity apa.glpe;
-- synopsys translate_on
-- synopsys translate_off
for U9 : pwr use entity APA.pwr;
-- synopsys translate_on

begin

----  Component instantiations  ----

U1 : registers
  port map(
       address_in => address_ipads,
       clock_in => mhz_20_clock,
       cs_n_in => cs_n_ipad,
       dac_data_out => dac_data,
       dac_serializer_fsm_clock_enable_out => dac_clock_enable,
       dac_start_serializer_out => dac_start,
       dac_transfer_done_in => dac_transfer_busy,
       data_in => data_in,
       data_out => data_out,
       drive_cpu_bus_out => drive_cpu_bus,
       mxfe_configuration_data_out => mxfe_configuration_data,
       mxfe_configuration_fsm_clock_enable_out => mxfe_clock_enable,
       mxfe_configurator_done_in => configuration_busy,
       mxfe_one_n_or_two_out => one_n_or_two,
       mxfe_register_data_in => mxfe_register_data,
       mxfe_start_serializer_out => mxfe_start,
       mxfe_write_n_or_read_out => write_n_or_read,
       rd_n_in => rd_n_ipad,
       reset_in => reset,
       wr_n_in => write_n
  );

U2 : reset_synchronizer
  port map(
       async_reset_n_in => async_reset_n_ipad,
       clock_in => mhz_20_clock,
       sync_reset_out => reset
  );

U3 : bus_bidirectional_buffer
  port map(
       ip_in => data_out,
       oe_in => drive_cpu_bus,
       op_fb_out => data_in,
       op_io => data_iopads
  );

U4 : mxfe_configurator
  port map(
       clock_in => mhz_20_clock,
       configuration_clock_out => spi_clock_opad,
       configuration_data_in => mxfe_configuration_data,
       configuration_data_out => spi_sdo_opad,
       configuration_done_out => configuration_busy,
       configuration_select_n_out => spi_cs_n_opad,
       enable_in => mxfe_clock_enable,
       mxfe_register_data_in => spi_dio_ipad,
       mxfe_register_data_out => mxfe_register_data,
       one_n_or_two_in => one_n_or_two,
       reset_in => reset,
       start_in => mxfe_start,
       write_n_or_read_in => write_n_or_read
  );

U5 : clock_prescalar
  port map(
       clock_in => mhz_80_clock,
       mhz_20_out => mhz_20_clock
  );

U6 : glpe
  port map(
       GL => mhz_80_clock,
       PECLIN => fpga_clock_n_ipad,
       PECLREF => fpga_clock_p_ipad
  );

U7 : dac_serializer
  port map(
       clock_in => mhz_20_clock,
       configuration_data_in => dac_data,
       dac_clock_out => dac_clock_opad,
       dac_data_out => dac_data_opad,
       dac_select_n_out => dac_cs_n_opad,
       dac_transfer_done_out => dac_transfer_busy,
       enable_in => dac_clock_enable,
       reset_in => reset,
       start_in => dac_start
  );

write_n <= wr_0_n_ipad and wr_1_n_ipad;

U9 : pwr
  port map(
       Y => NET509
  );


---- Terminal assignment ----

    -- Output\buffer terminals
	interrupt_n_opad <= NET509;
	stall_n_opad <= NET509;


end synthesis;