-------------------------------------------------------------------------------
--
-- Title       : No Title
-- Design      : analog_io
-- Author      : Wayne Radochonski
-- Company     : Acumentix
--
-------------------------------------------------------------------------------
--
-- File        : c:\my_designs\biosa\MotherBoard\analog_io\compile\dac_serializer.vhd
-- Generated   : Thu Feb 15 14:15:07 2007
-- From        : c:\my_designs\biosa\MotherBoard\analog_io\src\dac_serializer.bde
-- By          : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;


-- other libraries declarations
library ANALOG_IO;

entity dac_serializer is
  port(
       clock_in : in STD_LOGIC;
       enable_in : in STD_LOGIC;
       reset_in : in STD_LOGIC;
       start_in : in STD_LOGIC;
       configuration_data_in : in STD_LOGIC_VECTOR(23 downto 0);
       dac_clock_out : out STD_LOGIC;
       dac_data_out : out STD_LOGIC;
       dac_select_n_out : out STD_LOGIC;
       dac_transfer_done_out : out STD_LOGIC
  );
end dac_serializer;

architecture dac_serializer of dac_serializer is

---- Component declarations -----

component dac_serializer_fsm
  port (
       clock_in : in STD_LOGIC;
       read_clock_enable_in : in STD_LOGIC;
       reset_in : in STD_LOGIC;
       start_in : in STD_LOGIC;
       write_clock_enable_in : in STD_LOGIC;
       done_out : out STD_LOGIC;
       load_configuration_data_out : out STD_LOGIC;
       select_dac_n_out : out STD_LOGIC;
       shift_configuration_data_out : out STD_LOGIC
  );
end component;
component mxfe_clock_generator
  port (
       clock_in : in STD_LOGIC;
       enable_in : in STD_LOGIC;
       gate_clock_in : in STD_LOGIC;
       reset_in : in STD_LOGIC;
       configuration_clock_out : out STD_LOGIC;
       read_clock_enable_out : out STD_LOGIC;
       write_clock_enable_out : out STD_LOGIC
  );
end component;
component piso_shift_register
  port (
       clock_in : in STD_LOGIC;
       data_in : in STD_LOGIC_VECTOR(23 downto 0);
       enable_in : in STD_LOGIC;
       load_in : in STD_LOGIC;
       reset_in : in STD_LOGIC;
       shift_in : in STD_LOGIC;
       data_out : out STD_LOGIC
  );
end component;

---- Signal declarations used on the diagram ----

signal load_configuration_data : STD_LOGIC;
signal read_clock_enable : STD_LOGIC;
signal shift_configuration_data : STD_LOGIC;
signal write_clock_enable : STD_LOGIC;

begin

----  Component instantiations  ----

U2 : piso_shift_register
  port map(
       clock_in => clock_in,
       data_in => configuration_data_in,
       data_out => dac_data_out,
       enable_in => write_clock_enable,
       load_in => load_configuration_data,
       reset_in => reset_in,
       shift_in => shift_configuration_data
  );

U3 : dac_serializer_fsm
  port map(
       clock_in => clock_in,
       done_out => dac_transfer_done_out,
       load_configuration_data_out => load_configuration_data,
       read_clock_enable_in => read_clock_enable,
       reset_in => reset_in,
       select_dac_n_out => dac_select_n_out,
       shift_configuration_data_out => shift_configuration_data,
       start_in => start_in,
       write_clock_enable_in => write_clock_enable
  );

U4 : mxfe_clock_generator
  port map(
       clock_in => clock_in,
       configuration_clock_out => dac_clock_out,
       enable_in => enable_in,
       gate_clock_in => shift_configuration_data,
       read_clock_enable_out => read_clock_enable,
       reset_in => reset_in,
       write_clock_enable_out => write_clock_enable
  );


end dac_serializer;