-------------------------------------------------------------------------------
--
-- Title       : No Title
-- Design      : analog_io
-- Author      : Wayne Radochonski
-- Company     : Acumentix
--
-------------------------------------------------------------------------------
--
-- File        : c:\my_designs\biosa\MotherBoard\analog_io\compile\mxfe_serializer_fsm.vhd
-- Generated   : 02/15/07 13:50:20
-- From        : c:\my_designs\biosa\MotherBoard\analog_io\src\mxfe_serializer_fsm.asf
-- By          : FSM2VHDL ver. 5.0.2.7
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity mxfe_serializer_fsm is 
	port (
		clock_in: in STD_LOGIC;
		one_n_or_two_in: in STD_LOGIC;
		read_clock_enable_in: in STD_LOGIC;
		reset_in: in STD_LOGIC;
		start_in: in STD_LOGIC;
		write_clock_enable_in: in STD_LOGIC;
		write_n_or_read_in: in STD_LOGIC;
		configure_mxfe_out: out STD_LOGIC;
		done_out: out STD_LOGIC;
		load_configuration_data_out: out STD_LOGIC;
		shift_configuration_data_out: out STD_LOGIC;
		shift_mxfe_register_data_out: out STD_LOGIC);
end mxfe_serializer_fsm;

architecture synthesis of mxfe_serializer_fsm is

-- diagram signals declarations
signal counter: STD_LOGIC_VECTOR (4 downto 0);

-- ONE HOT ENCODED state machine: next_state
attribute enum_encoding: string;
type next_state_type is (
    IDLE, RUN, READ, WRITE_1, WRITE_2, WAIT1, WAIT2
);
attribute enum_encoding of next_state_type: type is
	"0000001 " &		-- IDLE
	"0000010 " &		-- RUN
	"0000100 " &		-- READ
	"0001000 " &		-- WRITE_1
	"0010000 " &		-- WRITE_2
	"0100000 " &		-- WAIT1
	"1000000" ; 		-- WAIT2

signal next_state, NextState_next_state: next_state_type;

-- Declarations of pre-registered internal signals
signal int_configure_mxfe_out, next_configure_mxfe_out: STD_LOGIC;
signal int_done_out, next_done_out: STD_LOGIC;
signal int_load_configuration_data_out, next_load_configuration_data_out: STD_LOGIC;
signal int_shift_configuration_data_out, next_shift_configuration_data_out: STD_LOGIC;
signal int_shift_mxfe_register_data_out, next_shift_mxfe_register_data_out: STD_LOGIC;

begin


----------------------------------------------------------------------
-- Machine: next_state
----------------------------------------------------------------------
------------------------------------
-- Next State Logic (combinatorial)
------------------------------------
next_state_NextState: process (start_in, counter, write_n_or_read_in, read_clock_enable_in, one_n_or_two_in, write_clock_enable_in, next_state)
begin
	NextState_next_state <= next_state;
	case next_state is
		when IDLE =>
			if start_in = '1' then	
				NextState_next_state <= WAIT1;
			end if;
		when RUN =>
			if counter = "00111" and write_n_or_read_in = '0' and read_clock_enable_in = '1' then	
				NextState_next_state <= WRITE_1;
			elsif read_clock_enable_in = '0' then	
				NextState_next_state <= RUN;
			elsif counter = "00111" and write_n_or_read_in = '1' and read_clock_enable_in = '1' then	
				NextState_next_state <= READ;
			end if;
		when READ =>
			if counter = "01111" and read_clock_enable_in = '1' then	
				NextState_next_state <= WAIT2;
			elsif read_clock_enable_in = '0' then	
				NextState_next_state <= READ;
			end if;
		when WRITE_1 =>
			if read_clock_enable_in = '0' then	
				NextState_next_state <= WRITE_1;
			elsif counter = "01111" and one_n_or_two_in = '0' and read_clock_enable_in = '1' then	
				NextState_next_state <= WAIT2;
			elsif counter = "01111" and one_n_or_two_in = '1' and read_clock_enable_in = '1' then	
				NextState_next_state <= WRITE_2;
			end if;
		when WRITE_2 =>
			if read_clock_enable_in = '0' then	
				NextState_next_state <= WRITE_2;
			elsif counter = "10111" and read_clock_enable_in = '1' then	
				NextState_next_state <= WAIT2;
			end if;
		when WAIT1 =>
			if write_clock_enable_in = '1' then	
				NextState_next_state <= RUN;
			end if;
		when WAIT2 =>
			if write_clock_enable_in = '1' then	
				NextState_next_state <= IDLE;
			end if;
		when others =>
			null;
	end case;
end process;

------------------------------------
-- Output Block
------------------------------------
next_state_OutputBlock: process (write_clock_enable_in, int_shift_configuration_data_out, int_load_configuration_data_out, int_shift_mxfe_register_data_out, int_configure_mxfe_out, int_done_out, next_state)
begin
	-- Set default values for outputs and signals
	next_shift_configuration_data_out <= int_shift_configuration_data_out;
	next_load_configuration_data_out <= int_load_configuration_data_out;
	next_shift_mxfe_register_data_out <= int_shift_mxfe_register_data_out;
	next_configure_mxfe_out <= int_configure_mxfe_out;
	next_done_out <= int_done_out;
	case next_state is
		when IDLE =>
			next_shift_configuration_data_out <= '0';
			next_load_configuration_data_out <= '0';
			next_shift_mxfe_register_data_out <= '0';
			next_configure_mxfe_out <= '1';
			next_done_out <= '0';
		when RUN =>
			next_load_configuration_data_out <= '0';
			next_configure_mxfe_out <= '0';
			next_shift_configuration_data_out <= '1';
		when READ =>
			if write_clock_enable_in = '1' then
			      next_shift_mxfe_register_data_out <= '1';
			end if;
		when WAIT1 =>
			if write_clock_enable_in = '1' then	
				next_load_configuration_data_out <= '1';
			end if;
		when WAIT2 =>
			if write_clock_enable_in = '1' then	
				next_done_out <= '1';
			end if;
		when others =>
			null;
	end case;
end process;

------------------------------------
-- Current State Logic (sequential)
------------------------------------
next_state_CurrentState: process (clock_in)
begin
	if rising_edge(clock_in) then
		if reset_in = '1' then	
			next_state <= IDLE;
			counter <= "00000";
		else
			next_state <= NextState_next_state;
			-- Set default values for outputs and signals
			-- ...
			case next_state is
				when IDLE =>
					counter <= "00000";
				when RUN =>
					if read_clock_enable_in = '1' then
					      counter <= counter + 1;
					end if;
				when READ =>
					if read_clock_enable_in = '1' then
					      counter <= counter + 1;
					end if;
				when WRITE_1 =>
					if read_clock_enable_in = '1' then
					      counter <= counter + 1;
					end if;
				when WRITE_2 =>
					if read_clock_enable_in = '1' then
					      counter <= counter + 1;
					end if;
				when others =>
					null;
			end case;
		end if;
	end if;
end process;

------------------------------------
-- Registered Outputs Logic
------------------------------------
next_state_RegOutput: process (clock_in)
begin
	if rising_edge(clock_in) then
		if reset_in = '1' then	
			int_shift_configuration_data_out <= '0';
			int_load_configuration_data_out <= '0';
			int_shift_mxfe_register_data_out <= '0';
			int_configure_mxfe_out <= '1';
			int_done_out <= '0';
		else
			int_shift_configuration_data_out <= next_shift_configuration_data_out;
			int_load_configuration_data_out <= next_load_configuration_data_out;
			int_shift_mxfe_register_data_out <= next_shift_mxfe_register_data_out;
			int_configure_mxfe_out <= next_configure_mxfe_out;
			int_done_out <= next_done_out;
		end if;
	end if;
end process;

-- Copy temporary signals to target output ports
shift_configuration_data_out <= int_shift_configuration_data_out;
load_configuration_data_out <= int_load_configuration_data_out;
shift_mxfe_register_data_out <= int_shift_mxfe_register_data_out;
configure_mxfe_out <= int_configure_mxfe_out;
done_out <= int_done_out;

end synthesis;