; HEADER ; FILEID ADL ./biosa.adl 179ee5b4 ; CHECKSUM 179ee5b4 ; ASC c816d456 ; PROGRAM Actel Designer Software ; VERSION 7.2 SP2 7.2.3.2 ; ALSMAJORREV 7 ; ALSMINORREV 2 ; ALSPATCHREV 3 ; VAR DESIGN biosa ; VAR FAM PA ; VAR FAMILY PA ; VAR DIE 075 ; VAR PACKAGE tq100 ; VAR IFIKEEPER ; VAR RESTRICTTRSTPIN YES ; VAR UNCLAMP_UNUSED_IOS 0 ; VAR RESERVE_PROGRAMMING_PINS 1 ; VAR RESTRICTPROBEPINS 0 ; VAR RESTRICTJTAGPINS YES ; VAR SPEED -F ; VAR TEMPR COM ; VAR VOLTR COM ; VAR SI_SECURITY_KEY ; VAR SIG ; VAR FUSCHECKSUM ; VAR PROGSECFUSE ; VAR PINCHECKSUM ; VAR ACT1_special_IO_pins_used NO ; VAR AXPRG_USE_UMA ; ENDHEADER DEF clock_prescalar; mhz_80_clock, mhz_20_clock_0, mhz_20_clock_1, mhz_20_clock_2, mhz_20_clock_3, mhz_20_clock_4, mhz_20_clock_5, mhz_20_clock_6, mhz_20_clock_7, mhz_20_clock_8, mhz_20_clock_9, mhz_20_clock_10, mhz_20_clock_11, mhz_20_clock_12, mhz_20_clock_13. PIN mhz_80_clock; DIRECTION:INPUT. PIN mhz_20_clock_0; DIRECTION:OUTPUT. PIN mhz_20_clock_1; DIRECTION:OUTPUT. PIN mhz_20_clock_2; DIRECTION:OUTPUT. PIN mhz_20_clock_3; DIRECTION:OUTPUT. PIN mhz_20_clock_4; DIRECTION:OUTPUT. PIN mhz_20_clock_5; DIRECTION:OUTPUT. PIN mhz_20_clock_6; DIRECTION:OUTPUT. PIN mhz_20_clock_7; DIRECTION:OUTPUT. PIN mhz_20_clock_8; DIRECTION:OUTPUT. PIN mhz_20_clock_9; DIRECTION:OUTPUT. PIN mhz_20_clock_10; DIRECTION:OUTPUT. PIN mhz_20_clock_11; DIRECTION:OUTPUT. PIN mhz_20_clock_12; DIRECTION:OUTPUT. PIN mhz_20_clock_13; DIRECTION:OUTPUT. USE ADLIB:INV; counter_bits_i[0]. USE ADLIB:BFR; counter_bits_inferred_clock_3[1]. USE ADLIB:BFR; counter_bits_inferred_clock_2[1]. USE ADLIB:BFR; counter_bits_inferred_clock_13[1]. USE ADLIB:BFR; counter_bits_inferred_clock_8[1]. USE ADLIB:BFR; counter_bits_inferred_clock_12[1]. USE ADLIB:PWR; PWR_i. USE ADLIB:BFR; counter_bits_inferred_clock_9[1]. USE ADLIB:BFR; counter_bits_inferred_clock_6[1]. USE ADLIB:DFF; counter_bits[1]. USE ADLIB:BFR; counter_bits_inferred_clock_1[1]. USE ADLIB:GND; GND_i. USE ADLIB:BFR; counter_bits_inferred_clock_0[1]. USE ADLIB:DFF; counter_bits[0]. USE ADLIB:BFR; counter_bits_inferred_clock_7[1]. USE ADLIB:BFR; counter_bits_inferred_clock_4[1]. USE ADLIB:BFR; counter_bits_inferred_clock_11[1]. USE ADLIB:BFR; counter_bits_inferred_clock_10[1]. USE ADLIB:XOR2; un2_counter_bits_1_SUM1. USE ADLIB:BFR; counter_bits_inferred_clock_5[1]. USE ADLIB:BFR; counter_bits_inferred_clock_0_0[1]. NET mhz_80_clock; mhz_80_clock, counter_bits[0]:CLK, counter_bits[1]:CLK. NET mhz_20_clock_0; mhz_20_clock_0, counter_bits_inferred_clock_0[1]:Y. NET mhz_20_clock_1; mhz_20_clock_1, un2_counter_bits_1_SUM1:B, counter_bits_inferred_clock_1[1]:Y. NET mhz_20_clock_2; mhz_20_clock_2, counter_bits_inferred_clock_2[1]:Y. NET mhz_20_clock_3; mhz_20_clock_3, counter_bits_inferred_clock_3[1]:Y. NET mhz_20_clock_4; mhz_20_clock_4, counter_bits_inferred_clock_4[1]:Y. NET mhz_20_clock_5; mhz_20_clock_5, counter_bits_inferred_clock_5[1]:Y. NET mhz_20_clock_6; mhz_20_clock_6, counter_bits_inferred_clock_6[1]:Y. NET mhz_20_clock_7; mhz_20_clock_7, counter_bits_inferred_clock_7[1]:Y. NET mhz_20_clock_8; mhz_20_clock_8, counter_bits_inferred_clock_8[1]:Y. NET mhz_20_clock_9; mhz_20_clock_9, counter_bits_inferred_clock_9[1]:Y. NET mhz_20_clock_10; mhz_20_clock_10, counter_bits_inferred_clock_10[1]:Y. NET mhz_20_clock_11; mhz_20_clock_11, counter_bits_inferred_clock_11[1]:Y. NET mhz_20_clock_12; mhz_20_clock_12, counter_bits_inferred_clock_12[1]:Y. NET mhz_20_clock_13; mhz_20_clock_13, counter_bits_inferred_clock_13[1]:Y. NET counter_bits[1]; counter_bits_inferred_clock_3[1]:A, counter_bits_inferred_clock_0_0[1]:A, counter_bits_inferred_clock_5[1]:A, counter_bits_inferred_clock_4[1]:A, counter_bits_inferred_clock_0[1]:A, counter_bits_inferred_clock_1[1]:A, counter_bits[1]:Q, counter_bits_inferred_clock_6[1]:A, counter_bits_inferred_clock_2[1]:A. NET mhz_20_clock_0_0; counter_bits_inferred_clock_13[1]:A, counter_bits_inferred_clock_0_0[1]:Y, counter_bits_inferred_clock_10[1]:A, counter_bits_inferred_clock_11[1]:A, counter_bits_inferred_clock_7[1]:A, counter_bits_inferred_clock_9[1]:A, counter_bits_inferred_clock_12[1]:A, counter_bits_inferred_clock_8[1]:A. NET counter_bits_i_0[0]; counter_bits[0]:D, counter_bits_i[0]:Y. NET counter_bits[0]; counter_bits_i[0]:A, un2_counter_bits_1_SUM1:A, counter_bits[0]:Q. NET SUM1; counter_bits[1]:D, un2_counter_bits_1_SUM1:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF jk_ff; mhz_20_clock_1, mxfe_start, configuration_busy, mxfe_busy, reset_10. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN mxfe_start; DIRECTION:INPUT. PIN configuration_busy; DIRECTION:INPUT. PIN mxfe_busy; DIRECTION:OUTPUT. PIN reset_10; DIRECTION:INPUT. USE ADLIB:NOR2; jk_next_state_qns7. USE ADLIB:AOI21TTF; ff_q_3_r. USE ADLIB:DFF; q. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2FT; q_1. USE ADLIB:MUX2H; q_0. USE ADLIB:GND; GND_i. NET mhz_20_clock_1; mhz_20_clock_1, q:CLK. NET mxfe_start; mxfe_start, ff_q_3_r:C, jk_next_state_qns7:B. NET configuration_busy; configuration_busy, ff_q_3_r:B, jk_next_state_qns7:A. NET mxfe_busy; mxfe_busy, q_0:B, q:Q, ff_q_3_r:A. NET reset_10; reset_10, q_1:B. NET q_1; q:D, q_1:Y. NET q_0; q_1:A, q_0:Y. NET q_3; q_0:A, ff_q_3_r:Y. NET qns7; q_0:S, jk_next_state_qns7:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF dual_rank_synchronizer_1; mhz_20_clock_1, synced_wr_n, reset_10, wr_0_n_ipad_c, wr_1_n_ipad_c. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN synced_wr_n; DIRECTION:OUTPUT. PIN reset_10; DIRECTION:INPUT. PIN wr_0_n_ipad_c; DIRECTION:INPUT. PIN wr_1_n_ipad_c; DIRECTION:INPUT. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2FT; rank_2_0_0_a3. USE ADLIB:DFF; rank_2. USE ADLIB:NOR3FFT; rank_1_0_0_a3. USE ADLIB:DFF; rank_1. USE ADLIB:GND; GND_i. NET mhz_20_clock_1; mhz_20_clock_1, rank_1:CLK, rank_2:CLK. NET synced_wr_n; synced_wr_n, rank_2:Q. NET reset_10; reset_10, rank_1_0_0_a3:C, rank_2_0_0_a3:B. NET wr_0_n_ipad_c; wr_0_n_ipad_c, rank_1_0_0_a3:B. NET wr_1_n_ipad_c; wr_1_n_ipad_c, rank_1_0_0_a3:A. NET rank_1_0_0_a3_0; rank_1:D, rank_1_0_0_a3:Y. NET rank_2_0_0_a3_0; rank_2:D, rank_2_0_0_a3:Y. NET rank_1; rank_2_0_0_a3:A, rank_1:Q. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF dual_rank_synchronizer; mhz_20_clock_1, synced_cs_n, reset_10, cs_n_ipad_c. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN synced_cs_n; DIRECTION:OUTPUT. PIN reset_10; DIRECTION:INPUT. PIN cs_n_ipad_c; DIRECTION:INPUT. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2FT; rank_2_0_0_a3. USE ADLIB:DFF; rank_2. USE ADLIB:NOR2FT; rank_1_0_0_a3. USE ADLIB:DFF; rank_1. USE ADLIB:GND; GND_i. NET mhz_20_clock_1; mhz_20_clock_1, rank_1:CLK, rank_2:CLK. NET synced_cs_n; synced_cs_n, rank_2:Q. NET reset_10; reset_10, rank_1_0_0_a3:B, rank_2_0_0_a3:B. NET cs_n_ipad_c; cs_n_ipad_c, rank_1_0_0_a3:A. NET rank_1_0_0_a3; rank_1:D, rank_1_0_0_a3:Y. NET rank_2_0_0_a3; rank_2:D, rank_2_0_0_a3:Y. NET rank_1; rank_2_0_0_a3:A, rank_1:Q. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF falling_edge_detector; mhz_20_clock_1, candidate_delayed, reset_10, synced_wr_n. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN candidate_delayed; DIRECTION:OUTPUT. PIN reset_10; DIRECTION:INPUT. PIN synced_wr_n; DIRECTION:INPUT. USE ADLIB:NOR2FT; candidate_delayed_0_0_a3. USE ADLIB:PWR; PWR_i. USE ADLIB:DFF; candidate_delayed. USE ADLIB:GND; GND_i. NET mhz_20_clock_1; mhz_20_clock_1, candidate_delayed:CLK. NET candidate_delayed; candidate_delayed, candidate_delayed:Q. NET reset_10; reset_10, candidate_delayed_0_0_a3:B. NET synced_wr_n; synced_wr_n, candidate_delayed_0_0_a3:A. NET candidate_delayed_0_0_a3; candidate_delayed:D, candidate_delayed_0_0_a3:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF jk_ff_1; mhz_20_clock_1, dac_transfer_busy, dac_start, dac_busy, reset_10. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN dac_transfer_busy; DIRECTION:INPUT. PIN dac_start; DIRECTION:INPUT. PIN dac_busy; DIRECTION:OUTPUT. PIN reset_10; DIRECTION:INPUT. USE ADLIB:NOR2; jk_next_state_qns7. USE ADLIB:AOI21TTF; ff_q_3_r. USE ADLIB:DFF; q. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2FT; q_1. USE ADLIB:MUX2H; q_0. USE ADLIB:GND; GND_i. NET mhz_20_clock_1; mhz_20_clock_1, q:CLK. NET dac_transfer_busy; dac_transfer_busy, ff_q_3_r:B, jk_next_state_qns7:B. NET dac_start; dac_start, ff_q_3_r:C, jk_next_state_qns7:A. NET dac_busy; dac_busy, q_0:B, q:Q, ff_q_3_r:A. NET reset_10; reset_10, q_1:B. NET q_1_0; q:D, q_1:Y. NET q_0_0; q_1:A, q_0:Y. NET q_3; q_0:A, ff_q_3_r:Y. NET qns7; q_0:S, jk_next_state_qns7:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF registers; mxfe_register_data<7>, mxfe_register_data<6>, mxfe_register_data<5>, mxfe_register_data<4>, mxfe_register_data<3>, mxfe_register_data<2>, mxfe_register_data<1>, mxfe_register_data<0>, data_out_0_iv_i<14>, mxfe_configuration_data<21>, mxfe_configuration_data<20>, mxfe_configuration_data<19>, mxfe_configuration_data<18>, mxfe_configuration_data<17>, mxfe_configuration_data<16>, mxfe_configuration_data<15>, mxfe_configuration_data<14>, mxfe_configuration_data<13>, mxfe_configuration_data<12>, mxfe_configuration_data<11>, mxfe_configuration_data<10>, mxfe_configuration_data<9>, mxfe_configuration_data<8>, mxfe_configuration_data<7>, mxfe_configuration_data<6>, mxfe_configuration_data<5>, mxfe_configuration_data<4>, mxfe_configuration_data<3>, mxfe_configuration_data<2>, mxfe_configuration_data<1>, mxfe_configuration_data<0>, data_iopads_in<15>, data_iopads_in<14>, data_iopads_in<13>, data_iopads_in<12>, data_iopads_in<11>, data_iopads_in<10>, data_iopads_in<9>, data_iopads_in<8>, data_iopads_in<7>, data_iopads_in<6>, data_iopads_in<5>, data_iopads_in<4>, data_iopads_in<3>, data_iopads_in<2>, data_iopads_in<1>, data_iopads_in<0>, dac_data<23>, dac_data<22>, dac_data<21>, dac_data<20>, dac_data<19>, dac_data<18>, dac_data<17>, dac_data<16>, dac_data<15>, dac_data<14>, dac_data<13>, dac_data<12>, dac_data<11>, dac_data<10>, dac_data<9>, dac_data<8>, dac_data<7>, dac_data<6>, dac_data<5>, dac_data<4>, dac_data<3>, dac_data<2>, dac_data<1>, dac_data<0>, address_ipads_c_i_0_i_14, address_ipads_c_i_0_i_12, address_ipads_c_i_0_i_10, address_ipads_c_i_0_i_8, address_ipads_c_i_0_i_0, address_ipads_c_14, address_ipads_c_12, address_ipads_c_10, address_ipads_c_8, address_ipads_c_0, address_ipads_c_4, address_ipads_c_2, address_ipads_c_1, address_ipads_c_6, address_ipads_c_5, address_ipads_c_3, data_out_0, data_out_1, data_out_2, data_out_3, data_out_4, data_out_5, data_out_6, data_out_7, data_out_8, data_out_9, data_out_10, data_out_11, data_out_12, data_out_13, data_out_15, dac_transfer_busy, configuration_busy, wr_1_n_ipad_c, wr_0_n_ipad_c, mhz_20_clock_6, mhz_20_clock_5, mhz_20_clock_4, mhz_20_clock_3, mhz_20_clock_2, mhz_20_clock_1, cs_n_ipad_c, rd_n_ipad_c, synced_cs_n, mxfe_start, reset_0, dac_clock_enable, reset_6, dac_start, one_n_or_two, write_n_or_read, reset_7, reset_8, reset_9, reset_10; BUSFORMAT:%s<%d>. PIN mxfe_register_data<7>; ENM:'mxfe_register_data<7:0>', BUS:0, DIRECTION:INPUT, ORIGNAME:mxfe_register_data, BUSINFO:0/7/0/0. PIN mxfe_register_data<6>; ENM:'mxfe_register_data<7:0>', BUS:1, DIRECTION:INPUT, ORIGNAME:mxfe_register_data, BUSINFO:1/7/0/0. PIN mxfe_register_data<5>; ENM:'mxfe_register_data<7:0>', BUS:2, DIRECTION:INPUT, ORIGNAME:mxfe_register_data, BUSINFO:2/7/0/0. PIN mxfe_register_data<4>; ENM:'mxfe_register_data<7:0>', BUS:3, DIRECTION:INPUT, ORIGNAME:mxfe_register_data, BUSINFO:3/7/0/0. PIN mxfe_register_data<3>; ENM:'mxfe_register_data<7:0>', BUS:4, DIRECTION:INPUT, ORIGNAME:mxfe_register_data, BUSINFO:4/7/0/0. PIN mxfe_register_data<2>; ENM:'mxfe_register_data<7:0>', BUS:5, DIRECTION:INPUT, ORIGNAME:mxfe_register_data, BUSINFO:5/7/0/0. PIN mxfe_register_data<1>; ENM:'mxfe_register_data<7:0>', BUS:6, DIRECTION:INPUT, ORIGNAME:mxfe_register_data, BUSINFO:6/7/0/0. PIN mxfe_register_data<0>; ENM:'mxfe_register_data<7:0>', BUS:7, DIRECTION:INPUT, ORIGNAME:mxfe_register_data, BUSINFO:7/7/0/0. PIN data_out_0_iv_i<14>; ENM:'data_out_0_iv_i<14:14>', BUS:0, DIRECTION:OUTPUT, ORIGNAME:data_out_0_iv_i, BUSINFO:0/14/14/0. PIN mxfe_configuration_data<21>; ENM: 'mxfe_configuration_data<21:0>', BUS:0, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:0/21/0/0. PIN mxfe_configuration_data<20>; ENM: 'mxfe_configuration_data<21:0>', BUS:1, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:1/21/0/0. PIN mxfe_configuration_data<19>; ENM: 'mxfe_configuration_data<21:0>', BUS:2, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:2/21/0/0. PIN mxfe_configuration_data<18>; ENM: 'mxfe_configuration_data<21:0>', BUS:3, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:3/21/0/0. PIN mxfe_configuration_data<17>; ENM: 'mxfe_configuration_data<21:0>', BUS:4, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:4/21/0/0. PIN mxfe_configuration_data<16>; ENM: 'mxfe_configuration_data<21:0>', BUS:5, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:5/21/0/0. PIN mxfe_configuration_data<15>; ENM: 'mxfe_configuration_data<21:0>', BUS:6, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:6/21/0/0. PIN mxfe_configuration_data<14>; ENM: 'mxfe_configuration_data<21:0>', BUS:7, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:7/21/0/0. PIN mxfe_configuration_data<13>; ENM: 'mxfe_configuration_data<21:0>', BUS:8, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:8/21/0/0. PIN mxfe_configuration_data<12>; ENM: 'mxfe_configuration_data<21:0>', BUS:9, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:9/21/0/0. PIN mxfe_configuration_data<11>; ENM: 'mxfe_configuration_data<21:0>', BUS:10, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:10/21/0/0. PIN mxfe_configuration_data<10>; ENM: 'mxfe_configuration_data<21:0>', BUS:11, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:11/21/0/0. PIN mxfe_configuration_data<9>; ENM:'mxfe_configuration_data<21:0>', BUS:12, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:12/21/0/0. PIN mxfe_configuration_data<8>; ENM:'mxfe_configuration_data<21:0>', BUS:13, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:13/21/0/0. PIN mxfe_configuration_data<7>; ENM:'mxfe_configuration_data<21:0>', BUS:14, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:14/21/0/0. PIN mxfe_configuration_data<6>; ENM:'mxfe_configuration_data<21:0>', BUS:15, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:15/21/0/0. PIN mxfe_configuration_data<5>; ENM:'mxfe_configuration_data<21:0>', BUS:16, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:16/21/0/0. PIN mxfe_configuration_data<4>; ENM:'mxfe_configuration_data<21:0>', BUS:17, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:17/21/0/0. PIN mxfe_configuration_data<3>; ENM:'mxfe_configuration_data<21:0>', BUS:18, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:18/21/0/0. PIN mxfe_configuration_data<2>; ENM:'mxfe_configuration_data<21:0>', BUS:19, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:19/21/0/0. PIN mxfe_configuration_data<1>; ENM:'mxfe_configuration_data<21:0>', BUS:20, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:20/21/0/0. PIN mxfe_configuration_data<0>; ENM:'mxfe_configuration_data<21:0>', BUS:21, DIRECTION:OUTPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:21/21/0/0. PIN data_iopads_in<15>; ENM:'data_iopads_in<15:0>', BUS:0, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:0/15/0/0. PIN data_iopads_in<14>; ENM:'data_iopads_in<15:0>', BUS:1, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:1/15/0/0. PIN data_iopads_in<13>; ENM:'data_iopads_in<15:0>', BUS:2, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:2/15/0/0. PIN data_iopads_in<12>; ENM:'data_iopads_in<15:0>', BUS:3, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:3/15/0/0. PIN data_iopads_in<11>; ENM:'data_iopads_in<15:0>', BUS:4, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:4/15/0/0. PIN data_iopads_in<10>; ENM:'data_iopads_in<15:0>', BUS:5, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:5/15/0/0. PIN data_iopads_in<9>; ENM:'data_iopads_in<15:0>', BUS:6, DIRECTION: INPUT, ORIGNAME:data_iopads_in, BUSINFO:6/15/0/0. PIN data_iopads_in<8>; ENM:'data_iopads_in<15:0>', BUS:7, DIRECTION: INPUT, ORIGNAME:data_iopads_in, BUSINFO:7/15/0/0. PIN data_iopads_in<7>; ENM:'data_iopads_in<15:0>', BUS:8, DIRECTION: INPUT, ORIGNAME:data_iopads_in, BUSINFO:8/15/0/0. PIN data_iopads_in<6>; ENM:'data_iopads_in<15:0>', BUS:9, DIRECTION: INPUT, ORIGNAME:data_iopads_in, BUSINFO:9/15/0/0. PIN data_iopads_in<5>; ENM:'data_iopads_in<15:0>', BUS:10, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:10/15/0/0. PIN data_iopads_in<4>; ENM:'data_iopads_in<15:0>', BUS:11, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:11/15/0/0. PIN data_iopads_in<3>; ENM:'data_iopads_in<15:0>', BUS:12, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:12/15/0/0. PIN data_iopads_in<2>; ENM:'data_iopads_in<15:0>', BUS:13, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:13/15/0/0. PIN data_iopads_in<1>; ENM:'data_iopads_in<15:0>', BUS:14, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:14/15/0/0. PIN data_iopads_in<0>; ENM:'data_iopads_in<15:0>', BUS:15, DIRECTION:INPUT, ORIGNAME:data_iopads_in, BUSINFO:15/15/0/0. PIN dac_data<23>; ENM:'dac_data<23:0>', BUS:0, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:0/23/0/0. PIN dac_data<22>; ENM:'dac_data<23:0>', BUS:1, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:1/23/0/0. PIN dac_data<21>; ENM:'dac_data<23:0>', BUS:2, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:2/23/0/0. PIN dac_data<20>; ENM:'dac_data<23:0>', BUS:3, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:3/23/0/0. PIN dac_data<19>; ENM:'dac_data<23:0>', BUS:4, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:4/23/0/0. PIN dac_data<18>; ENM:'dac_data<23:0>', BUS:5, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:5/23/0/0. PIN dac_data<17>; ENM:'dac_data<23:0>', BUS:6, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:6/23/0/0. PIN dac_data<16>; ENM:'dac_data<23:0>', BUS:7, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:7/23/0/0. PIN dac_data<15>; ENM:'dac_data<23:0>', BUS:8, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:8/23/0/0. PIN dac_data<14>; ENM:'dac_data<23:0>', BUS:9, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:9/23/0/0. PIN dac_data<13>; ENM:'dac_data<23:0>', BUS:10, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:10/23/0/0. PIN dac_data<12>; ENM:'dac_data<23:0>', BUS:11, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:11/23/0/0. PIN dac_data<11>; ENM:'dac_data<23:0>', BUS:12, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:12/23/0/0. PIN dac_data<10>; ENM:'dac_data<23:0>', BUS:13, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:13/23/0/0. PIN dac_data<9>; ENM:'dac_data<23:0>', BUS:14, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:14/23/0/0. PIN dac_data<8>; ENM:'dac_data<23:0>', BUS:15, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:15/23/0/0. PIN dac_data<7>; ENM:'dac_data<23:0>', BUS:16, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:16/23/0/0. PIN dac_data<6>; ENM:'dac_data<23:0>', BUS:17, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:17/23/0/0. PIN dac_data<5>; ENM:'dac_data<23:0>', BUS:18, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:18/23/0/0. PIN dac_data<4>; ENM:'dac_data<23:0>', BUS:19, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:19/23/0/0. PIN dac_data<3>; ENM:'dac_data<23:0>', BUS:20, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:20/23/0/0. PIN dac_data<2>; ENM:'dac_data<23:0>', BUS:21, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:21/23/0/0. PIN dac_data<1>; ENM:'dac_data<23:0>', BUS:22, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:22/23/0/0. PIN dac_data<0>; ENM:'dac_data<23:0>', BUS:23, DIRECTION:OUTPUT, ORIGNAME:dac_data, BUSINFO:23/23/0/0. PIN address_ipads_c_i_0_i_14; DIRECTION:INPUT. PIN address_ipads_c_i_0_i_12; DIRECTION:INPUT. PIN address_ipads_c_i_0_i_10; DIRECTION:INPUT. PIN address_ipads_c_i_0_i_8; DIRECTION:INPUT. PIN address_ipads_c_i_0_i_0; DIRECTION:INPUT. PIN address_ipads_c_14; DIRECTION:INPUT. PIN address_ipads_c_12; DIRECTION:INPUT. PIN address_ipads_c_10; DIRECTION:INPUT. PIN address_ipads_c_8; DIRECTION:INPUT. PIN address_ipads_c_0; DIRECTION:INPUT. PIN address_ipads_c_4; DIRECTION:INPUT. PIN address_ipads_c_2; DIRECTION:INPUT. PIN address_ipads_c_1; DIRECTION:INPUT. PIN address_ipads_c_6; DIRECTION:INPUT. PIN address_ipads_c_5; DIRECTION:INPUT. PIN address_ipads_c_3; DIRECTION:INPUT. PIN data_out_0; DIRECTION:OUTPUT. PIN data_out_1; DIRECTION:OUTPUT. PIN data_out_2; DIRECTION:OUTPUT. PIN data_out_3; DIRECTION:OUTPUT. PIN data_out_4; DIRECTION:OUTPUT. PIN data_out_5; DIRECTION:OUTPUT. PIN data_out_6; DIRECTION:OUTPUT. PIN data_out_7; DIRECTION:OUTPUT. PIN data_out_8; DIRECTION:OUTPUT. PIN data_out_9; DIRECTION:OUTPUT. PIN data_out_10; DIRECTION:OUTPUT. PIN data_out_11; DIRECTION:OUTPUT. PIN data_out_12; DIRECTION:OUTPUT. PIN data_out_13; DIRECTION:OUTPUT. PIN data_out_15; DIRECTION:OUTPUT. PIN dac_transfer_busy; DIRECTION:INPUT. PIN configuration_busy; DIRECTION:INPUT. PIN wr_1_n_ipad_c; DIRECTION:INPUT. PIN wr_0_n_ipad_c; DIRECTION:INPUT. PIN mhz_20_clock_6; DIRECTION:INPUT. PIN mhz_20_clock_5; DIRECTION:INPUT. PIN mhz_20_clock_4; DIRECTION:INPUT. PIN mhz_20_clock_3; DIRECTION:INPUT. PIN mhz_20_clock_2; DIRECTION:INPUT. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN cs_n_ipad_c; DIRECTION:INPUT. PIN rd_n_ipad_c; DIRECTION:INPUT. PIN synced_cs_n; DIRECTION:OUTPUT. PIN mxfe_start; DIRECTION:OUTPUT. PIN reset_0; DIRECTION:INPUT. PIN dac_clock_enable; DIRECTION:OUTPUT. PIN reset_6; DIRECTION:INPUT. PIN dac_start; DIRECTION:OUTPUT. PIN one_n_or_two; DIRECTION:OUTPUT. PIN write_n_or_read; DIRECTION:OUTPUT. PIN reset_7; DIRECTION:INPUT. PIN reset_8; DIRECTION:INPUT. PIN reset_9; DIRECTION:INPUT. PIN reset_10; DIRECTION:INPUT. USE ADLIB:OR2; un3_mxfe_start_0_a2_0. USE ADLIB:NOR2FT; clock_divider_clock_divider_counter_3_i_o3[0]. USE ADLIB:NOR2FT; mxfe_register_2_1_0_a3[2]. USE ADLIB:NOR2FT; mxfe_register_2_1_0_a3[4]. USE ADLIB:DFF; dac_command_register[7]. USE ADLIB:DFF; mxfe_instruction_register[1]. USE ADLIB:OR2; data_out_0_iv_i_a2_0_0[14]. USE ADLIB:DFF; dac_command_register[3]. USE ADLIB:NAND2; mxfe_register_2_m[3]. USE ADLIB:MUX2H; mxfe_register_1_0[6]. USE ADLIB:OR3; data_out_0_iv[1]. USE ADLIB:DFF; dac_data_register[13]. USE ADLIB:OR3; data_out_0_iv[6]. USE ADLIB:MUX2H; mxfe_register_1_0[0]. USE ADLIB:NAND2; dac_data_register_m[5]. USE ADLIB:MUX2H; dac_data_register_0[13]. USE ADLIB:DFF; dac_data_register[6]. USE ADLIB:DFF; dac_data_register[14]. USE ADLIB:MUX2H; dac_command_register_0[4]. USE ADLIB:AND2; data_out[8]. USE ADLIB:XOR2; un3_clock_divider_counter_I_9. USE ADLIB:MUX2H; dac_data_register_0[8]. USE ADLIB:NOR2; data_out_2_sqmuxa_0_a3. USE ADLIB:NOR2FT; dac_command_register_1_0_a3[5]. USE ADLIB:DFF; dac_data_register[10]. USE ADLIB:OR2FT; data_out_0_iv_i_a2_2[14]. USE ADLIB:DFF; mxfe_register_1[3]. USE ADLIB:NOR2FT; mxfe_register_1_1_0_a3[3]. USE ADLIB:DFF; mxfe_register_2[7]. USE ADLIB:AO21TTF; data_out_0_iv_2[5]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[5]. USE ADLIB:MUX2H; dac_data_register_0[9]. USE ADLIB:NAND2; mxfe_register_2_m[2]. USE ADLIB:DFF; dac_data_register[2]. USE ADLIB:AO21TTF; data_out_iv_2[0]. USE ADLIB:NAND2; mxfe_register_2_m[5]. USE ADLIB:OR3; data_out_0_iv_i_a2_0_4[14]. USE ADLIB:DFF; dac_data_register[5]. USE ADLIB:OR3; data_out_0_iv_i_a2_0_6[14]. USE ADLIB:NOR2FT; dac_command_register_1_0_a3[3]. USE ADLIB:OR3FTT; data_out_0_iv[7]. USE ADLIB:NAND2; mxfe_register_2_m[7]. USE ADLIB:AND2; dac_data_register_m[6]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[9]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[2]. USE ADLIB:NOR2FT; mxfe_register_1_1_0_a3[0]. USE ADLIB:DFF; dac_command_register[5]. USE ADLIB:DFF; clock_divider_counter[1]. USE ADLIB:MUX2H; dac_data_register_0[14]. USE ADLIB:NAND2; mxfe_register_2_m[0]. USE ADLIB:DFF; mxfe_instruction_register[7]. USE ADLIB:NOR2FT; mxfe_register_1_1_0_a3[2]. USE ADLIB:NOR2FT; mxfe_instruction_register_1_0_a3[6]. USE ADLIB:NOR2FT; mxfe_register_1_1_0_a3[4]. USE ADLIB:MUX2H; mxfe_register_2_0[1]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[6]. USE ADLIB:NOR2FT; dac_command_register_1_0_a3[0]. USE ADLIB:DFF; mxfe_register_1[5]. USE ADLIB:DFF; mxfe_register_2[5]. USE ADLIB:DFF; dac_data_register[4]. USE ADLIB:MUX2H; mxfe_register_1_0[7]. USE ADLIB:AOI21TTF; data_out_0_iv_1[3]. USE ADLIB:OR2; data_out_4_sqmuxa_0_a3_0. USE ADLIB:NAND3FTT; un4_reset_clock_divider_counter_0_a3. USE ADLIB:NOR2FT; mxfe_instruction_register_1_0_a3[7]. USE ADLIB:DFF; mxfe_instruction_register[4]. USE ADLIB:MUX2H; dac_command_register_0[6]. USE ADLIB:GND; GND_i. USE ADLIB:OR2; data_out_0_iv_i_0[14]. USE ADLIB:NAND2; dac_data_register_m[3]. USE jk_ff; mxfe_busy_ff. USE ADLIB:AND2; clock_divider_clock_divider_counter_3_i[2]. USE ADLIB:MUX2H; mxfe_register_1_0[2]. USE ADLIB:NOR2FT; clock_divider_clock_divider_counter_3_i[0]. USE ADLIB:NOR2; un3_mxfe_start_0_a3. USE ADLIB:OR2; un3_mxfe_start_0_a2. USE ADLIB:NOR2; un1_synced_cs_n_6_i_a3. USE ADLIB:NOR2FT; dac_command_register_1_0_a3[7]. USE ADLIB:MUX2H; dac_command_register_0[2]. USE ADLIB:MUX2H; dac_data_register_0[7]. USE ADLIB:NOR2FT; mxfe_register_2_1_0_a3[6]. USE ADLIB:AOI21TTF; data_out_0_iv_0[4]. USE ADLIB:NOR2; data_out_0_iv_i_a3[14]. USE ADLIB:NOR2FT; data_out_0_iv_i_a2_3[14]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[8]. USE ADLIB:NOR2FT; mxfe_instruction_register_1_0_a3[1]. USE ADLIB:NOR3; data_out_0_iv_i[14]. USE ADLIB:MUX2H; mxfe_instruction_register_0[2]. USE ADLIB:AOI21TTF; data_out_0_iv_1[2]. USE ADLIB:DFF; mxfe_instruction_register[6]. USE ADLIB:MUX2H; dac_data_register_0[2]. USE ADLIB:OR2; un1_data_out_0_sqmuxa_i_i_a2. USE ADLIB:DFF; dac_data_register[12]. USE ADLIB:XOR2; un3_clock_divider_counter_I_13. USE ADLIB:MUX2H; mxfe_register_2_0[5]. USE ADLIB:AOI21TTF; data_out_0_iv_0[7]. USE ADLIB:MUX2H; mxfe_instruction_register_0[6]. USE ADLIB:AND2; un3_clock_divider_counter_I_8. USE ADLIB:OR2; data_out_3_sqmuxa_0_a3_1. USE ADLIB:AND2; clock_divider_clock_divider_counter_3_i[1]. USE ADLIB:AO21TTF; data_out_0_iv_2[1]. USE ADLIB:AOI21TTF; data_out_0_iv_1[5]. USE ADLIB:MUX2H; mxfe_instruction_register_0[0]. USE ADLIB:PWR; PWR_i. USE ADLIB:DFF; dac_data_register[8]. USE ADLIB:NOR2; data_out_6_sqmuxa_0_a3. USE ADLIB:AND2; un3_dac_start_0_a3. USE ADLIB:OR3FTT; data_out_0_iv[2]. USE ADLIB:NOR2FT; data_out_cnst_i_o2[1]. USE ADLIB:MUX2H; dac_data_register_0[5]. USE ADLIB:AO21TTF; data_out_0_iv_2[2]. USE ADLIB:AO21; data_out_0_iv[10]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[12]. USE ADLIB:NOR2; un1_synced_cs_n_6_i_a3_0. USE ADLIB:MUX2H; mxfe_register_1_0[3]. USE ADLIB:AO21TTF; data_out_0_iv_2[6]. USE ADLIB:MUX2H; mxfe_register_1_0[5]. USE ADLIB:AOI21TTF; data_out_iv_1[0]. USE ADLIB:DFF; mxfe_register_2[0]. USE ADLIB:NOR2FT; mxfe_instruction_register_1_0_a3[5]. USE ADLIB:AO21; data_out_0_iv[13]. USE dual_rank_synchronizer_1; sync2. USE ADLIB:NOR2FT; mxfe_instruction_register_1_0_a3[4]. USE ADLIB:OR3; data_out_4_sqmuxa_0_a2. USE ADLIB:AO21; data_out_0_iv[9]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[1]. USE ADLIB:DFF; dac_command_register[1]. USE ADLIB:AND2; clock_divider_clock_divider_counter_3_i[3]. USE ADLIB:MUX2H; mxfe_instruction_register_0[7]. USE ADLIB:AOI21TTF; data_out_0_iv_0[3]. USE ADLIB:MUX2H; dac_command_register_0[7]. USE ADLIB:DFF; dac_data_register[3]. USE ADLIB:AOI21TTF; data_out_0_iv_0[1]. USE ADLIB:DFF; clock_divider_counter[3]. USE ADLIB:XOR2; un3_clock_divider_counter_I_5. USE ADLIB:NOR2FT; mxfe_register_1_1_0_a3[6]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[14]. USE ADLIB:DFF; clock_divider_counter[2]. USE ADLIB:NAND3; data_out_0_iv_i_a3_0_1[14]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[3]. USE ADLIB:AND2FT; un4_reset_clock_divider_counter_0_a3_0. USE dual_rank_synchronizer; sync1. USE ADLIB:NAND2; mxfe_register_2_m[1]. USE ADLIB:DFF; mxfe_register_2[4]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[4]. USE ADLIB:NAND3FFT; un3_mxfe_start_0_a2_1. USE ADLIB:MUX2H; mxfe_register_2_0[6]. USE ADLIB:AOI21TTF; data_out_0_iv_1[1]. USE ADLIB:NOR2FT; un1_synced_cs_n_7_i_a3. USE ADLIB:NOR2; un3_dac_start_0_a2_0. USE ADLIB:NAND2; dac_data_register_m[2]. USE ADLIB:MUX2H; mxfe_register_2_0[0]. USE ADLIB:DFF; dac_command_register[4]. USE ADLIB:NOR2FT; dac_command_register_1_0_a3[6]. USE ADLIB:INV; N_364_i. USE ADLIB:AO21; data_out_0_iv[11]. USE ADLIB:DFF; dac_command_register[6]. USE ADLIB:OR3FTT; data_out_0_iv[5]. USE ADLIB:AOI21TTF; data_out_0_iv_0[2]. USE ADLIB:MUX2H; dac_command_register_0[5]. USE ADLIB:MUX2H; mxfe_register_2_0[3]. USE ADLIB:DFF; mxfe_register_1[0]. USE ADLIB:NOR2FT; mxfe_instruction_register_1_0_a3[3]. USE ADLIB:AOI21TTF; data_out_0_iv_1[4]. USE ADLIB:MUX2H; dac_data_register_0[1]. USE ADLIB:NOR2FT; mxfe_register_2_1_0_a3[7]. USE ADLIB:DFF; mxfe_register_1[4]. USE ADLIB:MUX2H; mxfe_instruction_register_0[1]. USE ADLIB:MUX2H; mxfe_register_1_0[4]. USE ADLIB:OR3; data_out_iv_4[0]. USE ADLIB:OR2; data_out_0_iv_i_o3[14]. USE ADLIB:DFF; clock_divider_counter[0]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[7]. USE ADLIB:MUX2H; dac_data_register_0[10]. USE ADLIB:DFF; dac_data_register[0]. USE ADLIB:NOR2FT; dac_command_register_1_0_a3[1]. USE ADLIB:DFF; mxfe_register_2[6]. USE ADLIB:NOR2FT; mxfe_register_2_1_0_a3[1]. USE ADLIB:MUX2H; dac_data_register_0[0]. USE ADLIB:NOR3FFT; mxfe_busy_m. USE ADLIB:OR3; data_out_0_iv_i_a2_0_2[14]. USE ADLIB:MUX2H; dac_data_register_0[15]. USE ADLIB:NOR2FT; un1_synced_cs_n_9_i_a3. USE ADLIB:DFF; mxfe_register_2[1]. USE ADLIB:DFF; mxfe_instruction_register[2]. USE ADLIB:DFF; dac_data_register[1]. USE ADLIB:NOR2FT; mxfe_register_2_1_0_a3[5]. USE ADLIB:OR2FT; data_out_2_sqmuxa_0_a2. USE ADLIB:MUX2H; mxfe_register_1_0[1]. USE ADLIB:AND2FT; data_out_0_iv_i_a2_6[14]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[13]. USE ADLIB:NOR3FTT; data_out_cnst_m[15]. USE ADLIB:NOR3; data_out_0_iv_i_a3_0[14]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[10]. USE ADLIB:DFF; mxfe_register_1[6]. USE ADLIB:NAND2; dac_data_register_m[7]. USE ADLIB:AND3; un3_clock_divider_counter_I_12. USE ADLIB:MUX2H; mxfe_instruction_register_0[5]. USE ADLIB:MUX2H; mxfe_register_2_0[2]. USE ADLIB:AND2; dac_data_register_m[1]. USE ADLIB:NOR2; data_out_6_sqmuxa_0_a3_0. USE ADLIB:AO21; data_out_0_iv[12]. USE ADLIB:NOR2; data_out_1_sqmuxa_0_a3. USE ADLIB:AOI21TTF; data_out_iv_0[0]. USE ADLIB:NAND2; mxfe_register_2_m[4]. USE ADLIB:NAND2; un1_synced_cs_n_6_i_a3_1. USE ADLIB:NOR3; data_out_4_sqmuxa_0_a3. USE ADLIB:OR3; data_out_0_iv_i_a2_0[14]. USE ADLIB:MUX2H; mxfe_register_2_0[7]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[15]. USE ADLIB:OR3; data_out_iv[0]. USE ADLIB:DFF; dac_data_register[7]. USE ADLIB:NOR2FT; dac_command_register_1_0_a3[4]. USE ADLIB:AO21TTF; data_out_0_iv_2[7]. USE ADLIB:AOI21TTF; data_out_0_iv_2[4]. USE ADLIB:AOI21TTF; data_out_0_iv_1[7]. USE ADLIB:MUX2H; dac_command_register_0[1]. USE ADLIB:MUX2H; dac_command_register_0[0]. USE ADLIB:MUX2H; mxfe_instruction_register_0[3]. USE ADLIB:NOR2FT; mxfe_register_1_1_0_a3[7]. USE ADLIB:OR2FT; data_out_0_iv_i_a2_1[14]. USE ADLIB:AO21TTF; data_out_0_iv[4]. USE falling_edge_detector; fed1. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[11]. USE ADLIB:NOR2; data_out_3_sqmuxa_0_a3. USE ADLIB:DFF; mxfe_register_2[3]. USE ADLIB:DFF; mxfe_register_1[2]. USE ADLIB:NOR2FT; mxfe_instruction_register_1_0_a3[0]. USE ADLIB:AOI21TTF; data_out_0_iv_0[5]. USE ADLIB:DFF; dac_command_register[0]. USE ADLIB:MUX2H; mxfe_instruction_register_0[4]. USE ADLIB:AO21; data_out_0_iv[15]. USE ADLIB:NOR2FT; mxfe_register_2_1_0_a3[3]. USE ADLIB:DFF; mxfe_instruction_register[5]. USE ADLIB:NOR2FT; mxfe_register_1_1_0_a3[1]. USE ADLIB:MUX2H; dac_command_register_0[3]. USE ADLIB:MUX2H; dac_data_register_0[12]. USE ADLIB:NOR3FFT; dac_busy_m. USE ADLIB:MUX2H; mxfe_register_2_0[4]. USE ADLIB:OR3FTT; data_out_0_iv[3]. USE ADLIB:DFF; dac_data_register[15]. USE ADLIB:MUX2H; dac_data_register_0[4]. USE ADLIB:DFF; mxfe_register_2[2]. USE ADLIB:NOR2FT; mxfe_register_1_1_0_a3[5]. USE ADLIB:NOR2FT; dac_data_register_1_0_a3[0]. USE ADLIB:OA21FTF; data_out_0_iv_i_a2[14]. USE ADLIB:AO21TTF; data_out_0_iv_2[3]. USE ADLIB:AOI21TTF; data_out_0_iv_1[6]. USE ADLIB:MUX2H; dac_data_register_0[3]. USE ADLIB:DFF; dac_data_register[9]. USE ADLIB:NOR2FT; mxfe_instruction_register_1_0_a3[2]. USE jk_ff_1; dac_busy_ff. USE ADLIB:AND2; dac_data_register_m[0]. USE ADLIB:DFF; dac_data_register[11]. USE ADLIB:DFF; dac_command_register[2]. USE ADLIB:NOR2FT; dac_command_register_1_0_a3[2]. USE ADLIB:DFF; mxfe_register_1[1]. USE ADLIB:NOR2FT; mxfe_register_2_1_0_a3[0]. USE ADLIB:DFF; mxfe_instruction_register[3]. USE ADLIB:DFF; mxfe_register_1[7]. USE ADLIB:AOI21TTF; data_out_0_iv_0[6]. USE ADLIB:DFF; mxfe_instruction_register[0]. USE ADLIB:MUX2H; dac_data_register_0[11]. USE ADLIB:NOR2FT; un3_dac_start_0_a2. USE ADLIB:NAND2; mxfe_register_2_m[6]. USE ADLIB:NOR2; un1_synced_cs_n_8_i_a3. USE ADLIB:NAND2; data_out_1_sqmuxa_0_a2. USE ADLIB:MUX2H; dac_data_register_0[6]. NET address_ipads_c_i_0_i[14]; address_ipads_c_i_0_i_14, data_out_0_iv_i_a2_0_0[14]:A. NET address_ipads_c_i_0_i[12]; address_ipads_c_i_0_i_12, data_out_0_iv_i_a2_0_2[14]:A. NET address_ipads_c_i_0_i[10]; address_ipads_c_i_0_i_10, data_out_0_iv_i_a2_0_4[14]:A. NET address_ipads_c_i_0_i[8]; address_ipads_c_i_0_i_8, data_out_0_iv_i_a2_0_6[14]:A. NET address_ipads_c_i_0_i[0]; address_ipads_c_i_0_i_0, data_out_0_iv_i_a2_0[14]:A. NET address_ipads_c[15]; address_ipads_c_14, data_out_0_iv_i_a2_0_0[14]:B. NET address_ipads_c[13]; address_ipads_c_12, data_out_0_iv_i_a2_0_2[14]:C. NET address_ipads_c[11]; address_ipads_c_10, data_out_0_iv_i_a2_0_4[14]:C. NET address_ipads_c[9]; address_ipads_c_8, data_out_0_iv_i_a2_0_6[14]:C. NET address_ipads_c[1]; address_ipads_c_0, data_out_0_iv_i_a2_0[14]:C. NET address_ipads_c[5]; address_ipads_c_4, un3_dac_start_0_a2:A, un1_synced_cs_n_6_i_a3_1:B, data_out_2_sqmuxa_0_a2:B, data_out_0_iv_i_a2_3[14]:B, un3_mxfe_start_0_a2:A. NET address_ipads_c[3]; address_ipads_c_2, un3_dac_start_0_a2:B, un1_synced_cs_n_6_i_a3_1:A, data_out_2_sqmuxa_0_a2:A, un3_mxfe_start_0_a2:B. NET address_ipads_c[2]; address_ipads_c_1, data_out_1_sqmuxa_0_a2:B, data_out_0_iv_i_a2_1[14]:B, data_out_0_iv_i_a2_2[14]:B. NET address_ipads_c[7]; address_ipads_c_6, data_out_0_iv_i_a3_0_1[14]:C, data_out_4_sqmuxa_0_a2:C. NET address_ipads_c[6]; address_ipads_c_5, data_out_0_iv_i_a3_0_1[14]:B, data_out_4_sqmuxa_0_a2:B. NET address_ipads_c[4]; address_ipads_c_3, data_out_0_iv_i_a2_6[14]:B, data_out_0_iv_i_a3_0_1[14]:A, data_out_0_iv_i_a2_3[14]:A, data_out_4_sqmuxa_0_a3_0:B. NET mxfe_register_data[0]; mxfe_register_data<0>, data_out_iv_0[0]:B. NET mxfe_register_data[1]; mxfe_register_data<1>, data_out_0_iv_0[1]:B. NET mxfe_register_data[2]; mxfe_register_data<2>, data_out_0_iv_0[2]:B. NET mxfe_register_data[3]; mxfe_register_data<3>, data_out_0_iv_0[3]:B. NET mxfe_register_data[4]; mxfe_register_data<4>, data_out_0_iv_0[4]:B. NET mxfe_register_data[5]; mxfe_register_data<5>, data_out_0_iv_0[5]:B. NET mxfe_register_data[6]; mxfe_register_data<6>, data_out_0_iv_0[6]:B. NET mxfe_register_data[7]; mxfe_register_data<7>, data_out_0_iv_0[7]:B. NET data_out[0]; data_out_0, data_out_iv[0]:Y. NET data_out[1]; data_out_1, data_out_0_iv[1]:Y. NET data_out[2]; data_out_2, data_out_0_iv[2]:Y. NET data_out[3]; data_out_3, data_out_0_iv[3]:Y. NET data_out[4]; data_out_4, data_out_0_iv[4]:Y. NET data_out[5]; data_out_5, data_out_0_iv[5]:Y. NET data_out[6]; data_out_6, data_out_0_iv[6]:Y. NET data_out[7]; data_out_7, data_out_0_iv[7]:Y. NET data_out[8]; data_out_8, data_out[8]:Y. NET data_out[9]; data_out_9, data_out_0_iv[9]:Y. NET data_out[10]; data_out_10, data_out_0_iv[10]:Y. NET data_out[11]; data_out_11, data_out_0_iv[11]:Y. NET data_out[12]; data_out_12, data_out_0_iv[12]:Y. NET data_out[13]; data_out_13, data_out_0_iv[13]:Y. NET data_out[15]; data_out_15, data_out_0_iv[15]:Y. NET data_out_0_iv_i[14]; data_out_0_iv_i<14>, data_out_0_iv_i[14]:Y. NET mxfe_configuration_data[0]; mxfe_configuration_data<0>, mxfe_register_2_0[0]:A, mxfe_register_2[0]:Q, mxfe_register_2_m[0]:B. NET mxfe_configuration_data[1]; mxfe_configuration_data<1>, mxfe_register_2[1]:Q, mxfe_register_2_m[1]:B, mxfe_register_2_0[1]:A. NET mxfe_configuration_data[2]; mxfe_configuration_data<2>, mxfe_register_2[2]:Q, mxfe_register_2_0[2]:A, mxfe_register_2_m[2]:B. NET mxfe_configuration_data[3]; mxfe_configuration_data<3>, mxfe_register_2[3]:Q, mxfe_register_2_0[3]:A, mxfe_register_2_m[3]:B. NET mxfe_configuration_data[4]; mxfe_configuration_data<4>, mxfe_register_2_0[4]:A, mxfe_register_2_m[4]:B, mxfe_register_2[4]:Q. NET mxfe_configuration_data[5]; mxfe_configuration_data<5>, mxfe_register_2_0[5]:A, mxfe_register_2[5]:Q, mxfe_register_2_m[5]:B. NET mxfe_configuration_data[6]; mxfe_configuration_data<6>, mxfe_register_2_m[6]:B, mxfe_register_2[6]:Q, mxfe_register_2_0[6]:A. NET mxfe_configuration_data[7]; mxfe_configuration_data<7>, mxfe_register_2_0[7]:A, mxfe_register_2_m[7]:B, mxfe_register_2[7]:Q. NET mxfe_configuration_data[8]; mxfe_configuration_data<8>, mxfe_register_1[0]:Q, data_out_iv_1[0]:B, mxfe_register_1_0[0]: A. NET mxfe_configuration_data[9]; mxfe_configuration_data<9>, mxfe_register_1[1]:Q, mxfe_register_1_0[1]:A, data_out_0_iv_1[1]:B. NET mxfe_configuration_data[10]; mxfe_configuration_data<10>, mxfe_register_1[2]:Q, data_out_0_iv_1[2]:B, mxfe_register_1_0[2]:A. NET mxfe_configuration_data[11]; mxfe_configuration_data<11>, mxfe_register_1_0[3]:A, data_out_0_iv_1[3]:B, mxfe_register_1[3]:Q. NET mxfe_configuration_data[12]; mxfe_configuration_data<12>, mxfe_register_1_0[4]:A, mxfe_register_1[4]:Q, data_out_0_iv_1[4]:B. NET mxfe_configuration_data[13]; mxfe_configuration_data<13>, mxfe_register_1_0[5]:A, data_out_0_iv_1[5]:B, mxfe_register_1[5]:Q. NET mxfe_configuration_data[14]; mxfe_configuration_data<14>, data_out_0_iv_1[6]:B, mxfe_register_1[6]:Q, mxfe_register_1_0[6]:A. NET mxfe_configuration_data[15]; mxfe_configuration_data<15>, mxfe_register_1[7]:Q, data_out_0_iv_1[7]:B, mxfe_register_1_0[7]:A. NET mxfe_configuration_data[16]; mxfe_configuration_data<16>, mxfe_instruction_register[0]:Q, mxfe_instruction_register_0[0]: A, data_out_iv_2[0]:B. NET mxfe_configuration_data[17]; mxfe_configuration_data<17>, mxfe_instruction_register_0[1]:A, data_out_0_iv_2[1]:B, mxfe_instruction_register[1]:Q. NET mxfe_configuration_data[18]; mxfe_configuration_data<18>, mxfe_instruction_register[2]:Q, data_out_0_iv_2[2]:B, mxfe_instruction_register_0[2]:A. NET mxfe_configuration_data[19]; mxfe_configuration_data<19>, mxfe_instruction_register[3]:Q, data_out_0_iv_2[3]:B, mxfe_instruction_register_0[3]:A. NET mxfe_configuration_data[20]; mxfe_configuration_data<20>, mxfe_instruction_register_0[4]:A, data_out_0_iv_2[4]:B, mxfe_instruction_register[4]:Q. NET mxfe_configuration_data[21]; mxfe_configuration_data<21>, mxfe_instruction_register[5]:Q, mxfe_instruction_register_0[5]: A, data_out_0_iv_2[5]:B. NET data_iopads_in[0]; data_iopads_in<0>, dac_command_register_0[0]:B, dac_data_register_0[0]:B, mxfe_register_2_0[0]:B, mxfe_instruction_register_0[0]:B, mxfe_register_1_0[0]:B. NET data_iopads_in[1]; data_iopads_in<1>, dac_command_register_0[1]:B, mxfe_register_1_0[1]:B, mxfe_instruction_register_0[1]:B, dac_data_register_0[1]:B, mxfe_register_2_0[1]:B. NET data_iopads_in[2]; data_iopads_in<2>, mxfe_register_2_0[2]:B, dac_data_register_0[2]:B, mxfe_instruction_register_0[2]:B, dac_command_register_0[2]:B, mxfe_register_1_0[2]:B. NET data_iopads_in[3]; data_iopads_in<3>, dac_data_register_0[3]: B, dac_command_register_0[3]:B, mxfe_instruction_register_0[3]: B, mxfe_register_2_0[3]:B, mxfe_register_1_0[3]:B. NET data_iopads_in[4]; data_iopads_in<4>, dac_data_register_0[4]: B, mxfe_register_2_0[4]:B, mxfe_instruction_register_0[4]:B, mxfe_register_1_0[4]:B, dac_command_register_0[4]:B. NET data_iopads_in[5]; data_iopads_in<5>, mxfe_instruction_register_0[5]:B, dac_command_register_0[5]:B, mxfe_register_1_0[5]:B, dac_data_register_0[5]:B, mxfe_register_2_0[5]:B. NET data_iopads_in[6]; data_iopads_in<6>, dac_data_register_0[6]: B, mxfe_register_2_0[6]:B, mxfe_instruction_register_0[6]:B, dac_command_register_0[6]:B, mxfe_register_1_0[6]:B. NET data_iopads_in[7]; data_iopads_in<7>, mxfe_register_2_0[7]:B, dac_command_register_0[7]:B, mxfe_instruction_register_0[7]:B, dac_data_register_0[7]:B, mxfe_register_1_0[7]:B. NET data_iopads_in[8]; data_iopads_in<8>, dac_data_register_0[8]: B. NET data_iopads_in[9]; data_iopads_in<9>, dac_data_register_0[9]: B. NET data_iopads_in[10]; data_iopads_in<10>, dac_data_register_0[10]:B. NET data_iopads_in[11]; data_iopads_in<11>, dac_data_register_0[11]:B. NET data_iopads_in[12]; data_iopads_in<12>, dac_data_register_0[12]:B. NET data_iopads_in[13]; data_iopads_in<13>, dac_data_register_0[13]:B. NET data_iopads_in[14]; data_iopads_in<14>, dac_data_register_0[14]:B. NET data_iopads_in[15]; data_iopads_in<15>, dac_data_register_0[15]:B. NET dac_data[0]; dac_data<0>, dac_data_register_m[0]:B, dac_data_register_0[0]:A, dac_data_register[0]:Q. NET dac_data[1]; dac_data<1>, dac_data_register_m[1]:B, dac_data_register[1]:Q, dac_data_register_0[1]:A. NET dac_data[2]; dac_data<2>, dac_data_register_m[2]:B, dac_data_register_0[2]:A, dac_data_register[2]:Q. NET dac_data[3]; dac_data<3>, dac_data_register_0[3]:A, dac_data_register[3]:Q, dac_data_register_m[3]:B. NET dac_data[4]; dac_data<4>, dac_data_register_0[4]:A, data_out_0_iv[4]:B, dac_data_register[4]:Q. NET dac_data[5]; dac_data<5>, dac_data_register_0[5]:A, dac_data_register[5]:Q, dac_data_register_m[5]:B. NET dac_data[6]; dac_data<6>, dac_data_register_0[6]:A, dac_data_register_m[6]:B, dac_data_register[6]:Q. NET dac_data[7]; dac_data<7>, dac_data_register[7]:Q, dac_data_register_m[7]:B, dac_data_register_0[7]:A. NET dac_data[8]; dac_data<8>, dac_data_register[8]:Q, dac_data_register_0[8]:A, data_out[8]:B. NET dac_data[9]; dac_data<9>, dac_data_register[9]:Q, data_out_0_iv[9]:B, dac_data_register_0[9]:A. NET dac_data[10]; dac_data<10>, dac_data_register_0[10]:A, data_out_0_iv[10]:B, dac_data_register[10]:Q. NET dac_data[11]; dac_data<11>, dac_data_register_0[11]:A, dac_data_register[11]:Q, data_out_0_iv[11]:B. NET dac_data[12]; dac_data<12>, dac_data_register_0[12]:A, data_out_0_iv[12]:B, dac_data_register[12]:Q. NET dac_data[13]; dac_data<13>, data_out_0_iv[13]:B, dac_data_register_0[13]:A, dac_data_register[13]:Q. NET dac_data[14]; dac_data<14>, data_out_0_iv_i_a3[14]:B, dac_data_register_0[14]:A, dac_data_register[14]:Q. NET dac_data[15]; dac_data<15>, dac_data_register[15]:Q, data_out_0_iv[15]:B, dac_data_register_0[15]:A. NET dac_data[16]; dac_data<16>, dac_command_register[0]:Q, dac_command_register_0[0]:A. NET dac_data[17]; dac_data<17>, dac_command_register_0[1]:A, dac_command_register[1]:Q. NET dac_data[18]; dac_data<18>, dac_command_register[2]:Q, dac_command_register_0[2]:A. NET dac_data[19]; dac_data<19>, dac_command_register_0[3]:A, dac_command_register[3]:Q. NET dac_data[20]; dac_data<20>, dac_command_register[4]:Q, dac_command_register_0[4]:A. NET dac_data[21]; dac_data<21>, dac_command_register_0[5]:A, dac_command_register[5]:Q. NET dac_data[22]; dac_data<22>, dac_command_register[6]:Q, dac_command_register_0[6]:A. NET dac_data[23]; dac_data<23>, dac_command_register_0[7]:A, dac_command_register[7]:Q. NET dac_transfer_busy; dac_transfer_busy, dac_busy_ff: dac_transfer_busy. NET configuration_busy; configuration_busy, mxfe_busy_ff: configuration_busy. NET wr_1_n_ipad_c; wr_1_n_ipad_c, sync2:wr_1_n_ipad_c. NET wr_0_n_ipad_c; wr_0_n_ipad_c, sync2:wr_0_n_ipad_c. NET mhz_20_clock_6; mhz_20_clock_6, clock_divider_counter[2]:CLK, clock_divider_counter[3]:CLK, clock_divider_counter[1]:CLK. NET mhz_20_clock_5; mhz_20_clock_5, dac_data_register[11]:CLK, dac_data_register[9]:CLK, dac_data_register[15]:CLK, dac_data_register[7]:CLK, clock_divider_counter[0]:CLK, dac_data_register[8]:CLK, dac_data_register[12]:CLK, dac_data_register[5]:CLK, dac_data_register[10]:CLK, dac_data_register[14]:CLK, dac_data_register[6]:CLK, dac_data_register[13]:CLK. NET mhz_20_clock_4; mhz_20_clock_4, mxfe_register_2[2]:CLK, mxfe_register_2[3]:CLK, dac_data_register[1]:CLK, mxfe_register_2[1]:CLK, mxfe_register_2[6]:CLK, dac_data_register[0]:CLK, mxfe_register_2[4]:CLK, dac_data_register[3]:CLK, dac_data_register[4]:CLK, mxfe_register_2[5]:CLK, dac_data_register[2]:CLK, mxfe_register_2[7]:CLK. NET mhz_20_clock_3; mhz_20_clock_3, mxfe_register_1[7]:CLK, mxfe_register_1[1]:CLK, mxfe_instruction_register[5]:CLK, mxfe_register_1[2]:CLK, mxfe_register_1[6]:CLK, mxfe_register_1[4]:CLK, mxfe_register_1[0]:CLK, mxfe_register_2[0]:CLK, mxfe_instruction_register[6]:CLK, mxfe_register_1[5]:CLK, mxfe_instruction_register[7]:CLK, mxfe_register_1[3]:CLK. NET mhz_20_clock_2; mhz_20_clock_2, mxfe_instruction_register[0]: CLK, mxfe_instruction_register[3]:CLK, dac_command_register[2]: CLK, mxfe_instruction_register[2]:CLK, dac_command_register[6]: CLK, dac_command_register[4]:CLK, dac_command_register[1]:CLK, mxfe_instruction_register[4]:CLK, dac_command_register[5]:CLK, dac_command_register[3]:CLK, mxfe_instruction_register[1]:CLK, dac_command_register[7]:CLK. NET mhz_20_clock_1; mhz_20_clock_1, dac_busy_ff:mhz_20_clock_1, dac_command_register[0]:CLK, fed1:mhz_20_clock_1, sync1: mhz_20_clock_1, sync2:mhz_20_clock_1, mxfe_busy_ff: mhz_20_clock_1. NET cs_n_ipad_c; cs_n_ipad_c, data_out_0_iv_i_o3[14]:B, sync1: cs_n_ipad_c. NET rd_n_ipad_c; rd_n_ipad_c, data_out_0_iv_i_o3[14]:A. NET synced_cs_n; synced_cs_n, un3_mxfe_start_0_a2_1:A, sync1: synced_cs_n. NET mxfe_start; mxfe_start, un3_mxfe_start_0_a3:Y, mxfe_busy_ff: mxfe_start. NET reset_0; reset_0, clock_divider_clock_divider_counter_3_i_o3[0]:B. NET dac_clock_enable; dac_clock_enable, un4_reset_clock_divider_counter_0_a3:Y, clock_divider_clock_divider_counter_3_i_o3[0]:A. NET reset_6; reset_6, dac_command_register_1_0_a3[2]:B, dac_command_register_1_0_a3[4]:B, dac_command_register_1_0_a3[1]:B, dac_command_register_1_0_a3[6]:B, dac_command_register_1_0_a3[0]:B, dac_command_register_1_0_a3[3]:B, dac_command_register_1_0_a3[5]:B. NET dac_start; dac_start, dac_busy_ff:dac_start, dac_command_register_0[3]:S, dac_command_register_0[0]:S, dac_command_register_0[1]:S, dac_command_register_0[5]:S, dac_command_register_0[7]:S, un3_dac_start_0_a3:Y, dac_command_register_0[2]:S, dac_command_register_0[6]:S, dac_command_register_0[4]:S. NET one_n_or_two; one_n_or_two, data_out_0_iv_2[6]:B, mxfe_instruction_register_0[6]:A, mxfe_instruction_register[6]: Q. NET write_n_or_read; write_n_or_read, data_out_0_iv_2[7]:B, mxfe_instruction_register_0[7]:A, mxfe_instruction_register[7]: Q. NET reset_7; reset_7, mxfe_instruction_register_1_0_a3[2]:B, mxfe_register_1_1_0_a3[1]:B, mxfe_instruction_register_1_0_a3[0]:B, mxfe_instruction_register_1_0_a3[3]:B, mxfe_instruction_register_1_0_a3[4]:B, mxfe_instruction_register_1_0_a3[5]:B, mxfe_instruction_register_1_0_a3[1]:B, dac_command_register_1_0_a3[7]:B, mxfe_instruction_register_1_0_a3[7]:B, mxfe_instruction_register_1_0_a3[6]:B, mxfe_register_1_1_0_a3[2]:B, mxfe_register_1_1_0_a3[0]:B. NET reset_8; reset_8, mxfe_register_2_1_0_a3[0]:B, mxfe_register_1_1_0_a3[5]:B, mxfe_register_2_1_0_a3[3]:B, mxfe_register_1_1_0_a3[7]:B, mxfe_register_2_1_0_a3[5]:B, mxfe_register_2_1_0_a3[1]:B, mxfe_register_1_1_0_a3[6]:B, mxfe_register_2_1_0_a3[6]:B, mxfe_register_1_1_0_a3[4]:B, mxfe_register_1_1_0_a3[3]:B, mxfe_register_2_1_0_a3[4]:B, mxfe_register_2_1_0_a3[2]:B. NET reset_9; reset_9, dac_data_register_1_0_a3[0]:B, dac_data_register_1_0_a3[10]:B, dac_data_register_1_0_a3[7]:B, mxfe_register_2_1_0_a3[7]:B, dac_data_register_1_0_a3[4]:B, dac_data_register_1_0_a3[3]:B, dac_data_register_1_0_a3[1]:B, dac_data_register_1_0_a3[8]:B, dac_data_register_1_0_a3[6]:B, dac_data_register_1_0_a3[2]:B, dac_data_register_1_0_a3[9]:B, dac_data_register_1_0_a3[5]:B. NET reset_10; reset_10, dac_busy_ff:reset_10, dac_data_register_1_0_a3[11]:B, fed1:reset_10, dac_data_register_1_0_a3[15]:B, dac_data_register_1_0_a3[13]:B, sync1:reset_10, dac_data_register_1_0_a3[14]:B, sync2:reset_10, dac_data_register_1_0_a3[12]:B, mxfe_busy_ff:reset_10. NET data_out_6_sqmuxa_0; data_out[8]:A, data_out_0_iv[15]:A, data_out_0_iv[12]:A, data_out_6_sqmuxa_0_a3_0:Y, dac_data_register_m[7]:A, data_out_0_iv[11]:A, data_out_0_iv[9]: A, data_out_0_iv[13]:A, data_out_0_iv[10]:A. NET N_297_1; data_out_6_sqmuxa_0_a3:A, un1_synced_cs_n_6_i_a3_1: Y, data_out_6_sqmuxa_0_a3_0:A, un1_synced_cs_n_6_i_a3_0:B, un1_synced_cs_n_6_i_a3:B. NET un1_data_out_0_sqmuxa_i_i_a2; N_364_i:A, dac_busy_m:C, data_out_6_sqmuxa_0_a3_0:B, data_out_cnst_m[15]:A, data_out_2_sqmuxa_0_a3:B, data_out_6_sqmuxa_0_a3:B, un1_data_out_0_sqmuxa_i_i_a2:Y. NET N_297_0; dac_data_register_0[13]:S, dac_data_register_0[11]: S, dac_data_register_0[12]:S, dac_data_register_0[15]:S, dac_data_register_0[10]:S, un1_synced_cs_n_6_i_a3_0:Y, dac_data_register_0[7]:S, dac_data_register_0[14]:S, dac_data_register_0[9]:S, dac_data_register_0[8]:S. NET un3_mxfe_start_0_a2_0; un1_synced_cs_n_6_i_a3:A, un1_synced_cs_n_8_i_a3:A, un1_synced_cs_n_6_i_a3_0:A, un3_mxfe_start_0_a3:B, un3_mxfe_start_0_a2_0:Y. NET dac_data_register_1_0_a3[15]; dac_data_register[15]:D, dac_data_register_1_0_a3[15]:Y. NET dac_data_register_0[15]; dac_data_register_1_0_a3[15]:A, dac_data_register_0[15]:Y. NET dac_data_register_1_0_a3[14]; dac_data_register[14]:D, dac_data_register_1_0_a3[14]:Y. NET dac_data_register_0[14]; dac_data_register_1_0_a3[14]:A, dac_data_register_0[14]:Y. NET dac_data_register_1_0_a3[13]; dac_data_register[13]:D, dac_data_register_1_0_a3[13]:Y. NET dac_data_register_0[13]; dac_data_register_1_0_a3[13]:A, dac_data_register_0[13]:Y. NET dac_data_register_1_0_a3[12]; dac_data_register[12]:D, dac_data_register_1_0_a3[12]:Y. NET dac_data_register_0[12]; dac_data_register_1_0_a3[12]:A, dac_data_register_0[12]:Y. NET dac_data_register_1_0_a3[11]; dac_data_register[11]:D, dac_data_register_1_0_a3[11]:Y. NET dac_data_register_0[11]; dac_data_register_1_0_a3[11]:A, dac_data_register_0[11]:Y. NET dac_data_register_1_0_a3[10]; dac_data_register[10]:D, dac_data_register_1_0_a3[10]:Y. NET dac_data_register_0[10]; dac_data_register_1_0_a3[10]:A, dac_data_register_0[10]:Y. NET dac_data_register_1_0_a3[9]; dac_data_register[9]:D, dac_data_register_1_0_a3[9]:Y. NET dac_data_register_0[9]; dac_data_register_1_0_a3[9]:A, dac_data_register_0[9]:Y. NET dac_data_register_1_0_a3[8]; dac_data_register[8]:D, dac_data_register_1_0_a3[8]:Y. NET dac_data_register_0[8]; dac_data_register_1_0_a3[8]:A, dac_data_register_0[8]:Y. NET dac_data_register_1_0_a3[7]; dac_data_register[7]:D, dac_data_register_1_0_a3[7]:Y. NET dac_data_register_0[7]; dac_data_register_1_0_a3[7]:A, dac_data_register_0[7]:Y. NET dac_data_register_1_0_a3[6]; dac_data_register[6]:D, dac_data_register_1_0_a3[6]:Y. NET N_13; dac_data_register_1_0_a3[6]:A, dac_data_register_0[6]: Y. NET un1_synced_cs_n_6_i_a3; dac_data_register_0[2]:S, dac_data_register_0[6]:S, dac_data_register_0[3]:S, dac_data_register_0[4]:S, dac_data_register_0[0]:S, dac_data_register_0[1]:S, dac_data_register_0[5]:S, un1_synced_cs_n_6_i_a3:Y. NET dac_data_register_1_0_a3[5]; dac_data_register[5]:D, dac_data_register_1_0_a3[5]:Y. NET dac_data_register_0[5]; dac_data_register_1_0_a3[5]:A, dac_data_register_0[5]:Y. NET dac_data_register_1_0_a3[4]; dac_data_register[4]:D, dac_data_register_1_0_a3[4]:Y. NET dac_data_register_0[4]; dac_data_register_1_0_a3[4]:A, dac_data_register_0[4]:Y. NET dac_data_register_1_0_a3[3]; dac_data_register[3]:D, dac_data_register_1_0_a3[3]:Y. NET N_10; dac_data_register_1_0_a3[3]:A, dac_data_register_0[3]: Y. NET dac_data_register_1_0_a3[2]; dac_data_register[2]:D, dac_data_register_1_0_a3[2]:Y. NET dac_data_register_0[2]; dac_data_register_1_0_a3[2]:A, dac_data_register_0[2]:Y. NET dac_data_register_1_0_a3[1]; dac_data_register[1]:D, dac_data_register_1_0_a3[1]:Y. NET dac_data_register_0[1]; dac_data_register_1_0_a3[1]:A, dac_data_register_0[1]:Y. NET dac_data_register_1_0_a3[0]; dac_data_register[0]:D, dac_data_register_1_0_a3[0]:Y. NET dac_data_register_0[0]; dac_data_register_1_0_a3[0]:A, dac_data_register_0[0]:Y. NET mxfe_register_2_1_0_a3[7]; mxfe_register_2[7]:D, mxfe_register_2_1_0_a3[7]:Y. NET mxfe_register_2_0[7]; mxfe_register_2_1_0_a3[7]:A, mxfe_register_2_0[7]:Y. NET un1_synced_cs_n_7_i_a3; mxfe_register_2_0[1]:S, mxfe_register_2_0[4]:S, mxfe_register_2_0[7]:S, mxfe_register_2_0[2]:S, mxfe_register_2_0[3]:S, mxfe_register_2_0[0]:S, un1_synced_cs_n_7_i_a3:Y, mxfe_register_2_0[6]:S, mxfe_register_2_0[5]:S. NET mxfe_register_2_1_0_a3[6]; mxfe_register_2[6]:D, mxfe_register_2_1_0_a3[6]:Y. NET N_29; mxfe_register_2_1_0_a3[6]:A, mxfe_register_2_0[6]:Y. NET mxfe_register_2_1_0_a3[5]; mxfe_register_2[5]:D, mxfe_register_2_1_0_a3[5]:Y. NET mxfe_register_2_0[5]; mxfe_register_2_1_0_a3[5]:A, mxfe_register_2_0[5]:Y. NET mxfe_register_2_1_0_a3[4]; mxfe_register_2[4]:D, mxfe_register_2_1_0_a3[4]:Y. NET mxfe_register_2_0[4]; mxfe_register_2_1_0_a3[4]:A, mxfe_register_2_0[4]:Y. NET mxfe_register_2_1_0_a3[3]; mxfe_register_2[3]:D, mxfe_register_2_1_0_a3[3]:Y. NET mxfe_register_2_0[3]; mxfe_register_2_1_0_a3[3]:A, mxfe_register_2_0[3]:Y. NET mxfe_register_2_1_0_a3[2]; mxfe_register_2[2]:D, mxfe_register_2_1_0_a3[2]:Y. NET mxfe_register_2_0[2]; mxfe_register_2_1_0_a3[2]:A, mxfe_register_2_0[2]:Y. NET mxfe_register_2_1_0_a3[1]; mxfe_register_2[1]:D, mxfe_register_2_1_0_a3[1]:Y. NET mxfe_register_2_0[1]; mxfe_register_2_1_0_a3[1]:A, mxfe_register_2_0[1]:Y. NET mxfe_register_2_1_0_a3[0]; mxfe_register_2[0]:D, mxfe_register_2_1_0_a3[0]:Y. NET mxfe_register_2_0[0]; mxfe_register_2_1_0_a3[0]:A, mxfe_register_2_0[0]:Y. NET un3_dac_start_0_a2_0; un1_synced_cs_n_7_i_a3:A, un1_synced_cs_n_9_i_a3:A, un3_dac_start_0_a2_0:Y, un3_dac_start_0_a3:B. NET data_out_2_sqmuxa_0_a2; data_out_2_sqmuxa_0_a3:A, un1_synced_cs_n_8_i_a3:B, data_out_3_sqmuxa_0_a3:A, data_out_2_sqmuxa_0_a2:Y, un1_synced_cs_n_7_i_a3:B. NET mxfe_register_1_1_0_a3[7]; mxfe_register_1[7]:D, mxfe_register_1_1_0_a3[7]:Y. NET mxfe_register_1_0[7]; mxfe_register_1_1_0_a3[7]:A, mxfe_register_1_0[7]:Y. NET un1_synced_cs_n_8_i_a3; mxfe_register_1_0[6]:S, un1_synced_cs_n_8_i_a3:Y, mxfe_register_1_0[1]:S, mxfe_register_1_0[4]:S, mxfe_register_1_0[5]:S, mxfe_register_1_0[3]:S, mxfe_register_1_0[2]:S, mxfe_register_1_0[7]:S, mxfe_register_1_0[0]:S. NET mxfe_register_1_1_0_a3[6]; mxfe_register_1[6]:D, mxfe_register_1_1_0_a3[6]:Y. NET N_37; mxfe_register_1_1_0_a3[6]:A, mxfe_register_1_0[6]:Y. NET mxfe_register_1_1_0_a3[5]; mxfe_register_1[5]:D, mxfe_register_1_1_0_a3[5]:Y. NET mxfe_register_1_0[5]; mxfe_register_1_1_0_a3[5]:A, mxfe_register_1_0[5]:Y. NET mxfe_register_1_1_0_a3[4]; mxfe_register_1[4]:D, mxfe_register_1_1_0_a3[4]:Y. NET mxfe_register_1_0[4]; mxfe_register_1_1_0_a3[4]:A, mxfe_register_1_0[4]:Y. NET mxfe_register_1_1_0_a3[3]; mxfe_register_1[3]:D, mxfe_register_1_1_0_a3[3]:Y. NET mxfe_register_1_0[3]; mxfe_register_1_1_0_a3[3]:A, mxfe_register_1_0[3]:Y. NET mxfe_register_1_1_0_a3[2]; mxfe_register_1[2]:D, mxfe_register_1_1_0_a3[2]:Y. NET mxfe_register_1_0[2]; mxfe_register_1_1_0_a3[2]:A, mxfe_register_1_0[2]:Y. NET mxfe_register_1_1_0_a3[1]; mxfe_register_1[1]:D, mxfe_register_1_1_0_a3[1]:Y. NET mxfe_register_1_0[1]; mxfe_register_1_1_0_a3[1]:A, mxfe_register_1_0[1]:Y. NET mxfe_register_1_1_0_a3[0]; mxfe_register_1[0]:D, mxfe_register_1_1_0_a3[0]:Y. NET N_31; mxfe_register_1_1_0_a3[0]:A, mxfe_register_1_0[0]:Y. NET mxfe_instruction_register_1_0_a3[7]; mxfe_instruction_register[7]:D, mxfe_instruction_register_1_0_a3[7]:Y. NET mxfe_instruction_register_0[7]; mxfe_instruction_register_1_0_a3[7]:A, mxfe_instruction_register_0[7]:Y. NET un1_synced_cs_n_9_i_a3; mxfe_instruction_register_0[2]:S, mxfe_instruction_register_0[4]:S, mxfe_instruction_register_0[3]:S, mxfe_instruction_register_0[5]:S, un1_synced_cs_n_9_i_a3:Y, mxfe_instruction_register_0[1]:S, mxfe_instruction_register_0[7]:S, mxfe_instruction_register_0[0]:S, mxfe_instruction_register_0[6]:S. NET mxfe_instruction_register_1_0_a3[6]; mxfe_instruction_register[6]:D, mxfe_instruction_register_1_0_a3[6]:Y. NET N_45; mxfe_instruction_register_1_0_a3[6]:A, mxfe_instruction_register_0[6]:Y. NET mxfe_instruction_register_1_0_a3[5]; mxfe_instruction_register[5]:D, mxfe_instruction_register_1_0_a3[5]:Y. NET mxfe_instruction_register_0[5]; mxfe_instruction_register_1_0_a3[5]:A, mxfe_instruction_register_0[5]:Y. NET mxfe_instruction_register_1_0_a3[4]; mxfe_instruction_register[4]:D, mxfe_instruction_register_1_0_a3[4]:Y. NET mxfe_instruction_register_0[4]; mxfe_instruction_register_1_0_a3[4]:A, mxfe_instruction_register_0[4]:Y. NET mxfe_instruction_register_1_0_a3[3]; mxfe_instruction_register[3]:D, mxfe_instruction_register_1_0_a3[3]:Y. NET mxfe_instruction_register_0[3]; mxfe_instruction_register_1_0_a3[3]:A, mxfe_instruction_register_0[3]:Y. NET mxfe_instruction_register_1_0_a3[2]; mxfe_instruction_register[2]:D, mxfe_instruction_register_1_0_a3[2]:Y. NET mxfe_instruction_register_0[2]; mxfe_instruction_register_1_0_a3[2]:A, mxfe_instruction_register_0[2]:Y. NET mxfe_instruction_register_1_0_a3[1]; mxfe_instruction_register[1]:D, mxfe_instruction_register_1_0_a3[1]:Y. NET mxfe_instruction_register_0[1]; mxfe_instruction_register_1_0_a3[1]:A, mxfe_instruction_register_0[1]:Y. NET mxfe_instruction_register_1_0_a3[0]; mxfe_instruction_register[0]:D, mxfe_instruction_register_1_0_a3[0]:Y. NET mxfe_instruction_register_0[0]; mxfe_instruction_register_1_0_a3[0]:A, mxfe_instruction_register_0[0]:Y. NET un3_mxfe_start_0_a2; un3_mxfe_start_0_a3:A, data_out_1_sqmuxa_0_a3:A, un1_synced_cs_n_9_i_a3:B, mxfe_busy_m: C, un3_mxfe_start_0_a2:Y. NET dac_command_register_1_0_a3[7]; dac_command_register[7]:D, dac_command_register_1_0_a3[7]:Y. NET dac_command_register_0[7]; dac_command_register_1_0_a3[7]:A, dac_command_register_0[7]:Y. NET dac_command_register_1_0_a3[6]; dac_command_register[6]:D, dac_command_register_1_0_a3[6]:Y. NET dac_command_register_0[6]; dac_command_register_1_0_a3[6]:A, dac_command_register_0[6]:Y. NET dac_command_register_1_0_a3[5]; dac_command_register[5]:D, dac_command_register_1_0_a3[5]:Y. NET dac_command_register_0[5]; dac_command_register_1_0_a3[5]:A, dac_command_register_0[5]:Y. NET dac_command_register_1_0_a3[4]; dac_command_register[4]:D, dac_command_register_1_0_a3[4]:Y. NET dac_command_register_0[4]; dac_command_register_1_0_a3[4]:A, dac_command_register_0[4]:Y. NET dac_command_register_1_0_a3[3]; dac_command_register[3]:D, dac_command_register_1_0_a3[3]:Y. NET N_50; dac_command_register_1_0_a3[3]:A, dac_command_register_0[3]:Y. NET dac_command_register_1_0_a3[2]; dac_command_register[2]:D, dac_command_register_1_0_a3[2]:Y. NET dac_command_register_0[2]; dac_command_register_1_0_a3[2]:A, dac_command_register_0[2]:Y. NET dac_command_register_1_0_a3[1]; dac_command_register[1]:D, dac_command_register_1_0_a3[1]:Y. NET dac_command_register_0[1]; dac_command_register_1_0_a3[1]:A, dac_command_register_0[1]:Y. NET dac_command_register_1_0_a3[0]; dac_command_register[0]:D, dac_command_register_1_0_a3[0]:Y. NET dac_command_register_0[0]; dac_command_register_1_0_a3[0]:A, dac_command_register_0[0]:Y. NET clock_divider_counter_3_i[3]; clock_divider_counter[3]:D, clock_divider_clock_divider_counter_3_i[3]:Y. NET clock_divider_counter_3_i_o3[0]; clock_divider_clock_divider_counter_3_i[2]:A, clock_divider_clock_divider_counter_3_i[3]:A, clock_divider_clock_divider_counter_3_i[1]:A, clock_divider_clock_divider_counter_3_i[0]:A, clock_divider_clock_divider_counter_3_i_o3[0]:Y. NET I_13; clock_divider_clock_divider_counter_3_i[3]:B, un3_clock_divider_counter_I_13:Y. NET clock_divider_counter_3_i[2]; clock_divider_counter[2]:D, clock_divider_clock_divider_counter_3_i[2]:Y. NET I_9; clock_divider_clock_divider_counter_3_i[2]:B, un3_clock_divider_counter_I_9:Y. NET clock_divider_counter_3_i[1]; clock_divider_counter[1]:D, clock_divider_clock_divider_counter_3_i[1]:Y. NET I_5; clock_divider_clock_divider_counter_3_i[1]:B, un3_clock_divider_counter_I_5:Y. NET clock_divider_counter_3_i[0]; clock_divider_counter[0]:D, clock_divider_clock_divider_counter_3_i[0]:Y. NET clock_divider_counter[0]; un3_clock_divider_counter_I_5:A, un3_clock_divider_counter_I_12:A, clock_divider_counter[0]:Q, clock_divider_clock_divider_counter_3_i[0]:B, un3_clock_divider_counter_I_8:B, un4_reset_clock_divider_counter_0_a3:C. NET data_out_0_iv_i_o3[14]; data_out_0_iv_i[14]:A, data_out_4_sqmuxa_0_a3:A, data_out_cnst_m[15]:C, data_out_0_iv_i_o3[14]:Y, data_out_cnst_i_o2[1]:B, data_out_3_sqmuxa_0_a3_1:A, un1_data_out_0_sqmuxa_i_i_a2:A. NET data_out_0_iv_i_a3[14]; data_out_0_iv_i[14]:B, data_out_0_iv_i_a3[14]:Y. NET data_out_0_iv_i_0[14]; data_out_0_iv_i[14]:C, data_out_0_iv_i_0[14]:Y. NET data_out_0_iv_i_a3_0[14]; data_out_0_iv_i_0[14]:A, data_out_0_iv_i_a3_0[14]:Y, data_out_cnst_i_o2[1]:A. NET data_out_0_iv_i_a2[14]; data_out_0_iv_i_0[14]:B, data_out_0_iv_i_a2[14]:Y, data_out_cnst_m[15]:B. NET data_out_0_iv_i_a2_1[14]; un3_mxfe_start_0_a2_0:A, data_out_0_iv_i_a2_1[14]:Y, un1_data_out_0_sqmuxa_i_i_a2:B, data_out_0_iv_i_a3[14]:A. NET un3_mxfe_start_0_a2_1; un3_dac_start_0_a2_0:A, un3_mxfe_start_0_a2_0:B, un3_mxfe_start_0_a2_1:Y. NET un3_dac_start_0_a2; data_out_0_iv_i_a2_2[14]:A, un3_dac_start_0_a2:Y, dac_busy_m:B, un3_dac_start_0_a3:A. NET data_out_1_sqmuxa_0_a2; data_out_3_sqmuxa_0_a3_1:B, data_out_1_sqmuxa_0_a2:Y, un3_dac_start_0_a2_0:B. NET synced_wr_n; un3_mxfe_start_0_a2_1:B, fed1:synced_wr_n, sync2:synced_wr_n. NET candidate_delayed; un3_mxfe_start_0_a2_1:C, fed1: candidate_delayed. NET clock_divider_counter[1]; un4_reset_clock_divider_counter_0_a3:A, un3_clock_divider_counter_I_12:B, un3_clock_divider_counter_I_5: B, un3_clock_divider_counter_I_8:A, clock_divider_counter[1]:Q. NET un4_reset_clock_divider_counter_0_a3_0; un4_reset_clock_divider_counter_0_a3:B, un4_reset_clock_divider_counter_0_a3_0:Y. NET clock_divider_counter[2]; un4_reset_clock_divider_counter_0_a3_0:A, un3_clock_divider_counter_I_12:C, un3_clock_divider_counter_I_9: B, clock_divider_counter[2]:Q. NET clock_divider_counter[3]; un3_clock_divider_counter_I_13:B, un4_reset_clock_divider_counter_0_a3_0:B, clock_divider_counter[3]:Q. NET data_out_cnst_m[0]; data_out_iv_4[0]:A, data_out_0_iv[3]:B, data_out_0_iv[15]:C, data_out_0_iv[12]:C, data_out_cnst_m[15]:Y, data_out_0_iv[7]:B, data_out_0_iv[5]:B, data_out_0_iv[11]:C, data_out_0_iv[9]:C, data_out_0_iv[10]:C, data_out_0_iv[2]:B. NET N_150_i_0; data_out_0_iv[1]:A, data_out_0_iv[13]:C, data_out_cnst_i_o2[1]:Y, data_out_0_iv[6]:A. NET dac_data_register_m[7]; data_out_0_iv[7]:A, dac_data_register_m[7]:Y. NET data_out_0_iv_2_i[7]; data_out_0_iv[7]:C, data_out_0_iv_2[7]: Y. NET data_out_1_sqmuxa; data_out_0_iv_2[5]:A, data_out_0_iv_2[3]: A, data_out_0_iv_2[4]:A, data_out_0_iv_2[7]:A, data_out_1_sqmuxa_0_a3:Y, data_out_0_iv_2[6]:A, data_out_0_iv_2[2]:A, data_out_0_iv_2[1]:A, data_out_iv_2[0]:A. NET data_out_0_iv_1[7]; data_out_0_iv_2[7]:C, data_out_0_iv_1[7]: Y. NET data_out_2_sqmuxa; data_out_0_iv_1[3]:A, data_out_0_iv_1[6]: A, data_out_0_iv_1[7]:A, data_out_0_iv_1[4]:A, data_out_0_iv_1[1]:A, data_out_iv_1[0]:A, data_out_0_iv_1[5]:A, data_out_0_iv_1[2]:A, data_out_2_sqmuxa_0_a3:Y. NET data_out_0_iv_0[7]; data_out_0_iv_1[7]:C, data_out_0_iv_0[7]: Y. NET data_out_4_sqmuxa; data_out_0_iv_0[4]:A, data_out_0_iv_0[6]: A, data_out_0_iv_0[5]:A, data_out_4_sqmuxa_0_a3:Y, data_out_iv_0[0]:A, data_out_0_iv_0[2]:A, data_out_0_iv_0[1]:A, data_out_0_iv_0[3]:A, data_out_0_iv_0[7]:A. NET mxfe_register_2_m[7]; data_out_0_iv_0[7]:C, mxfe_register_2_m[7]:Y. NET data_out_3_sqmuxa; mxfe_register_2_m[3]:A, mxfe_register_2_m[6]:A, data_out_3_sqmuxa_0_a3:Y, mxfe_register_2_m[4]:A, mxfe_register_2_m[1]:A, mxfe_register_2_m[0]:A, mxfe_register_2_m[7]:A, mxfe_register_2_m[5]:A, mxfe_register_2_m[2]:A. NET data_out_0_iv_2_i[6]; data_out_0_iv[6]:B, data_out_0_iv_2[6]: Y. NET dac_data_register_m_i[6]; data_out_0_iv[6]:C, dac_data_register_m[6]:Y. NET data_out_0_iv_1[6]; data_out_0_iv_2[6]:C, data_out_0_iv_1[6]: Y. NET data_out_0_iv_0[6]; data_out_0_iv_1[6]:C, data_out_0_iv_0[6]: Y. NET mxfe_register_2_m[6]; data_out_0_iv_0[6]:C, mxfe_register_2_m[6]:Y. NET data_out_6_sqmuxa; dac_data_register_m[5]:A, dac_data_register_m[0]:A, data_out_0_iv[4]:A, dac_data_register_m[1]:A, dac_data_register_m[2]:A, data_out_6_sqmuxa_0_a3:Y, dac_data_register_m[3]:A, dac_data_register_m[6]:A. NET dac_data_register_m[5]; data_out_0_iv[5]:A, dac_data_register_m[5]:Y. NET data_out_0_iv_2_i[5]; data_out_0_iv[5]:C, data_out_0_iv_2[5]: Y. NET data_out_0_iv_1[5]; data_out_0_iv_2[5]:C, data_out_0_iv_1[5]: Y. NET data_out_0_iv_0[5]; data_out_0_iv_1[5]:C, data_out_0_iv_0[5]: Y. NET mxfe_register_2_m[5]; data_out_0_iv_0[5]:C, mxfe_register_2_m[5]:Y. NET data_out_0_iv_2[4]; data_out_0_iv[4]:C, data_out_0_iv_2[4]:Y. NET data_out_0_iv_1[4]; data_out_0_iv_2[4]:C, data_out_0_iv_1[4]: Y. NET data_out_0_iv_0[4]; data_out_0_iv_1[4]:C, data_out_0_iv_0[4]: Y. NET mxfe_register_2_m[4]; data_out_0_iv_0[4]:C, mxfe_register_2_m[4]:Y. NET dac_data_register_m[3]; data_out_0_iv[3]:A, dac_data_register_m[3]:Y. NET data_out_0_iv_2_i[3]; data_out_0_iv[3]:C, data_out_0_iv_2[3]: Y. NET data_out_0_iv_1[3]; data_out_0_iv_2[3]:C, data_out_0_iv_1[3]: Y. NET data_out_0_iv_0[3]; data_out_0_iv_1[3]:C, data_out_0_iv_0[3]: Y. NET mxfe_register_2_m[3]; data_out_0_iv_0[3]:C, mxfe_register_2_m[3]:Y. NET dac_data_register_m[2]; data_out_0_iv[2]:A, dac_data_register_m[2]:Y. NET data_out_0_iv_2_i[2]; data_out_0_iv[2]:C, data_out_0_iv_2[2]: Y. NET data_out_0_iv_1[2]; data_out_0_iv_2[2]:C, data_out_0_iv_1[2]: Y. NET data_out_0_iv_0[2]; data_out_0_iv_1[2]:C, data_out_0_iv_0[2]: Y. NET mxfe_register_2_m[2]; data_out_0_iv_0[2]:C, mxfe_register_2_m[2]:Y. NET data_out_0_iv_2_i[1]; data_out_0_iv[1]:B, data_out_0_iv_2[1]: Y. NET dac_data_register_m_i[1]; data_out_0_iv[1]:C, dac_data_register_m[1]:Y. NET data_out_0_iv_1[1]; data_out_0_iv_2[1]:C, data_out_0_iv_1[1]: Y. NET data_out_0_iv_0[1]; data_out_0_iv_1[1]:C, data_out_0_iv_0[1]: Y. NET mxfe_register_2_m[1]; data_out_0_iv_0[1]:C, mxfe_register_2_m[1]:Y. NET data_out_0_iv_i_a2_2[14]; data_out_4_sqmuxa_0_a3_0:A, data_out_0_iv_i_a2[14]:A, data_out_0_iv_i_a3_0[14]:A, data_out_0_iv_i_a2_2[14]:Y. NET N_392_i; data_out_4_sqmuxa_0_a2:A, data_out_0_iv_i_a2_0[14]: Y, data_out_0_iv_i_a3_0[14]:B. NET data_out_0_iv_i_a3_0_1_i[14]; data_out_0_iv_i_a3_0[14]:C, data_out_0_iv_i_a3_0_1[14]:Y. NET dac_busy_m_i; data_out_iv[0]:A, dac_busy_m:Y. NET dac_data_register_m_i[0]; data_out_iv[0]:B, dac_data_register_m[0]:Y. NET data_out_iv_4_i[0]; data_out_iv[0]:C, data_out_iv_4[0]:Y. NET data_out_iv_2_i[0]; data_out_iv_4[0]:B, data_out_iv_2[0]:Y. NET mxfe_busy_m_i; data_out_iv_4[0]:C, mxfe_busy_m:Y. NET data_out_iv_1[0]; data_out_iv_2[0]:C, data_out_iv_1[0]:Y. NET data_out_3_sqmuxa_1; data_out_1_sqmuxa_0_a3:B, data_out_3_sqmuxa_0_a3:B, data_out_3_sqmuxa_0_a3_1:Y. NET data_out_iv_0[0]; data_out_iv_1[0]:C, data_out_iv_0[0]:Y. NET mxfe_register_2_m[0]; data_out_iv_0[0]:C, mxfe_register_2_m[0]:Y. NET data_out_4_sqmuxa_0_a2; data_out_0_iv_i_a2_6[14]:A, data_out_0_iv_i_a2[14]:C, data_out_4_sqmuxa_0_a3:B, data_out_4_sqmuxa_0_a2:Y. NET data_out_4_sqmuxa_0_a3_0; data_out_4_sqmuxa_0_a3:C, data_out_4_sqmuxa_0_a3_0:Y. NET data_out_0_iv_i_a2_6[14]; data_out_0_iv_i_a2_1[14]:A, data_out_1_sqmuxa_0_a2:A, data_out_0_iv_i_a2_6[14]:Y. NET mxfe_busy; mxfe_busy_m:A, mxfe_busy_ff:mxfe_busy. NET N_364_i_0; mxfe_busy_m:B, N_364_i:Y. NET data_out_0_iv_i_a2_3[14]; data_out_0_iv_i_a2[14]:B, data_out_0_iv_i_a2_3[14]:Y. NET dac_busy; dac_busy_m:A, dac_busy_ff:dac_busy. NET data_out_0_iv_i_a2_0_6_i[14]; data_out_0_iv_i_a2_0[14]:B, data_out_0_iv_i_a2_0_6[14]:Y. NET data_out_0_iv_i_a2_0_4_i[14]; data_out_0_iv_i_a2_0_6[14]:B, data_out_0_iv_i_a2_0_4[14]:Y. NET data_out_0_iv_i_a2_0_2_i[14]; data_out_0_iv_i_a2_0_4[14]:B, data_out_0_iv_i_a2_0_2[14]:Y. NET data_out_0_iv_i_a2_0_0_i[14]; data_out_0_iv_i_a2_0_2[14]:B, data_out_0_iv_i_a2_0_0[14]:Y. NET N_7; un3_clock_divider_counter_I_9:A, un3_clock_divider_counter_I_8:Y. NET N_4; un3_clock_divider_counter_I_13:A, un3_clock_divider_counter_I_12:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF piso_shift_register; mxfe_configuration_data<21>, mxfe_configuration_data<20>, mxfe_configuration_data<19>, mxfe_configuration_data<18>, mxfe_configuration_data<17>, mxfe_configuration_data<16>, mxfe_configuration_data<15>, mxfe_configuration_data<14>, mxfe_configuration_data<13>, mxfe_configuration_data<12>, mxfe_configuration_data<11>, mxfe_configuration_data<10>, mxfe_configuration_data<9>, mxfe_configuration_data<8>, mxfe_configuration_data<7>, mxfe_configuration_data<6>, mxfe_configuration_data<5>, mxfe_configuration_data<4>, mxfe_configuration_data<3>, mxfe_configuration_data<2>, mxfe_configuration_data<1>, mxfe_configuration_data<0>, mhz_20_clock_8, mhz_20_clock_7, mhz_20_clock_6, load_configuration_data, reset_4, load_configuration_data_1, reset_5, one_n_or_two, write_n_or_read, spi_sdo_opad_c, reset_6, load_configuration_data_0, write_clock_enable, shift_configuration_data; BUSFORMAT:%s<%d>. PIN mxfe_configuration_data<21>; ENM: 'mxfe_configuration_data<21:0>', BUS:0, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:0/21/0/0. PIN mxfe_configuration_data<20>; ENM: 'mxfe_configuration_data<21:0>', BUS:1, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:1/21/0/0. PIN mxfe_configuration_data<19>; ENM: 'mxfe_configuration_data<21:0>', BUS:2, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:2/21/0/0. PIN mxfe_configuration_data<18>; ENM: 'mxfe_configuration_data<21:0>', BUS:3, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:3/21/0/0. PIN mxfe_configuration_data<17>; ENM: 'mxfe_configuration_data<21:0>', BUS:4, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:4/21/0/0. PIN mxfe_configuration_data<16>; ENM: 'mxfe_configuration_data<21:0>', BUS:5, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:5/21/0/0. PIN mxfe_configuration_data<15>; ENM: 'mxfe_configuration_data<21:0>', BUS:6, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:6/21/0/0. PIN mxfe_configuration_data<14>; ENM: 'mxfe_configuration_data<21:0>', BUS:7, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:7/21/0/0. PIN mxfe_configuration_data<13>; ENM: 'mxfe_configuration_data<21:0>', BUS:8, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:8/21/0/0. PIN mxfe_configuration_data<12>; ENM: 'mxfe_configuration_data<21:0>', BUS:9, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:9/21/0/0. PIN mxfe_configuration_data<11>; ENM: 'mxfe_configuration_data<21:0>', BUS:10, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:10/21/0/0. PIN mxfe_configuration_data<10>; ENM: 'mxfe_configuration_data<21:0>', BUS:11, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:11/21/0/0. PIN mxfe_configuration_data<9>; ENM:'mxfe_configuration_data<21:0>', BUS:12, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:12/21/0/0. PIN mxfe_configuration_data<8>; ENM:'mxfe_configuration_data<21:0>', BUS:13, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:13/21/0/0. PIN mxfe_configuration_data<7>; ENM:'mxfe_configuration_data<21:0>', BUS:14, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:14/21/0/0. PIN mxfe_configuration_data<6>; ENM:'mxfe_configuration_data<21:0>', BUS:15, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:15/21/0/0. PIN mxfe_configuration_data<5>; ENM:'mxfe_configuration_data<21:0>', BUS:16, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:16/21/0/0. PIN mxfe_configuration_data<4>; ENM:'mxfe_configuration_data<21:0>', BUS:17, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:17/21/0/0. PIN mxfe_configuration_data<3>; ENM:'mxfe_configuration_data<21:0>', BUS:18, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:18/21/0/0. PIN mxfe_configuration_data<2>; ENM:'mxfe_configuration_data<21:0>', BUS:19, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:19/21/0/0. PIN mxfe_configuration_data<1>; ENM:'mxfe_configuration_data<21:0>', BUS:20, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:20/21/0/0. PIN mxfe_configuration_data<0>; ENM:'mxfe_configuration_data<21:0>', BUS:21, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:21/21/0/0. PIN mhz_20_clock_8; DIRECTION:INPUT. PIN mhz_20_clock_7; DIRECTION:INPUT. PIN mhz_20_clock_6; DIRECTION:INPUT. PIN load_configuration_data; DIRECTION:INPUT. PIN reset_4; DIRECTION:INPUT. PIN load_configuration_data_1; DIRECTION:INPUT. PIN reset_5; DIRECTION:INPUT. PIN one_n_or_two; DIRECTION:INPUT. PIN write_n_or_read; DIRECTION:INPUT. PIN spi_sdo_opad_c; DIRECTION:OUTPUT. PIN reset_6; DIRECTION:INPUT. PIN load_configuration_data_0; DIRECTION:INPUT. PIN write_clock_enable; DIRECTION:INPUT. PIN shift_configuration_data; DIRECTION:INPUT. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[22]. USE ADLIB:DFF; parallel_in_serial_out[5]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[22]. USE ADLIB:MUX2H; parallel_in_serial_out_0[1]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[1]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[15]. USE ADLIB:MUX2H; parallel_in_serial_out_0[7]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[8]. USE ADLIB:DFF; parallel_in_serial_out[1]. USE ADLIB:DFF; parallel_in_serial_out[0]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[19]. USE ADLIB:MUX2H; parallel_in_serial_out_0[18]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[15]. USE ADLIB:DFF; parallel_in_serial_out[22]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[12]. USE ADLIB:MUX2H; parallel_in_serial_out_0[12]. USE ADLIB:DFF; parallel_in_serial_out[8]. USE ADLIB:DFF; parallel_in_serial_out[10]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[14]. USE ADLIB:DFF; parallel_in_serial_out[13]. USE ADLIB:DFF; parallel_in_serial_out[3]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[1]. USE ADLIB:DFF; parallel_in_serial_out[6]. USE ADLIB:DFF; parallel_in_serial_out[18]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[19]. USE ADLIB:MUX2H; parallel_in_serial_out_0[8]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[10]. USE ADLIB:DFF; parallel_in_serial_out[16]. USE ADLIB:OA21FTF; un1_load_in_1. USE ADLIB:NOR2FT; parallel_in_serial_out_1[5]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[18]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[11]. USE ADLIB:DFF; parallel_in_serial_out[14]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[3]. USE ADLIB:MUX2H; parallel_in_serial_out_0[16]. USE ADLIB:DFF; parallel_in_serial_out[19]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[23]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[8]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[6]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[13]. USE ADLIB:MUX2H; parallel_in_serial_out_0[17]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[0]. USE ADLIB:MUX2H; parallel_in_serial_out_0[6]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[16]. USE ADLIB:DFF; parallel_in_serial_out[2]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[9]. USE ADLIB:DFF; parallel_in_serial_out[15]. USE ADLIB:DFF; parallel_in_serial_out[11]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[4]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[4]. USE ADLIB:AND2; piso_parallel_in_serial_out_4[0]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[14]. USE ADLIB:MUX2H; parallel_in_serial_out_0[20]. USE ADLIB:GND; GND_i. USE ADLIB:MUX2H; parallel_in_serial_out_0[21]. USE ADLIB:MUX2H; parallel_in_serial_out_0[15]. USE ADLIB:MUX2H; parallel_in_serial_out_0[3]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[13]. USE ADLIB:MUX2H; parallel_in_serial_out_0[23]. USE ADLIB:MUX2H; parallel_in_serial_out_0[0]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[18]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[7]. USE ADLIB:DFF; parallel_in_serial_out[12]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[20]. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2FT; parallel_in_serial_out_1[12]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[3]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[21]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[6]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[7]. USE ADLIB:MUX2H; parallel_in_serial_out_0[14]. USE ADLIB:DFF; parallel_in_serial_out[20]. USE ADLIB:DFF; parallel_in_serial_out[17]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[23]. USE ADLIB:DFF; parallel_in_serial_out[23]. USE ADLIB:DFF; parallel_in_serial_out[7]. USE ADLIB:MUX2H; parallel_in_serial_out_0[4]. USE ADLIB:MUX2H; parallel_in_serial_out_0[19]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[21]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[20]. USE ADLIB:MUX2H; parallel_in_serial_out_0[10]. USE ADLIB:MUX2H; parallel_in_serial_out_0[9]. USE ADLIB:MUX2H; parallel_in_serial_out_0[11]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[5]. USE ADLIB:DFF; parallel_in_serial_out[9]. USE ADLIB:DFF; parallel_in_serial_out[4]. USE ADLIB:MUX2H; parallel_in_serial_out_0[2]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[16]. USE ADLIB:MUX2H; parallel_in_serial_out_0[22]. USE ADLIB:MUX2H; parallel_in_serial_out_0[13]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[17]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[17]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[9]. USE ADLIB:MUX2H; parallel_in_serial_out_0[5]. USE ADLIB:OA21FTF; un1_load_in_1_0. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[2]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[11]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[10]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[2]. USE ADLIB:DFF; parallel_in_serial_out[21]. NET mxfe_configuration_data[0]; mxfe_configuration_data<0>, piso_parallel_in_serial_out_4[0]:B. NET mxfe_configuration_data[1]; mxfe_configuration_data<1>, piso_parallel_in_serial_out_4[1]:B. NET mxfe_configuration_data[2]; mxfe_configuration_data<2>, piso_parallel_in_serial_out_4[2]:B. NET mxfe_configuration_data[3]; mxfe_configuration_data<3>, piso_parallel_in_serial_out_4[3]:B. NET mxfe_configuration_data[4]; mxfe_configuration_data<4>, piso_parallel_in_serial_out_4[4]:B. NET mxfe_configuration_data[5]; mxfe_configuration_data<5>, piso_parallel_in_serial_out_4[5]:B. NET mxfe_configuration_data[6]; mxfe_configuration_data<6>, piso_parallel_in_serial_out_4[6]:B. NET mxfe_configuration_data[7]; mxfe_configuration_data<7>, piso_parallel_in_serial_out_4[7]:B. NET mxfe_configuration_data[8]; mxfe_configuration_data<8>, piso_parallel_in_serial_out_4[8]:B. NET mxfe_configuration_data[9]; mxfe_configuration_data<9>, piso_parallel_in_serial_out_4[9]:B. NET mxfe_configuration_data[10]; mxfe_configuration_data<10>, piso_parallel_in_serial_out_4[10]:B. NET mxfe_configuration_data[11]; mxfe_configuration_data<11>, piso_parallel_in_serial_out_4[11]:B. NET mxfe_configuration_data[12]; mxfe_configuration_data<12>, piso_parallel_in_serial_out_4[12]:B. NET mxfe_configuration_data[13]; mxfe_configuration_data<13>, piso_parallel_in_serial_out_4[13]:B. NET mxfe_configuration_data[14]; mxfe_configuration_data<14>, piso_parallel_in_serial_out_4[14]:B. NET mxfe_configuration_data[15]; mxfe_configuration_data<15>, piso_parallel_in_serial_out_4[15]:B. NET mxfe_configuration_data[16]; mxfe_configuration_data<16>, piso_parallel_in_serial_out_4[16]:B. NET mxfe_configuration_data[17]; mxfe_configuration_data<17>, piso_parallel_in_serial_out_4[17]:B. NET mxfe_configuration_data[18]; mxfe_configuration_data<18>, piso_parallel_in_serial_out_4[18]:B. NET mxfe_configuration_data[19]; mxfe_configuration_data<19>, piso_parallel_in_serial_out_4[19]:B. NET mxfe_configuration_data[20]; mxfe_configuration_data<20>, piso_parallel_in_serial_out_4[20]:B. NET mxfe_configuration_data[21]; mxfe_configuration_data<21>, piso_parallel_in_serial_out_4[21]:B. NET mhz_20_clock_8; mhz_20_clock_8, parallel_in_serial_out[21]: CLK, parallel_in_serial_out[23]:CLK, parallel_in_serial_out[20]: CLK, parallel_in_serial_out[19]:CLK, parallel_in_serial_out[22]: CLK. NET mhz_20_clock_7; mhz_20_clock_7, parallel_in_serial_out[9]: CLK, parallel_in_serial_out[7]:CLK, parallel_in_serial_out[17]: CLK, parallel_in_serial_out[12]:CLK, parallel_in_serial_out[11]: CLK, parallel_in_serial_out[15]:CLK, parallel_in_serial_out[14]: CLK, parallel_in_serial_out[16]:CLK, parallel_in_serial_out[18]: CLK, parallel_in_serial_out[13]:CLK, parallel_in_serial_out[10]: CLK, parallel_in_serial_out[8]:CLK. NET mhz_20_clock_6; mhz_20_clock_6, parallel_in_serial_out[4]: CLK, parallel_in_serial_out[2]:CLK, parallel_in_serial_out[6]: CLK, parallel_in_serial_out[3]:CLK, parallel_in_serial_out[0]: CLK, parallel_in_serial_out[1]:CLK, parallel_in_serial_out[5]: CLK. NET load_configuration_data; load_configuration_data, piso_parallel_in_serial_out_4[2]:S, piso_parallel_in_serial_out_4[5]:S, piso_parallel_in_serial_out_4[3]:S, piso_parallel_in_serial_out_4[0]:A, piso_parallel_in_serial_out_4[4]:S, piso_parallel_in_serial_out_4[1]:S. NET reset_4; reset_4, parallel_in_serial_out_1[2]:B, parallel_in_serial_out_1[4]:B, parallel_in_serial_out_1[0]:B, parallel_in_serial_out_1[6]:B, parallel_in_serial_out_1[3]:B, parallel_in_serial_out_1[5]:B, parallel_in_serial_out_1[1]:B. NET load_configuration_data_1; load_configuration_data_1, piso_parallel_in_serial_out_4[10]:S, piso_parallel_in_serial_out_4[11]:S, piso_parallel_in_serial_out_4[7]:S, piso_parallel_in_serial_out_4[6]:S, piso_parallel_in_serial_out_4[13]:S, piso_parallel_in_serial_out_4[14]:S, piso_parallel_in_serial_out_4[9]:S, piso_parallel_in_serial_out_4[12]:S, piso_parallel_in_serial_out_4[15]:S, piso_parallel_in_serial_out_4[8]:S. NET reset_5; reset_5, parallel_in_serial_out_1[9]:B, parallel_in_serial_out_1[17]:B, parallel_in_serial_out_1[16]:B, parallel_in_serial_out_1[12]:B, parallel_in_serial_out_1[7]:B, parallel_in_serial_out_1[18]:B, parallel_in_serial_out_1[13]:B, parallel_in_serial_out_1[8]:B, parallel_in_serial_out_1[11]:B, parallel_in_serial_out_1[10]:B, parallel_in_serial_out_1[14]:B, parallel_in_serial_out_1[15]:B. NET one_n_or_two; one_n_or_two, piso_parallel_in_serial_out_4[22]:B. NET write_n_or_read; write_n_or_read, piso_parallel_in_serial_out_4[23]:B. NET spi_sdo_opad_c; spi_sdo_opad_c, parallel_in_serial_out[23]:Q, parallel_in_serial_out_0[23]:B. NET reset_6; reset_6, parallel_in_serial_out_1[23]:B, parallel_in_serial_out_1[21]:B, parallel_in_serial_out_1[20]:B, parallel_in_serial_out_1[19]:B, parallel_in_serial_out_1[22]:B. NET load_configuration_data_0; load_configuration_data_0, un1_load_in_1_0:C, piso_parallel_in_serial_out_4[17]:S, piso_parallel_in_serial_out_4[20]:S, piso_parallel_in_serial_out_4[21]:S, piso_parallel_in_serial_out_4[16]:S, piso_parallel_in_serial_out_4[23]:S, piso_parallel_in_serial_out_4[18]:S, un1_load_in_1:C, piso_parallel_in_serial_out_4[19]:S, piso_parallel_in_serial_out_4[22]:S. NET write_clock_enable; write_clock_enable, un1_load_in_1_0:B, un1_load_in_1:B. NET shift_configuration_data; shift_configuration_data, un1_load_in_1_0:A, un1_load_in_1:A. NET un1_load_in_1_0; parallel_in_serial_out_0[18]:S, un1_load_in_1_0:Y, parallel_in_serial_out_0[13]:S, parallel_in_serial_out_0[22]:S, parallel_in_serial_out_0[19]:S, parallel_in_serial_out_0[14]:S, parallel_in_serial_out_0[23]:S, parallel_in_serial_out_0[15]:S, parallel_in_serial_out_0[21]:S, parallel_in_serial_out_0[20]:S, parallel_in_serial_out_0[17]:S, parallel_in_serial_out_0[16]:S, parallel_in_serial_out_0[12]:S. NET parallel_in_serial_out_1[23]; parallel_in_serial_out[23]:D, parallel_in_serial_out_1[23]:Y. NET parallel_in_serial_out_0[23]; parallel_in_serial_out_1[23]:A, parallel_in_serial_out_0[23]:Y. NET parallel_in_serial_out_4[23]; parallel_in_serial_out_0[23]:A, piso_parallel_in_serial_out_4[23]:Y. NET parallel_in_serial_out[22]; piso_parallel_in_serial_out_4[23]:A, parallel_in_serial_out_0[22]:B, parallel_in_serial_out[22]:Q. NET parallel_in_serial_out_1[22]; parallel_in_serial_out[22]:D, parallel_in_serial_out_1[22]:Y. NET N_23; parallel_in_serial_out_1[22]:A, parallel_in_serial_out_0[22]:Y. NET parallel_in_serial_out_4[22]; parallel_in_serial_out_0[22]:A, piso_parallel_in_serial_out_4[22]:Y. NET parallel_in_serial_out[21]; piso_parallel_in_serial_out_4[22]:A, parallel_in_serial_out[21]: Q, parallel_in_serial_out_0[21]:B. NET parallel_in_serial_out_1[21]; parallel_in_serial_out[21]:D, parallel_in_serial_out_1[21]:Y. NET parallel_in_serial_out_0[21]; parallel_in_serial_out_1[21]:A, parallel_in_serial_out_0[21]:Y. NET parallel_in_serial_out_4[21]; parallel_in_serial_out_0[21]:A, piso_parallel_in_serial_out_4[21]:Y. NET parallel_in_serial_out[20]; piso_parallel_in_serial_out_4[21]:A, parallel_in_serial_out_0[20]:B, parallel_in_serial_out[20]:Q. NET parallel_in_serial_out_1[20]; parallel_in_serial_out[20]:D, parallel_in_serial_out_1[20]:Y. NET parallel_in_serial_out_0[20]; parallel_in_serial_out_1[20]:A, parallel_in_serial_out_0[20]:Y. NET parallel_in_serial_out_4[20]; parallel_in_serial_out_0[20]:A, piso_parallel_in_serial_out_4[20]:Y. NET parallel_in_serial_out[19]; piso_parallel_in_serial_out_4[20]:A, parallel_in_serial_out_0[19]:B, parallel_in_serial_out[19]:Q. NET parallel_in_serial_out_1[19]; parallel_in_serial_out[19]:D, parallel_in_serial_out_1[19]:Y. NET parallel_in_serial_out_0[19]; parallel_in_serial_out_1[19]:A, parallel_in_serial_out_0[19]:Y. NET parallel_in_serial_out_4[19]; parallel_in_serial_out_0[19]:A, piso_parallel_in_serial_out_4[19]:Y. NET parallel_in_serial_out[18]; piso_parallel_in_serial_out_4[19]:A, parallel_in_serial_out[18]: Q, parallel_in_serial_out_0[18]:B. NET parallel_in_serial_out_1[18]; parallel_in_serial_out[18]:D, parallel_in_serial_out_1[18]:Y. NET parallel_in_serial_out_0[18]; parallel_in_serial_out_1[18]:A, parallel_in_serial_out_0[18]:Y. NET parallel_in_serial_out_4[18]; parallel_in_serial_out_0[18]:A, piso_parallel_in_serial_out_4[18]:Y. NET parallel_in_serial_out[17]; piso_parallel_in_serial_out_4[18]:A, parallel_in_serial_out[17]: Q, parallel_in_serial_out_0[17]:B. NET parallel_in_serial_out_1[17]; parallel_in_serial_out[17]:D, parallel_in_serial_out_1[17]:Y. NET parallel_in_serial_out_0[17]; parallel_in_serial_out_1[17]:A, parallel_in_serial_out_0[17]:Y. NET parallel_in_serial_out_4[17]; parallel_in_serial_out_0[17]:A, piso_parallel_in_serial_out_4[17]:Y. NET parallel_in_serial_out[16]; piso_parallel_in_serial_out_4[17]:A, parallel_in_serial_out_0[16]:B, parallel_in_serial_out[16]:Q. NET parallel_in_serial_out_1[16]; parallel_in_serial_out[16]:D, parallel_in_serial_out_1[16]:Y. NET parallel_in_serial_out_0[16]; parallel_in_serial_out_1[16]:A, parallel_in_serial_out_0[16]:Y. NET parallel_in_serial_out_4[16]; parallel_in_serial_out_0[16]:A, piso_parallel_in_serial_out_4[16]:Y. NET parallel_in_serial_out[15]; piso_parallel_in_serial_out_4[16]:A, parallel_in_serial_out_0[15]:B, parallel_in_serial_out[15]:Q. NET parallel_in_serial_out_1[15]; parallel_in_serial_out[15]:D, parallel_in_serial_out_1[15]:Y. NET parallel_in_serial_out_0[15]; parallel_in_serial_out_1[15]:A, parallel_in_serial_out_0[15]:Y. NET parallel_in_serial_out_4[15]; parallel_in_serial_out_0[15]:A, piso_parallel_in_serial_out_4[15]:Y. NET parallel_in_serial_out[14]; piso_parallel_in_serial_out_4[15]:A, parallel_in_serial_out_0[14]:B, parallel_in_serial_out[14]:Q. NET parallel_in_serial_out_1[14]; parallel_in_serial_out[14]:D, parallel_in_serial_out_1[14]:Y. NET parallel_in_serial_out_0[14]; parallel_in_serial_out_1[14]:A, parallel_in_serial_out_0[14]:Y. NET parallel_in_serial_out_4[14]; parallel_in_serial_out_0[14]:A, piso_parallel_in_serial_out_4[14]:Y. NET parallel_in_serial_out[13]; piso_parallel_in_serial_out_4[14]:A, parallel_in_serial_out_0[13]:B, parallel_in_serial_out[13]:Q. NET parallel_in_serial_out_1[13]; parallel_in_serial_out[13]:D, parallel_in_serial_out_1[13]:Y. NET parallel_in_serial_out_0[13]; parallel_in_serial_out_1[13]:A, parallel_in_serial_out_0[13]:Y. NET parallel_in_serial_out_4[13]; parallel_in_serial_out_0[13]:A, piso_parallel_in_serial_out_4[13]:Y. NET parallel_in_serial_out[12]; piso_parallel_in_serial_out_4[13]:A, parallel_in_serial_out[12]: Q, parallel_in_serial_out_0[12]:B. NET parallel_in_serial_out_1[12]; parallel_in_serial_out[12]:D, parallel_in_serial_out_1[12]:Y. NET parallel_in_serial_out_0[12]; parallel_in_serial_out_1[12]:A, parallel_in_serial_out_0[12]:Y. NET parallel_in_serial_out_4[12]; parallel_in_serial_out_0[12]:A, piso_parallel_in_serial_out_4[12]:Y. NET parallel_in_serial_out[11]; piso_parallel_in_serial_out_4[12]:A, parallel_in_serial_out_0[11]:B, parallel_in_serial_out[11]:Q. NET parallel_in_serial_out_1[11]; parallel_in_serial_out[11]:D, parallel_in_serial_out_1[11]:Y. NET parallel_in_serial_out_0[11]; parallel_in_serial_out_1[11]:A, parallel_in_serial_out_0[11]:Y. NET parallel_in_serial_out_4[11]; parallel_in_serial_out_0[11]:A, piso_parallel_in_serial_out_4[11]:Y. NET un1_load_in_1; parallel_in_serial_out_0[1]:S, parallel_in_serial_out_0[5]:S, parallel_in_serial_out_0[2]:S, parallel_in_serial_out_0[11]:S, parallel_in_serial_out_0[9]:S, parallel_in_serial_out_0[10]:S, parallel_in_serial_out_0[4]:S, parallel_in_serial_out_0[0]:S, parallel_in_serial_out_0[3]:S, parallel_in_serial_out_0[6]:S, un1_load_in_1:Y, parallel_in_serial_out_0[8]:S, parallel_in_serial_out_0[7]:S. NET parallel_in_serial_out[10]; piso_parallel_in_serial_out_4[11]:A, parallel_in_serial_out_0[10]:B, parallel_in_serial_out[10]:Q. NET parallel_in_serial_out_1[10]; parallel_in_serial_out[10]:D, parallel_in_serial_out_1[10]:Y. NET parallel_in_serial_out_0[10]; parallel_in_serial_out_1[10]:A, parallel_in_serial_out_0[10]:Y. NET parallel_in_serial_out_4[10]; parallel_in_serial_out_0[10]:A, piso_parallel_in_serial_out_4[10]:Y. NET parallel_in_serial_out[9]; piso_parallel_in_serial_out_4[10]: A, parallel_in_serial_out_0[9]:B, parallel_in_serial_out[9]:Q. NET parallel_in_serial_out_1[9]; parallel_in_serial_out[9]:D, parallel_in_serial_out_1[9]:Y. NET parallel_in_serial_out_0[9]; parallel_in_serial_out_1[9]:A, parallel_in_serial_out_0[9]:Y. NET parallel_in_serial_out_4[9]; parallel_in_serial_out_0[9]:A, piso_parallel_in_serial_out_4[9]:Y. NET parallel_in_serial_out[8]; piso_parallel_in_serial_out_4[9]: A, parallel_in_serial_out_0[8]:B, parallel_in_serial_out[8]:Q. NET parallel_in_serial_out_1[8]; parallel_in_serial_out[8]:D, parallel_in_serial_out_1[8]:Y. NET parallel_in_serial_out_0[8]; parallel_in_serial_out_1[8]:A, parallel_in_serial_out_0[8]:Y. NET parallel_in_serial_out_4[8]; parallel_in_serial_out_0[8]:A, piso_parallel_in_serial_out_4[8]:Y. NET parallel_in_serial_out[7]; piso_parallel_in_serial_out_4[8]: A, parallel_in_serial_out[7]:Q, parallel_in_serial_out_0[7]:B. NET parallel_in_serial_out_1[7]; parallel_in_serial_out[7]:D, parallel_in_serial_out_1[7]:Y. NET parallel_in_serial_out_0[7]; parallel_in_serial_out_1[7]:A, parallel_in_serial_out_0[7]:Y. NET parallel_in_serial_out_4[7]; parallel_in_serial_out_0[7]:A, piso_parallel_in_serial_out_4[7]:Y. NET parallel_in_serial_out[6]; piso_parallel_in_serial_out_4[7]: A, parallel_in_serial_out_0[6]:B, parallel_in_serial_out[6]:Q. NET parallel_in_serial_out_1[6]; parallel_in_serial_out[6]:D, parallel_in_serial_out_1[6]:Y. NET parallel_in_serial_out_0[6]; parallel_in_serial_out_1[6]:A, parallel_in_serial_out_0[6]:Y. NET parallel_in_serial_out_4[6]; parallel_in_serial_out_0[6]:A, piso_parallel_in_serial_out_4[6]:Y. NET parallel_in_serial_out[5]; piso_parallel_in_serial_out_4[6]: A, parallel_in_serial_out_0[5]:B, parallel_in_serial_out[5]:Q. NET parallel_in_serial_out_1[5]; parallel_in_serial_out[5]:D, parallel_in_serial_out_1[5]:Y. NET parallel_in_serial_out_0[5]; parallel_in_serial_out_1[5]:A, parallel_in_serial_out_0[5]:Y. NET parallel_in_serial_out_4[5]; parallel_in_serial_out_0[5]:A, piso_parallel_in_serial_out_4[5]:Y. NET parallel_in_serial_out[4]; piso_parallel_in_serial_out_4[5]: A, parallel_in_serial_out[4]:Q, parallel_in_serial_out_0[4]:B. NET parallel_in_serial_out_1[4]; parallel_in_serial_out[4]:D, parallel_in_serial_out_1[4]:Y. NET parallel_in_serial_out_0[4]; parallel_in_serial_out_1[4]:A, parallel_in_serial_out_0[4]:Y. NET parallel_in_serial_out_4[4]; parallel_in_serial_out_0[4]:A, piso_parallel_in_serial_out_4[4]:Y. NET parallel_in_serial_out[3]; piso_parallel_in_serial_out_4[4]: A, parallel_in_serial_out_0[3]:B, parallel_in_serial_out[3]:Q. NET parallel_in_serial_out_1[3]; parallel_in_serial_out[3]:D, parallel_in_serial_out_1[3]:Y. NET parallel_in_serial_out_0[3]; parallel_in_serial_out_1[3]:A, parallel_in_serial_out_0[3]:Y. NET parallel_in_serial_out_4[3]; parallel_in_serial_out_0[3]:A, piso_parallel_in_serial_out_4[3]:Y. NET parallel_in_serial_out[2]; piso_parallel_in_serial_out_4[3]: A, parallel_in_serial_out_0[2]:B, parallel_in_serial_out[2]:Q. NET parallel_in_serial_out_1[2]; parallel_in_serial_out[2]:D, parallel_in_serial_out_1[2]:Y. NET parallel_in_serial_out_0[2]; parallel_in_serial_out_1[2]:A, parallel_in_serial_out_0[2]:Y. NET parallel_in_serial_out_4[2]; parallel_in_serial_out_0[2]:A, piso_parallel_in_serial_out_4[2]:Y. NET parallel_in_serial_out[1]; piso_parallel_in_serial_out_4[2]: A, parallel_in_serial_out_0[1]:B, parallel_in_serial_out[1]:Q. NET parallel_in_serial_out_1[1]; parallel_in_serial_out[1]:D, parallel_in_serial_out_1[1]:Y. NET parallel_in_serial_out_0[1]; parallel_in_serial_out_1[1]:A, parallel_in_serial_out_0[1]:Y. NET parallel_in_serial_out_4[1]; parallel_in_serial_out_0[1]:A, piso_parallel_in_serial_out_4[1]:Y. NET parallel_in_serial_out[0]; piso_parallel_in_serial_out_4[1]: A, parallel_in_serial_out_0[0]:B, parallel_in_serial_out[0]:Q. NET parallel_in_serial_out_1[0]; parallel_in_serial_out[0]:D, parallel_in_serial_out_1[0]:Y. NET parallel_in_serial_out_0[0]; parallel_in_serial_out_1[0]:A, parallel_in_serial_out_0[0]:Y. NET parallel_in_serial_out_4[0]; parallel_in_serial_out_0[0]:A, piso_parallel_in_serial_out_4[0]:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF mxfe_clock_generator; mhz_20_clock_9, read_clock_enable_i_0_i, reset_0, shift_configuration_data, spi_clock_opad_c, reset_1, dac_clock_enable, write_clock_enable. PIN mhz_20_clock_9; DIRECTION:INPUT. PIN read_clock_enable_i_0_i; DIRECTION:OUTPUT. PIN reset_0; DIRECTION:INPUT. PIN shift_configuration_data; DIRECTION:INPUT. PIN spi_clock_opad_c; DIRECTION:OUTPUT. PIN reset_1; DIRECTION:INPUT. PIN dac_clock_enable; DIRECTION:INPUT. PIN write_clock_enable; DIRECTION:OUTPUT. USE ADLIB:NOR2FT; toggle_q_1. USE ADLIB:XOR2FT; toggle_q_0. USE ADLIB:XOR2; gated_clock_q_0. USE ADLIB:NOR2FT; gated_clock_q_1. USE ADLIB:DFF; toggle_q. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2; read_clock_enable_out. USE ADLIB:NOR2FT; gated_clock_ff_un1_gate_clock_in. USE ADLIB:DFF; gated_clock_q. USE ADLIB:OR2FT; write_clock_enable_out. USE ADLIB:GND; GND_i. NET mhz_20_clock_9; mhz_20_clock_9, gated_clock_q:CLK, toggle_q: CLK. NET read_clock_enable_i_0_i; read_clock_enable_i_0_i, read_clock_enable_out:Y. NET reset_0; reset_0, toggle_q_1:B. NET shift_configuration_data; shift_configuration_data, gated_clock_ff_un1_gate_clock_in:A. NET spi_clock_opad_c; spi_clock_opad_c, gated_clock_q:Q, gated_clock_q_0:B. NET reset_1; reset_1, gated_clock_q_1:B. NET dac_clock_enable; dac_clock_enable, write_clock_enable_out:B, gated_clock_ff_un1_gate_clock_in:B, read_clock_enable_out:B, toggle_q_0:A. NET write_clock_enable; write_clock_enable, write_clock_enable_out:Y. NET toggle_q; read_clock_enable_out:A, write_clock_enable_out:A, toggle_q_0:B, toggle_q:Q. NET gated_clock_q_1; gated_clock_q:D, gated_clock_q_1:Y. NET N_1; gated_clock_q_1:A, gated_clock_q_0:Y. NET un1_gate_clock_in; gated_clock_q_0:A, gated_clock_ff_un1_gate_clock_in:Y. NET toggle_q_1; toggle_q:D, toggle_q_1:Y. NET toggle_q_0; toggle_q_1:A, toggle_q_0:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF mxfe_serializer_fsm; mhz_20_clock_9, mhz_20_clock_8, spi_cs_n_opad_c, shift_configuration_data, configuration_busy, shift_mxfe_data, reset_3, load_configuration_data, reset_4, write_clock_enable, mxfe_start, read_clock_enable_i_0_i, one_n_or_two, reset, write_n_or_read, load_configuration_data_0, mhz_20_clock_1, load_configuration_data_1. PIN mhz_20_clock_9; DIRECTION:INPUT. PIN mhz_20_clock_8; DIRECTION:INPUT. PIN spi_cs_n_opad_c; DIRECTION:OUTPUT. PIN shift_configuration_data; DIRECTION:OUTPUT. PIN configuration_busy; DIRECTION:OUTPUT. PIN shift_mxfe_data; DIRECTION:OUTPUT. PIN reset_3; DIRECTION:INPUT. PIN load_configuration_data; DIRECTION:OUTPUT. PIN reset_4; DIRECTION:INPUT. PIN write_clock_enable; DIRECTION:INPUT. PIN mxfe_start; DIRECTION:INPUT. PIN read_clock_enable_i_0_i; DIRECTION:INPUT. PIN one_n_or_two; DIRECTION:INPUT. PIN reset; DIRECTION:INPUT. PIN write_n_or_read; DIRECTION:INPUT. PIN load_configuration_data_0; DIRECTION:OUTPUT. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN load_configuration_data_1; DIRECTION:OUTPUT. USE ADLIB:DFF; int_load_configuration_data_out. USE ADLIB:OR3; next_state_srsts_0[0]. USE ADLIB:NOR3; next_state_nss_i_i[0]. USE ADLIB:DFF; int_done_out. USE ADLIB:AO21; next_state_srsts_i_a3[2]. USE ADLIB:XOR2; un1_counter_I_17. USE ADLIB:OA21; next_state_srsts_i[4]. USE ADLIB:NOR3FFT; next_state_srsts_i[2]. USE ADLIB:OR2FT; un1_next_state_9_0. USE ADLIB:AND2; next_state_CurrentState_counter_6[3]. USE ADLIB:DFF; counter[2]. USE ADLIB:AND2; next_state_CurrentState_counter_6[4]. USE ADLIB:AND2; next_state_srsts_i_o3_1[3]. USE ADLIB:DFF; next_state[1]. USE ADLIB:DFF; next_state[0]. USE ADLIB:OR2; un1_next_state_12_0. USE ADLIB:NOR2; next_state_srsts_i_o3_0[5]. USE ADLIB:NOR2FT; int_shift_configuration_data_out_1. USE ADLIB:AND2; next_state_CurrentState_counter_6[2]. USE ADLIB:DFF; next_state[5]. USE ADLIB:MUX2H; int_shift_mxfe_register_data_out_0. USE ADLIB:AND2; un1_counter_I_25. USE ADLIB:MUX2H; int_shift_configuration_data_out_0. USE ADLIB:NOR3FFT; next_state_srsts_0_a3_1[0]. USE ADLIB:NAND3FTT; next_state_srsts_0_a3_0_1[0]. USE ADLIB:NOR3; next_state_srsts_i[5]. USE ADLIB:NOR3FTT; next_state_srsts_0_a3_2[0]. USE ADLIB:XOR2; un1_counter_I_20. USE ADLIB:AND2; un1_counter_I_28. USE ADLIB:DFF; next_state_i[6]. USE ADLIB:AND2; next_state_srsts_0_o3_0_0[0]. USE ADLIB:NOR2FT; int_load_configuration_data_out_1. USE ADLIB:DFF; int_load_configuration_data_out_0_0. USE ADLIB:DFF; int_configure_mxfe_out. USE ADLIB:AND2FT; next_state_nss_i_i_a3[0]. USE ADLIB:MUX2H; int_load_configuration_data_out_0. USE ADLIB:OR2; int_configure_mxfe_out_1. USE ADLIB:NOR2FT; un1_reset_in_1_i. USE ADLIB:DFF; counter[4]. USE ADLIB:NOR2; next_state_srsts_i_a3_0[1]. USE ADLIB:NOR2; next_state_srsts_i_1[4]. USE ADLIB:NOR3FTT; next_state_srsts_i_a3_0[5]. USE ADLIB:OR2FT; un1_next_state_2_0. USE ADLIB:GND; GND_i. USE ADLIB:DFF; next_state[2]. USE ADLIB:NAND3; next_state_srsts_0_o3[0]. USE ADLIB:XOR2; un1_counter_I_22. USE ADLIB:DFF; counter[1]. USE ADLIB:AND2; next_state_CurrentState_counter_6[1]. USE ADLIB:DFF; next_state[4]. USE ADLIB:DFF; counter[3]. USE ADLIB:NOR2; next_state_nss_i_i_a3_0[0]. USE ADLIB:XOR2; un1_counter_I_19. USE ADLIB:OA21; next_state_srsts_i[3]. USE ADLIB:DFF; int_shift_configuration_data_out. USE ADLIB:AND2; un1_counter_I_1. USE ADLIB:PWR; PWR_i. USE ADLIB:MUX2H; int_configure_mxfe_out_0. USE ADLIB:NOR2FT; int_done_out_1. USE ADLIB:AOI21TTF; next_state_srsts_i_a3[1]. USE ADLIB:OR3; next_state_srsts_0_a3_0[0]. USE ADLIB:NOR2; next_state_srsts_i_a3[5]. USE ADLIB:DFF; int_shift_mxfe_register_data_out. USE ADLIB:OAI21FTT; un1_next_state_10_0. USE ADLIB:XOR2; un1_counter_I_21. USE ADLIB:AND2; un1_counter_I_26. USE ADLIB:AND2; un1_counter_I_27. USE ADLIB:NOR2FT; next_state_srsts_i_o3[5]. USE ADLIB:AND2; next_state_CurrentState_counter_6[0]. USE ADLIB:AND2FT; next_state_srsts_i_o3_0[3]. USE ADLIB:NOR3; next_state_srsts_i[1]. USE ADLIB:NOR2FT; int_shift_mxfe_register_data_out_1. USE ADLIB:AO21TTF; next_state_srsts_0_0[0]. USE ADLIB:AND2; next_state_srsts_i_o3[4]. USE ADLIB:DFF; next_state[3]. USE ADLIB:AND2; next_state_srsts_i_o3[3]. USE ADLIB:AND3FFT; counter_0_sqmuxa_0_a3. USE ADLIB:MUX2H; int_done_out_0. USE ADLIB:DFF; int_load_configuration_data_out_1_0. USE ADLIB:AND2; next_state_srsts_0_o3_0[0]. USE ADLIB:NOR2FT; next_state_srsts_0_a3_0_3[0]. USE ADLIB:INV; int_configure_mxfe_out_0_i. USE ADLIB:DFF; counter[0]. NET mhz_20_clock_9; mhz_20_clock_9, counter[0]:CLK, next_state[3]:CLK, counter[3]:CLK, next_state[4]:CLK, counter[1]:CLK, next_state[2]:CLK, counter[4]:CLK, next_state[0]:CLK, next_state[1]:CLK, counter[2]:CLK. NET mhz_20_clock_8; mhz_20_clock_8, int_shift_mxfe_register_data_out:CLK, int_shift_configuration_data_out:CLK, int_configure_mxfe_out: CLK, next_state_i[6]:CLK, next_state[5]:CLK, int_done_out:CLK, int_load_configuration_data_out:CLK. NET spi_cs_n_opad_c; spi_cs_n_opad_c, int_configure_mxfe_out_0:A, int_configure_mxfe_out:Q. NET shift_configuration_data; shift_configuration_data, int_shift_configuration_data_out:Q, int_shift_configuration_data_out_0:A. NET configuration_busy; configuration_busy, int_done_out_0:A, int_done_out:Q. NET shift_mxfe_data; shift_mxfe_data, int_shift_mxfe_register_data_out:Q, int_shift_mxfe_register_data_out_0:A. NET reset_3; reset_3, int_shift_mxfe_register_data_out_1:B, int_done_out_1:B, int_shift_configuration_data_out_1:B. NET load_configuration_data; load_configuration_data, int_load_configuration_data_out_0:A, int_load_configuration_data_out:Q. NET reset_4; reset_4, next_state_srsts_0_a3_0_3[0]:B, next_state_srsts_0_a3_0[0]:A, int_load_configuration_data_out_1: B, next_state_srsts_0_a3_2[0]:B, next_state_srsts_0_a3_1[0]:C. NET write_clock_enable; write_clock_enable, next_state_srsts_0_0[0]:A, next_state_srsts_i_o3[5]:B, un1_next_state_10_0:B, next_state_srsts_i_a3[1]:A, next_state_nss_i_i_a3[0]:A. NET mxfe_start; mxfe_start, next_state_nss_i_i_a3_0[0]:B, next_state_srsts_i_a3_0[1]:B. NET read_clock_enable_i_0_i; read_clock_enable_i_0_i, counter_0_sqmuxa_0_a3:C, next_state_srsts_0_o3[0]:A. NET one_n_or_two; one_n_or_two, next_state_srsts_0_a3_2[0]:C, next_state_srsts_i_a3[2]:B. NET reset; reset, next_state_srsts_i[1]:C, next_state_srsts_i_1[4]:B, un1_reset_in_1_i:B, int_configure_mxfe_out_1:B, next_state_srsts_i[5]:C, next_state_srsts_i[2]:C, next_state_nss_i_i[0]:C. NET write_n_or_read; write_n_or_read, next_state_srsts_i_o3[4]:B, next_state_srsts_i_o3_0[3]:A. NET load_configuration_data_0; load_configuration_data_0, int_load_configuration_data_out_0_0:Q. NET mhz_20_clock_1; mhz_20_clock_1, int_load_configuration_data_out_1_0:CLK, int_load_configuration_data_out_0_0:CLK. NET load_configuration_data_1; load_configuration_data_1, int_load_configuration_data_out_1_0:Q. NET int_load_configuration_data_out_1; int_load_configuration_data_out:D, int_load_configuration_data_out_1_0:D, int_load_configuration_data_out_0_0:D, int_load_configuration_data_out_1:Y. NET DWACT_ADD_CI_0_g_array_2[0]; un1_counter_I_22:B, un1_counter_I_27:Y. NET DWACT_ADD_CI_0_g_array_1[0]; un1_counter_I_25:A, un1_counter_I_27:A, un1_counter_I_26:Y, un1_counter_I_20:B. NET DWACT_ADD_CI_0_pog_array_1[0]; un1_counter_I_27:B, un1_counter_I_28:Y. NET DWACT_ADD_CI_0_g_array_12[0]; un1_counter_I_21:B, un1_counter_I_25:Y. NET counter[2]; un1_counter_I_20:A, next_state_srsts_0_o3_0_0[0]: B, un1_counter_I_28:A, un1_counter_I_25:B, counter[2]:Q. NET DWACT_ADD_CI_0_TMP[0]; un1_counter_I_26:A, un1_counter_I_19: B, un1_counter_I_1:Y. NET counter[1]; next_state_srsts_0_o3_0_0[0]:A, un1_counter_I_26: B, un1_counter_I_19:A, counter[1]:Q. NET N_77_i_0; next_state[3]:D, next_state_srsts_i[3]:Y. NET next_state_srsts_i_o3_0[3]; next_state_srsts_i[3]:A, next_state_srsts_i_o3_0[3]:Y. NET next_state[3]; next_state_srsts_i[3]:B, next_state_srsts_0_o3_0[0]:B, next_state[3]:Q. NET N_79_1_i_i; next_state_srsts_i[4]:C, next_state_srsts_i[3]:C, next_state_srsts_i_1[4]:Y. NET N_92; next_state_srsts_i_o3[4]:A, next_state_srsts_i_o3_0[3]: B, next_state_srsts_i_o3_1[3]:Y. NET N_75_i_0; next_state[2]:D, next_state_srsts_i[2]:Y. NET N_102_i; next_state_srsts_i[2]:A, next_state_srsts_0_0[0]:C, next_state_srsts_0_a3_0[0]:Y. NET N_107; next_state_srsts_i[2]:B, next_state_srsts_i_a3[2]:Y. NET N_94; next_state_srsts_i_a3[2]:A, next_state_srsts_0_o3_0[0]: Y, next_state_srsts_0_a3_2[0]:A. NET next_state[2]; next_state_srsts_i_a3[2]:C, next_state[2]:Q, next_state_srsts_0_a3_0_1[0]:C. NET counter_0_sqmuxa; un1_counter_I_17:B, counter_0_sqmuxa_0_a3: Y, un1_counter_I_1:B. NET next_state[1]; next_state_srsts_i_a3_0[1]:A, counter_0_sqmuxa_0_a3:A, next_state_srsts_i_o3[5]:A, next_state_srsts_i_a3[1]:B, next_state_srsts_i_a3_0[5]:B, int_load_configuration_data_out_0:B, next_state[1]:Q. NET next_state[0]; next_state_srsts_0_a3_0_3[0]:A, next_state_nss_i_i_a3[0]:B, counter_0_sqmuxa_0_a3:B, next_state[0]:Q. NET next_state_nss_i_i[0]; next_state_i[6]:D, next_state_nss_i_i[0]:Y. NET N_113; next_state_nss_i_i[0]:A, next_state_nss_i_i_a3[0]:Y, un1_next_state_9_0:B. NET N_114; next_state_nss_i_i[0]:B, next_state_nss_i_i_a3_0[0]:Y. NET next_state_i[6]; un1_next_state_9_0:A, int_done_out_0:B, un1_next_state_10_0:C, next_state_srsts_i_a3[1]:C, next_state_nss_i_i_a3_0[0]:A, un1_next_state_2_0:A, un1_reset_in_1_i:A, next_state_i[6]:Q, int_shift_configuration_data_out_0:B, int_shift_mxfe_register_data_out_0:B. NET next_state_srsts_i[5]; next_state[5]:D, next_state_srsts_i[5]:Y. NET N_111; next_state_srsts_i[5]:A, next_state_srsts_i_a3[5]:Y. NET N_112; next_state_srsts_i[5]:B, next_state_srsts_i_a3_0[5]:Y. NET N_90; next_state_srsts_i_a3_0[5]:A, next_state_srsts_i_o3[3]: A, next_state_srsts_i_o3_1[3]:B, next_state_srsts_i_o3_0[5]:Y. NET counter[3]; next_state_srsts_0_a3_0_1[0]:A, next_state_srsts_i_o3[3]:B, un1_counter_I_21:A, counter[3]:Q, next_state_srsts_i_a3_0[5]:C, un1_counter_I_28:B. NET N_93; un1_next_state_12_0:A, next_state_srsts_i_o3[5]:Y, next_state_srsts_i_a3[5]:A. NET next_state[5]; next_state_srsts_i_o3_1[3]:A, int_configure_mxfe_out_0_i:A, next_state_srsts_i_a3[5]:B, un1_next_state_2_0:B, next_state[5]:Q. NET next_state_srsts_i[4]; next_state[4]:D, next_state_srsts_i[4]:Y. NET next_state_srsts_i_o3[4]; next_state_srsts_i[4]:A, next_state_srsts_i_o3[4]:Y. NET next_state[4]; next_state_srsts_0_a3_1[0]:A, un1_next_state_10_0:A, next_state[4]:Q, next_state_srsts_i[4]:B. NET N_91_i_0; next_state_srsts_i_1[4]:A, next_state_srsts_0_o3_0[0]:A, next_state_srsts_i_o3[3]:Y, next_state_srsts_0_a3_1[0]:B. NET next_state_srsts_i[1]; next_state[1]:D, next_state_srsts_i[1]:Y. NET N_105; next_state_srsts_i[1]:A, next_state_srsts_i_a3[1]:Y. NET N_106; next_state_srsts_i[1]:B, next_state_srsts_i_a3_0[1]:Y. NET next_state_nss[6]; next_state[0]:D, next_state_srsts_0[0]:Y. NET N_104_i; next_state_srsts_0[0]:A, next_state_srsts_0_a3_2[0]: Y. NET N_103_i; next_state_srsts_0[0]:B, next_state_srsts_0_a3_1[0]: Y. NET next_state_srsts_0_0_i[0]; next_state_srsts_0[0]:C, next_state_srsts_0_0[0]:Y. NET next_state_srsts_0_a3_0[0]; next_state_srsts_0_0[0]:B, next_state_srsts_0_a3_0_3[0]:Y. NET next_state_srsts_0_o3[0]; next_state_srsts_i_o3_0[5]:A, next_state_srsts_0_a3_0[0]:B, next_state_srsts_0_o3[0]:Y. NET next_state_srsts_0_a3_0_1_i[0]; next_state_srsts_0_a3_0[0]:C, next_state_srsts_0_a3_0_1[0]:Y. NET counter[4]; un1_counter_I_22:A, next_state_srsts_i_o3_0[5]:B, counter[4]:Q, next_state_srsts_0_a3_0_1[0]:B. NET next_state_srsts_0_o3_0[0]; next_state_srsts_0_o3[0]:B, next_state_srsts_0_o3_0_0[0]:Y. NET counter[0]; un1_counter_I_17:A, counter[0]:Q, un1_counter_I_1:A, next_state_srsts_0_o3[0]:C. NET int_load_configuration_data_out_0; int_load_configuration_data_out_1:A, int_load_configuration_data_out_0:Y. NET un1_next_state_12; int_load_configuration_data_out_0:S, un1_next_state_12_0:Y. NET un1_next_state_2; un1_next_state_12_0:B, int_configure_mxfe_out_0:S, un1_next_state_2_0:Y, int_shift_configuration_data_out_0:S. NET int_shift_mxfe_register_data_out_1; int_shift_mxfe_register_data_out:D, int_shift_mxfe_register_data_out_1:Y. NET int_shift_mxfe_register_data_out_0; int_shift_mxfe_register_data_out_1:A, int_shift_mxfe_register_data_out_0:Y. NET un1_next_state_10; int_shift_mxfe_register_data_out_0:S, un1_next_state_10_0:Y. NET int_done_out_1; int_done_out:D, int_done_out_1:Y. NET N_6; int_done_out_1:A, int_done_out_0:Y. NET un1_next_state_9; int_done_out_0:S, un1_next_state_9_0:Y. NET int_shift_configuration_data_out_1; int_shift_configuration_data_out:D, int_shift_configuration_data_out_1:Y. NET int_shift_configuration_data_out_0; int_shift_configuration_data_out_1:A, int_shift_configuration_data_out_0:Y. NET int_configure_mxfe_out_1; int_configure_mxfe_out:D, int_configure_mxfe_out_1:Y. NET int_configure_mxfe_out_0; int_configure_mxfe_out_1:A, int_configure_mxfe_out_0:Y. NET next_state_i_0[5]; int_configure_mxfe_out_0:B, int_configure_mxfe_out_0_i:Y. NET counter_6[4]; counter[4]:D, next_state_CurrentState_counter_6[4]:Y. NET N_69; next_state_CurrentState_counter_6[3]:A, next_state_CurrentState_counter_6[0]:A, next_state_CurrentState_counter_6[1]:A, un1_reset_in_1_i:Y, next_state_CurrentState_counter_6[2]:A, next_state_CurrentState_counter_6[4]:A. NET I_22; next_state_CurrentState_counter_6[4]:B, un1_counter_I_22:Y. NET counter_6[3]; counter[3]:D, next_state_CurrentState_counter_6[3]:Y. NET I_21; next_state_CurrentState_counter_6[3]:B, un1_counter_I_21:Y. NET counter_6[2]; counter[2]:D, next_state_CurrentState_counter_6[2]:Y. NET I_20; next_state_CurrentState_counter_6[2]:B, un1_counter_I_20:Y. NET counter_6[1]; counter[1]:D, next_state_CurrentState_counter_6[1]:Y. NET I_19; next_state_CurrentState_counter_6[1]:B, un1_counter_I_19:Y. NET counter_6[0]; counter[0]:D, next_state_CurrentState_counter_6[0]:Y. NET DWACT_ADD_CI_0_partial_sum[0]; next_state_CurrentState_counter_6[0]:B, un1_counter_I_17:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF sipo_shift_register; mxfe_register_data<7>, mxfe_register_data<6>, mxfe_register_data<5>, mxfe_register_data<4>, mxfe_register_data<3>, mxfe_register_data<2>, mxfe_register_data<1>, mxfe_register_data<0>, mhz_20_clock_10, shift_mxfe_data, read_clock_enable_i_0_i, spi_dio_ipad_c, reset_0; BUSFORMAT: %s<%d>. PIN mxfe_register_data<7>; ENM:'mxfe_register_data<7:0>', BUS:0, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:0/7/0/0. PIN mxfe_register_data<6>; ENM:'mxfe_register_data<7:0>', BUS:1, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:1/7/0/0. PIN mxfe_register_data<5>; ENM:'mxfe_register_data<7:0>', BUS:2, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:2/7/0/0. PIN mxfe_register_data<4>; ENM:'mxfe_register_data<7:0>', BUS:3, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:3/7/0/0. PIN mxfe_register_data<3>; ENM:'mxfe_register_data<7:0>', BUS:4, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:4/7/0/0. PIN mxfe_register_data<2>; ENM:'mxfe_register_data<7:0>', BUS:5, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:5/7/0/0. PIN mxfe_register_data<1>; ENM:'mxfe_register_data<7:0>', BUS:6, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:6/7/0/0. PIN mxfe_register_data<0>; ENM:'mxfe_register_data<7:0>', BUS:7, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:7/7/0/0. PIN mhz_20_clock_10; DIRECTION:INPUT. PIN shift_mxfe_data; DIRECTION:INPUT. PIN read_clock_enable_i_0_i; DIRECTION:INPUT. PIN spi_dio_ipad_c; DIRECTION:INPUT. PIN reset_0; DIRECTION:INPUT. USE ADLIB:MUX2H; serial_in_parallel_out_0[1]. USE ADLIB:NOR2FT; serial_in_parallel_out_1[4]. USE ADLIB:MUX2H; serial_in_parallel_out_0[2]. USE ADLIB:NOR2FT; serial_in_parallel_out_1[2]. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2FT; serial_in_parallel_out_1[5]. USE ADLIB:MUX2H; serial_in_parallel_out_0[6]. USE ADLIB:MUX2H; serial_in_parallel_out_0[3]. USE ADLIB:NOR2FT; serial_in_parallel_out_1[7]. USE ADLIB:NOR2FT; serial_in_parallel_out_1[0]. USE ADLIB:MUX2H; serial_in_parallel_out_0[4]. USE ADLIB:MUX2H; serial_in_parallel_out_0[0]. USE ADLIB:DFF; serial_in_parallel_out[2]. USE ADLIB:NOR2FT; serial_in_parallel_out_1[6]. USE ADLIB:NOR2FT; serial_in_parallel_out_1[3]. USE ADLIB:DFF; serial_in_parallel_out[3]. USE ADLIB:GND; GND_i. USE ADLIB:MUX2H; serial_in_parallel_out_0[7]. USE ADLIB:DFF; serial_in_parallel_out[5]. USE ADLIB:DFF; serial_in_parallel_out[4]. USE ADLIB:DFF; serial_in_parallel_out[1]. USE ADLIB:DFF; serial_in_parallel_out[0]. USE ADLIB:DFF; serial_in_parallel_out[6]. USE ADLIB:NOR2FT; serial_in_parallel_out_1[1]. USE ADLIB:AND2; sipo_un1_shift_in. USE ADLIB:DFF; serial_in_parallel_out[7]. USE ADLIB:MUX2H; serial_in_parallel_out_0[5]. NET mxfe_register_data[0]; mxfe_register_data<0>, serial_in_parallel_out[0]:Q, serial_in_parallel_out_0[0]:A, serial_in_parallel_out_0[1]:B. NET mxfe_register_data[1]; mxfe_register_data<1>, serial_in_parallel_out[1]:Q, serial_in_parallel_out_0[2]:B, serial_in_parallel_out_0[1]:A. NET mxfe_register_data[2]; mxfe_register_data<2>, serial_in_parallel_out[2]:Q, serial_in_parallel_out_0[3]:B, serial_in_parallel_out_0[2]:A. NET mxfe_register_data[3]; mxfe_register_data<3>, serial_in_parallel_out[3]:Q, serial_in_parallel_out_0[4]:B, serial_in_parallel_out_0[3]:A. NET mxfe_register_data[4]; mxfe_register_data<4>, serial_in_parallel_out_0[5]:B, serial_in_parallel_out[4]:Q, serial_in_parallel_out_0[4]:A. NET mxfe_register_data[5]; mxfe_register_data<5>, serial_in_parallel_out_0[5]:A, serial_in_parallel_out[5]:Q, serial_in_parallel_out_0[6]:B. NET mxfe_register_data[6]; mxfe_register_data<6>, serial_in_parallel_out[6]:Q, serial_in_parallel_out_0[7]:B, serial_in_parallel_out_0[6]:A. NET mxfe_register_data[7]; mxfe_register_data<7>, serial_in_parallel_out[7]:Q, serial_in_parallel_out_0[7]:A. NET mhz_20_clock_10; mhz_20_clock_10, serial_in_parallel_out[7]: CLK, serial_in_parallel_out[6]:CLK, serial_in_parallel_out[0]: CLK, serial_in_parallel_out[1]:CLK, serial_in_parallel_out[4]: CLK, serial_in_parallel_out[5]:CLK, serial_in_parallel_out[3]: CLK, serial_in_parallel_out[2]:CLK. NET shift_mxfe_data; shift_mxfe_data, sipo_un1_shift_in:B. NET read_clock_enable_i_0_i; read_clock_enable_i_0_i, sipo_un1_shift_in:A. NET spi_dio_ipad_c; spi_dio_ipad_c, serial_in_parallel_out_0[0]: B. NET reset_0; reset_0, serial_in_parallel_out_1[1]:B, serial_in_parallel_out_1[3]:B, serial_in_parallel_out_1[6]:B, serial_in_parallel_out_1[0]:B, serial_in_parallel_out_1[7]:B, serial_in_parallel_out_1[5]:B, serial_in_parallel_out_1[2]:B, serial_in_parallel_out_1[4]:B. NET serial_in_parallel_out_1[7]; serial_in_parallel_out[7]:D, serial_in_parallel_out_1[7]:Y. NET serial_in_parallel_out_0[7]; serial_in_parallel_out_1[7]:A, serial_in_parallel_out_0[7]:Y. NET un1_shift_in; serial_in_parallel_out_0[1]:S, serial_in_parallel_out_0[5]:S, sipo_un1_shift_in:Y, serial_in_parallel_out_0[7]:S, serial_in_parallel_out_0[0]:S, serial_in_parallel_out_0[4]:S, serial_in_parallel_out_0[3]:S, serial_in_parallel_out_0[6]:S, serial_in_parallel_out_0[2]:S. NET serial_in_parallel_out_1[6]; serial_in_parallel_out[6]:D, serial_in_parallel_out_1[6]:Y. NET serial_in_parallel_out_0[6]; serial_in_parallel_out_1[6]:A, serial_in_parallel_out_0[6]:Y. NET serial_in_parallel_out_1[5]; serial_in_parallel_out[5]:D, serial_in_parallel_out_1[5]:Y. NET serial_in_parallel_out_0[5]; serial_in_parallel_out_1[5]:A, serial_in_parallel_out_0[5]:Y. NET serial_in_parallel_out_1[4]; serial_in_parallel_out[4]:D, serial_in_parallel_out_1[4]:Y. NET serial_in_parallel_out_0[4]; serial_in_parallel_out_1[4]:A, serial_in_parallel_out_0[4]:Y. NET serial_in_parallel_out_1[3]; serial_in_parallel_out[3]:D, serial_in_parallel_out_1[3]:Y. NET serial_in_parallel_out_0[3]; serial_in_parallel_out_1[3]:A, serial_in_parallel_out_0[3]:Y. NET serial_in_parallel_out_1[2]; serial_in_parallel_out[2]:D, serial_in_parallel_out_1[2]:Y. NET serial_in_parallel_out_0[2]; serial_in_parallel_out_1[2]:A, serial_in_parallel_out_0[2]:Y. NET serial_in_parallel_out_1[1]; serial_in_parallel_out[1]:D, serial_in_parallel_out_1[1]:Y. NET serial_in_parallel_out_0[1]; serial_in_parallel_out_1[1]:A, serial_in_parallel_out_0[1]:Y. NET serial_in_parallel_out_1[0]; serial_in_parallel_out[0]:D, serial_in_parallel_out_1[0]:Y. NET serial_in_parallel_out_0[0]; serial_in_parallel_out_1[0]:A, serial_in_parallel_out_0[0]:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF mxfe_configurator; mxfe_configuration_data<21>, mxfe_configuration_data<20>, mxfe_configuration_data<19>, mxfe_configuration_data<18>, mxfe_configuration_data<17>, mxfe_configuration_data<16>, mxfe_configuration_data<15>, mxfe_configuration_data<14>, mxfe_configuration_data<13>, mxfe_configuration_data<12>, mxfe_configuration_data<11>, mxfe_configuration_data<10>, mxfe_configuration_data<9>, mxfe_configuration_data<8>, mxfe_configuration_data<7>, mxfe_configuration_data<6>, mxfe_configuration_data<5>, mxfe_configuration_data<4>, mxfe_configuration_data<3>, mxfe_configuration_data<2>, mxfe_configuration_data<1>, mxfe_configuration_data<0>, mxfe_register_data<7>, mxfe_register_data<6>, mxfe_register_data<5>, mxfe_register_data<4>, mxfe_register_data<3>, mxfe_register_data<2>, mxfe_register_data<1>, mxfe_register_data<0>, dac_clock_enable, reset_1, spi_clock_opad_c, mhz_20_clock_1, reset, mxfe_start, reset_3, configuration_busy, spi_cs_n_opad_c, mhz_20_clock_9, reset_6, spi_sdo_opad_c, write_n_or_read, one_n_or_two, reset_5, reset_4, mhz_20_clock_6, mhz_20_clock_7, mhz_20_clock_8, reset_0, spi_dio_ipad_c, mhz_20_clock_10; BUSFORMAT:%s<%d>. PIN mxfe_configuration_data<21>; ENM: 'mxfe_configuration_data<21:0>', BUS:0, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:0/21/0/0. PIN mxfe_configuration_data<20>; ENM: 'mxfe_configuration_data<21:0>', BUS:1, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:1/21/0/0. PIN mxfe_configuration_data<19>; ENM: 'mxfe_configuration_data<21:0>', BUS:2, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:2/21/0/0. PIN mxfe_configuration_data<18>; ENM: 'mxfe_configuration_data<21:0>', BUS:3, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:3/21/0/0. PIN mxfe_configuration_data<17>; ENM: 'mxfe_configuration_data<21:0>', BUS:4, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:4/21/0/0. PIN mxfe_configuration_data<16>; ENM: 'mxfe_configuration_data<21:0>', BUS:5, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:5/21/0/0. PIN mxfe_configuration_data<15>; ENM: 'mxfe_configuration_data<21:0>', BUS:6, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:6/21/0/0. PIN mxfe_configuration_data<14>; ENM: 'mxfe_configuration_data<21:0>', BUS:7, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:7/21/0/0. PIN mxfe_configuration_data<13>; ENM: 'mxfe_configuration_data<21:0>', BUS:8, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:8/21/0/0. PIN mxfe_configuration_data<12>; ENM: 'mxfe_configuration_data<21:0>', BUS:9, DIRECTION:INPUT, ORIGNAME: mxfe_configuration_data, BUSINFO:9/21/0/0. PIN mxfe_configuration_data<11>; ENM: 'mxfe_configuration_data<21:0>', BUS:10, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:10/21/0/0. PIN mxfe_configuration_data<10>; ENM: 'mxfe_configuration_data<21:0>', BUS:11, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:11/21/0/0. PIN mxfe_configuration_data<9>; ENM:'mxfe_configuration_data<21:0>', BUS:12, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:12/21/0/0. PIN mxfe_configuration_data<8>; ENM:'mxfe_configuration_data<21:0>', BUS:13, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:13/21/0/0. PIN mxfe_configuration_data<7>; ENM:'mxfe_configuration_data<21:0>', BUS:14, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:14/21/0/0. PIN mxfe_configuration_data<6>; ENM:'mxfe_configuration_data<21:0>', BUS:15, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:15/21/0/0. PIN mxfe_configuration_data<5>; ENM:'mxfe_configuration_data<21:0>', BUS:16, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:16/21/0/0. PIN mxfe_configuration_data<4>; ENM:'mxfe_configuration_data<21:0>', BUS:17, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:17/21/0/0. PIN mxfe_configuration_data<3>; ENM:'mxfe_configuration_data<21:0>', BUS:18, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:18/21/0/0. PIN mxfe_configuration_data<2>; ENM:'mxfe_configuration_data<21:0>', BUS:19, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:19/21/0/0. PIN mxfe_configuration_data<1>; ENM:'mxfe_configuration_data<21:0>', BUS:20, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:20/21/0/0. PIN mxfe_configuration_data<0>; ENM:'mxfe_configuration_data<21:0>', BUS:21, DIRECTION:INPUT, ORIGNAME:mxfe_configuration_data, BUSINFO:21/21/0/0. PIN mxfe_register_data<7>; ENM:'mxfe_register_data<7:0>', BUS:0, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:0/7/0/0. PIN mxfe_register_data<6>; ENM:'mxfe_register_data<7:0>', BUS:1, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:1/7/0/0. PIN mxfe_register_data<5>; ENM:'mxfe_register_data<7:0>', BUS:2, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:2/7/0/0. PIN mxfe_register_data<4>; ENM:'mxfe_register_data<7:0>', BUS:3, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:3/7/0/0. PIN mxfe_register_data<3>; ENM:'mxfe_register_data<7:0>', BUS:4, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:4/7/0/0. PIN mxfe_register_data<2>; ENM:'mxfe_register_data<7:0>', BUS:5, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:5/7/0/0. PIN mxfe_register_data<1>; ENM:'mxfe_register_data<7:0>', BUS:6, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:6/7/0/0. PIN mxfe_register_data<0>; ENM:'mxfe_register_data<7:0>', BUS:7, DIRECTION:OUTPUT, ORIGNAME:mxfe_register_data, BUSINFO:7/7/0/0. PIN dac_clock_enable; DIRECTION:INPUT. PIN reset_1; DIRECTION:INPUT. PIN spi_clock_opad_c; DIRECTION:OUTPUT. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN reset; DIRECTION:INPUT. PIN mxfe_start; DIRECTION:INPUT. PIN reset_3; DIRECTION:INPUT. PIN configuration_busy; DIRECTION:OUTPUT. PIN spi_cs_n_opad_c; DIRECTION:OUTPUT. PIN mhz_20_clock_9; DIRECTION:INPUT. PIN reset_6; DIRECTION:INPUT. PIN spi_sdo_opad_c; DIRECTION:OUTPUT. PIN write_n_or_read; DIRECTION:INPUT. PIN one_n_or_two; DIRECTION:INPUT. PIN reset_5; DIRECTION:INPUT. PIN reset_4; DIRECTION:INPUT. PIN mhz_20_clock_6; DIRECTION:INPUT. PIN mhz_20_clock_7; DIRECTION:INPUT. PIN mhz_20_clock_8; DIRECTION:INPUT. PIN reset_0; DIRECTION:INPUT. PIN spi_dio_ipad_c; DIRECTION:INPUT. PIN mhz_20_clock_10; DIRECTION:INPUT. USE piso_shift_register; U2. USE mxfe_clock_generator; U4. USE ADLIB:PWR; PWR_i. USE mxfe_serializer_fsm; U3. USE sipo_shift_register; U1. USE ADLIB:GND; GND_i. NET mxfe_configuration_data[0]; mxfe_configuration_data<0>, U2: mxfe_configuration_data<0>. NET mxfe_configuration_data[1]; mxfe_configuration_data<1>, U2: mxfe_configuration_data<1>. NET mxfe_configuration_data[2]; mxfe_configuration_data<2>, U2: mxfe_configuration_data<2>. NET mxfe_configuration_data[3]; mxfe_configuration_data<3>, U2: mxfe_configuration_data<3>. NET mxfe_configuration_data[4]; mxfe_configuration_data<4>, U2: mxfe_configuration_data<4>. NET mxfe_configuration_data[5]; mxfe_configuration_data<5>, U2: mxfe_configuration_data<5>. NET mxfe_configuration_data[6]; mxfe_configuration_data<6>, U2: mxfe_configuration_data<6>. NET mxfe_configuration_data[7]; mxfe_configuration_data<7>, U2: mxfe_configuration_data<7>. NET mxfe_configuration_data[8]; mxfe_configuration_data<8>, U2: mxfe_configuration_data<8>. NET mxfe_configuration_data[9]; mxfe_configuration_data<9>, U2: mxfe_configuration_data<9>. NET mxfe_configuration_data[10]; mxfe_configuration_data<10>, U2: mxfe_configuration_data<10>. NET mxfe_configuration_data[11]; mxfe_configuration_data<11>, U2: mxfe_configuration_data<11>. NET mxfe_configuration_data[12]; mxfe_configuration_data<12>, U2: mxfe_configuration_data<12>. NET mxfe_configuration_data[13]; mxfe_configuration_data<13>, U2: mxfe_configuration_data<13>. NET mxfe_configuration_data[14]; mxfe_configuration_data<14>, U2: mxfe_configuration_data<14>. NET mxfe_configuration_data[15]; mxfe_configuration_data<15>, U2: mxfe_configuration_data<15>. NET mxfe_configuration_data[16]; mxfe_configuration_data<16>, U2: mxfe_configuration_data<16>. NET mxfe_configuration_data[17]; mxfe_configuration_data<17>, U2: mxfe_configuration_data<17>. NET mxfe_configuration_data[18]; mxfe_configuration_data<18>, U2: mxfe_configuration_data<18>. NET mxfe_configuration_data[19]; mxfe_configuration_data<19>, U2: mxfe_configuration_data<19>. NET mxfe_configuration_data[20]; mxfe_configuration_data<20>, U2: mxfe_configuration_data<20>. NET mxfe_configuration_data[21]; mxfe_configuration_data<21>, U2: mxfe_configuration_data<21>. NET mxfe_register_data[0]; mxfe_register_data<0>, U1: mxfe_register_data<0>. NET mxfe_register_data[1]; mxfe_register_data<1>, U1: mxfe_register_data<1>. NET mxfe_register_data[2]; mxfe_register_data<2>, U1: mxfe_register_data<2>. NET mxfe_register_data[3]; mxfe_register_data<3>, U1: mxfe_register_data<3>. NET mxfe_register_data[4]; mxfe_register_data<4>, U1: mxfe_register_data<4>. NET mxfe_register_data[5]; mxfe_register_data<5>, U1: mxfe_register_data<5>. NET mxfe_register_data[6]; mxfe_register_data<6>, U1: mxfe_register_data<6>. NET mxfe_register_data[7]; mxfe_register_data<7>, U1: mxfe_register_data<7>. NET dac_clock_enable; dac_clock_enable, U4:dac_clock_enable. NET reset_1; reset_1, U4:reset_1. NET spi_clock_opad_c; spi_clock_opad_c, U4:spi_clock_opad_c. NET mhz_20_clock_1; mhz_20_clock_1, U3:mhz_20_clock_1. NET reset; reset, U3:reset. NET mxfe_start; mxfe_start, U3:mxfe_start. NET reset_3; reset_3, U3:reset_3. NET configuration_busy; configuration_busy, U3: configuration_busy. NET spi_cs_n_opad_c; spi_cs_n_opad_c, U3:spi_cs_n_opad_c. NET mhz_20_clock_9; mhz_20_clock_9, U3:mhz_20_clock_9, U4: mhz_20_clock_9. NET reset_6; reset_6, U2:reset_6. NET spi_sdo_opad_c; spi_sdo_opad_c, U2:spi_sdo_opad_c. NET write_n_or_read; write_n_or_read, U3:write_n_or_read, U2: write_n_or_read. NET one_n_or_two; one_n_or_two, U3:one_n_or_two, U2:one_n_or_two. NET reset_5; reset_5, U2:reset_5. NET reset_4; reset_4, U3:reset_4, U2:reset_4. NET mhz_20_clock_6; mhz_20_clock_6, U2:mhz_20_clock_6. NET mhz_20_clock_7; mhz_20_clock_7, U2:mhz_20_clock_7. NET mhz_20_clock_8; mhz_20_clock_8, U3:mhz_20_clock_8, U2: mhz_20_clock_8. NET reset_0; reset_0, U1:reset_0, U4:reset_0. NET spi_dio_ipad_c; spi_dio_ipad_c, U1:spi_dio_ipad_c. NET mhz_20_clock_10; mhz_20_clock_10, U1:mhz_20_clock_10. NET shift_mxfe_data; U3:shift_mxfe_data, U1:shift_mxfe_data. NET read_clock_enable_i_0_i; U4:read_clock_enable_i_0_i, U1: read_clock_enable_i_0_i, U3:read_clock_enable_i_0_i. NET load_configuration_data; U2:load_configuration_data, U3: load_configuration_data. NET load_configuration_data_1; U2:load_configuration_data_1, U3: load_configuration_data_1. NET load_configuration_data_0; U2:load_configuration_data_0, U3: load_configuration_data_0. NET write_clock_enable; U2:write_clock_enable, U3: write_clock_enable, U4:write_clock_enable. NET shift_configuration_data; U2:shift_configuration_data, U3: shift_configuration_data, U4:shift_configuration_data. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF reset_synchronizer; reset, mhz_20_clock_6, reset_0, reset_1, reset_2, reset_3, reset_4, reset_5, reset_6, reset_7, reset_8, reset_9, mhz_20_clock_0, reset_10, async_reset_n_ipad_c. PIN reset; DIRECTION:OUTPUT. PIN mhz_20_clock_6; DIRECTION:INPUT. PIN reset_0; DIRECTION:OUTPUT. PIN reset_1; DIRECTION:OUTPUT. PIN reset_2; DIRECTION:OUTPUT. PIN reset_3; DIRECTION:OUTPUT. PIN reset_4; DIRECTION:OUTPUT. PIN reset_5; DIRECTION:OUTPUT. PIN reset_6; DIRECTION:OUTPUT. PIN reset_7; DIRECTION:OUTPUT. PIN reset_8; DIRECTION:OUTPUT. PIN reset_9; DIRECTION:OUTPUT. PIN mhz_20_clock_0; DIRECTION:INPUT. PIN reset_10; DIRECTION:OUTPUT. PIN async_reset_n_ipad_c; DIRECTION:INPUT. USE ADLIB:DFFS; sync_reset_out_3. USE ADLIB:DFFS; sync_reset_out. USE ADLIB:DFFS; sync_reset_out_10. USE ADLIB:PWR; PWR_i. USE ADLIB:INV; sync_reset_out_i_0. USE ADLIB:DFFS; sync_reset_out_4. USE ADLIB:DFFS; sync_reset_out_1. USE ADLIB:GND; GND_i. USE ADLIB:DFFS; sync_reset_out_8. USE ADLIB:DFFS; reset_ff. USE ADLIB:INV; sync_reset_out_i. USE ADLIB:DFFS; sync_reset_out_9. USE ADLIB:DFFS; sync_reset_out_2. USE ADLIB:DFFS; sync_reset_out_7. USE ADLIB:DFFS; sync_reset_out_5. USE ADLIB:DFFS; sync_reset_out_0. USE ADLIB:DFFS; sync_reset_out_6. NET reset; reset, sync_reset_out:Q. NET mhz_20_clock_6; mhz_20_clock_6, reset_ff:CLK, sync_reset_out: CLK. NET reset_0; reset_0, sync_reset_out_0:Q. NET reset_1; reset_1, sync_reset_out_1:Q. NET reset_2; reset_2, sync_reset_out_2:Q. NET reset_3; reset_3, sync_reset_out_3:Q. NET reset_4; reset_4, sync_reset_out_4:Q. NET reset_5; reset_5, sync_reset_out_5:Q. NET reset_6; reset_6, sync_reset_out_6:Q. NET reset_7; reset_7, sync_reset_out_7:Q. NET reset_8; reset_8, sync_reset_out_8:Q. NET reset_9; reset_9, sync_reset_out_9:Q. NET mhz_20_clock_0; mhz_20_clock_0, sync_reset_out_6:CLK, sync_reset_out_0:CLK, sync_reset_out_5:CLK, sync_reset_out_7: CLK, sync_reset_out_2:CLK, sync_reset_out_9:CLK, sync_reset_out_8:CLK, sync_reset_out_1:CLK, sync_reset_out_4: CLK, sync_reset_out_10:CLK, sync_reset_out_3:CLK. NET reset_10; reset_10, sync_reset_out_10:Q. NET async_reset_n_ipad_c; async_reset_n_ipad_c, sync_reset_out_i: A, sync_reset_out_i_0:A. NET async_reset_n_ipad_c_i_0_0; sync_reset_out_10:SET, sync_reset_out_6:SET, sync_reset_out_5:SET, sync_reset_out_7: SET, sync_reset_out_9:SET, sync_reset_out_8:SET, sync_reset_out_4:SET, sync_reset_out_i_0:Y. NET reset_ff; sync_reset_out_3:D, sync_reset_out_6:D, sync_reset_out_0:D, sync_reset_out_5:D, sync_reset_out_7:D, sync_reset_out_2:D, sync_reset_out_9:D, reset_ff:Q, sync_reset_out_8:D, sync_reset_out_1:D, sync_reset_out_4:D, sync_reset_out_10:D, sync_reset_out:D. NET async_reset_n_ipad_c_i_0; sync_reset_out_3:SET, sync_reset_out_0:SET, sync_reset_out_2:SET, sync_reset_out_i:Y, reset_ff:SET, sync_reset_out_1:SET, sync_reset_out:SET. NET GND; reset_ff:D, GND_i:Y. NET VCC; PWR_i:Y. END. DEF piso_shift_register_1; dac_data<23>, dac_data<22>, dac_data<21>, dac_data<20>, dac_data<19>, dac_data<18>, dac_data<17>, dac_data<16>, dac_data<15>, dac_data<14>, dac_data<13>, dac_data<12>, dac_data<11>, dac_data<10>, dac_data<9>, dac_data<8>, dac_data<7>, dac_data<6>, dac_data<5>, dac_data<4>, dac_data<3>, dac_data<2>, dac_data<1>, dac_data<0>, mhz_20_clock_12, mhz_20_clock_11, mhz_20_clock_10, reset_1, load_configuration_data, reset_2, load_configuration_data_1, dac_data_opad_c, reset_3, load_configuration_data_0, write_clock_enable, shift_configuration_data; BUSFORMAT:%s<%d>. PIN dac_data<23>; ENM:'dac_data<23:0>', BUS:0, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:0/23/0/0. PIN dac_data<22>; ENM:'dac_data<23:0>', BUS:1, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:1/23/0/0. PIN dac_data<21>; ENM:'dac_data<23:0>', BUS:2, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:2/23/0/0. PIN dac_data<20>; ENM:'dac_data<23:0>', BUS:3, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:3/23/0/0. PIN dac_data<19>; ENM:'dac_data<23:0>', BUS:4, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:4/23/0/0. PIN dac_data<18>; ENM:'dac_data<23:0>', BUS:5, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:5/23/0/0. PIN dac_data<17>; ENM:'dac_data<23:0>', BUS:6, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:6/23/0/0. PIN dac_data<16>; ENM:'dac_data<23:0>', BUS:7, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:7/23/0/0. PIN dac_data<15>; ENM:'dac_data<23:0>', BUS:8, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:8/23/0/0. PIN dac_data<14>; ENM:'dac_data<23:0>', BUS:9, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:9/23/0/0. PIN dac_data<13>; ENM:'dac_data<23:0>', BUS:10, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:10/23/0/0. PIN dac_data<12>; ENM:'dac_data<23:0>', BUS:11, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:11/23/0/0. PIN dac_data<11>; ENM:'dac_data<23:0>', BUS:12, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:12/23/0/0. PIN dac_data<10>; ENM:'dac_data<23:0>', BUS:13, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:13/23/0/0. PIN dac_data<9>; ENM:'dac_data<23:0>', BUS:14, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:14/23/0/0. PIN dac_data<8>; ENM:'dac_data<23:0>', BUS:15, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:15/23/0/0. PIN dac_data<7>; ENM:'dac_data<23:0>', BUS:16, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:16/23/0/0. PIN dac_data<6>; ENM:'dac_data<23:0>', BUS:17, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:17/23/0/0. PIN dac_data<5>; ENM:'dac_data<23:0>', BUS:18, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:18/23/0/0. PIN dac_data<4>; ENM:'dac_data<23:0>', BUS:19, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:19/23/0/0. PIN dac_data<3>; ENM:'dac_data<23:0>', BUS:20, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:20/23/0/0. PIN dac_data<2>; ENM:'dac_data<23:0>', BUS:21, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:21/23/0/0. PIN dac_data<1>; ENM:'dac_data<23:0>', BUS:22, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:22/23/0/0. PIN dac_data<0>; ENM:'dac_data<23:0>', BUS:23, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:23/23/0/0. PIN mhz_20_clock_12; DIRECTION:INPUT. PIN mhz_20_clock_11; DIRECTION:INPUT. PIN mhz_20_clock_10; DIRECTION:INPUT. PIN reset_1; DIRECTION:INPUT. PIN load_configuration_data; DIRECTION:INPUT. PIN reset_2; DIRECTION:INPUT. PIN load_configuration_data_1; DIRECTION:INPUT. PIN dac_data_opad_c; DIRECTION:OUTPUT. PIN reset_3; DIRECTION:INPUT. PIN load_configuration_data_0; DIRECTION:INPUT. PIN write_clock_enable; DIRECTION:INPUT. PIN shift_configuration_data; DIRECTION:INPUT. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[22]. USE ADLIB:DFF; parallel_in_serial_out[5]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[22]. USE ADLIB:MUX2H; parallel_in_serial_out_0[1]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[1]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[15]. USE ADLIB:MUX2H; parallel_in_serial_out_0[7]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[8]. USE ADLIB:DFF; parallel_in_serial_out[1]. USE ADLIB:DFF; parallel_in_serial_out[0]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[19]. USE ADLIB:MUX2H; parallel_in_serial_out_0[18]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[15]. USE ADLIB:DFF; parallel_in_serial_out[22]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[12]. USE ADLIB:MUX2H; parallel_in_serial_out_0[12]. USE ADLIB:DFF; parallel_in_serial_out[8]. USE ADLIB:DFF; parallel_in_serial_out[10]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[14]. USE ADLIB:DFF; parallel_in_serial_out[13]. USE ADLIB:DFF; parallel_in_serial_out[3]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[1]. USE ADLIB:DFF; parallel_in_serial_out[6]. USE ADLIB:DFF; parallel_in_serial_out[18]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[19]. USE ADLIB:MUX2H; parallel_in_serial_out_0[8]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[10]. USE ADLIB:DFF; parallel_in_serial_out[16]. USE ADLIB:OA21FTF; un1_load_in_1. USE ADLIB:NOR2FT; parallel_in_serial_out_1[5]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[18]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[11]. USE ADLIB:DFF; parallel_in_serial_out[14]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[3]. USE ADLIB:MUX2H; parallel_in_serial_out_0[16]. USE ADLIB:DFF; parallel_in_serial_out[19]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[23]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[8]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[6]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[13]. USE ADLIB:MUX2H; parallel_in_serial_out_0[17]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[0]. USE ADLIB:MUX2H; parallel_in_serial_out_0[6]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[16]. USE ADLIB:DFF; parallel_in_serial_out[2]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[9]. USE ADLIB:DFF; parallel_in_serial_out[15]. USE ADLIB:DFF; parallel_in_serial_out[11]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[4]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[4]. USE ADLIB:AND2; piso_parallel_in_serial_out_4[0]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[14]. USE ADLIB:MUX2H; parallel_in_serial_out_0[20]. USE ADLIB:GND; GND_i. USE ADLIB:MUX2H; parallel_in_serial_out_0[21]. USE ADLIB:MUX2H; parallel_in_serial_out_0[15]. USE ADLIB:MUX2H; parallel_in_serial_out_0[3]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[13]. USE ADLIB:MUX2H; parallel_in_serial_out_0[23]. USE ADLIB:MUX2H; parallel_in_serial_out_0[0]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[18]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[7]. USE ADLIB:DFF; parallel_in_serial_out[12]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[20]. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2FT; parallel_in_serial_out_1[12]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[3]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[21]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[6]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[7]. USE ADLIB:MUX2H; parallel_in_serial_out_0[14]. USE ADLIB:DFF; parallel_in_serial_out[20]. USE ADLIB:DFF; parallel_in_serial_out[17]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[23]. USE ADLIB:DFF; parallel_in_serial_out[23]. USE ADLIB:DFF; parallel_in_serial_out[7]. USE ADLIB:MUX2H; parallel_in_serial_out_0[4]. USE ADLIB:MUX2H; parallel_in_serial_out_0[19]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[21]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[20]. USE ADLIB:MUX2H; parallel_in_serial_out_0[10]. USE ADLIB:MUX2H; parallel_in_serial_out_0[9]. USE ADLIB:MUX2H; parallel_in_serial_out_0[11]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[5]. USE ADLIB:DFF; parallel_in_serial_out[9]. USE ADLIB:DFF; parallel_in_serial_out[4]. USE ADLIB:MUX2H; parallel_in_serial_out_0[2]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[16]. USE ADLIB:MUX2H; parallel_in_serial_out_0[22]. USE ADLIB:MUX2H; parallel_in_serial_out_0[13]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[17]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[17]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[9]. USE ADLIB:MUX2H; parallel_in_serial_out_0[5]. USE ADLIB:OA21FTF; un1_load_in_1_0. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[2]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[11]. USE ADLIB:MUX2H; piso_parallel_in_serial_out_4[10]. USE ADLIB:NOR2FT; parallel_in_serial_out_1[2]. USE ADLIB:DFF; parallel_in_serial_out[21]. NET dac_data[0]; dac_data<0>, piso_parallel_in_serial_out_4[0]:B. NET dac_data[1]; dac_data<1>, piso_parallel_in_serial_out_4[1]:B. NET dac_data[2]; dac_data<2>, piso_parallel_in_serial_out_4[2]:B. NET dac_data[3]; dac_data<3>, piso_parallel_in_serial_out_4[3]:B. NET dac_data[4]; dac_data<4>, piso_parallel_in_serial_out_4[4]:B. NET dac_data[5]; dac_data<5>, piso_parallel_in_serial_out_4[5]:B. NET dac_data[6]; dac_data<6>, piso_parallel_in_serial_out_4[6]:B. NET dac_data[7]; dac_data<7>, piso_parallel_in_serial_out_4[7]:B. NET dac_data[8]; dac_data<8>, piso_parallel_in_serial_out_4[8]:B. NET dac_data[9]; dac_data<9>, piso_parallel_in_serial_out_4[9]:B. NET dac_data[10]; dac_data<10>, piso_parallel_in_serial_out_4[10]:B. NET dac_data[11]; dac_data<11>, piso_parallel_in_serial_out_4[11]:B. NET dac_data[12]; dac_data<12>, piso_parallel_in_serial_out_4[12]:B. NET dac_data[13]; dac_data<13>, piso_parallel_in_serial_out_4[13]:B. NET dac_data[14]; dac_data<14>, piso_parallel_in_serial_out_4[14]:B. NET dac_data[15]; dac_data<15>, piso_parallel_in_serial_out_4[15]:B. NET dac_data[16]; dac_data<16>, piso_parallel_in_serial_out_4[16]:B. NET dac_data[17]; dac_data<17>, piso_parallel_in_serial_out_4[17]:B. NET dac_data[18]; dac_data<18>, piso_parallel_in_serial_out_4[18]:B. NET dac_data[19]; dac_data<19>, piso_parallel_in_serial_out_4[19]:B. NET dac_data[20]; dac_data<20>, piso_parallel_in_serial_out_4[20]:B. NET dac_data[21]; dac_data<21>, piso_parallel_in_serial_out_4[21]:B. NET dac_data[22]; dac_data<22>, piso_parallel_in_serial_out_4[22]:B. NET dac_data[23]; dac_data<23>, piso_parallel_in_serial_out_4[23]:B. NET mhz_20_clock_12; mhz_20_clock_12, parallel_in_serial_out[21]: CLK, parallel_in_serial_out[23]:CLK, parallel_in_serial_out[17]: CLK, parallel_in_serial_out[20]:CLK, parallel_in_serial_out[19]: CLK, parallel_in_serial_out[16]:CLK, parallel_in_serial_out[18]: CLK, parallel_in_serial_out[22]:CLK. NET mhz_20_clock_11; mhz_20_clock_11, parallel_in_serial_out[4]: CLK, parallel_in_serial_out[9]:CLK, parallel_in_serial_out[7]: CLK, parallel_in_serial_out[12]:CLK, parallel_in_serial_out[11]: CLK, parallel_in_serial_out[15]:CLK, parallel_in_serial_out[14]: CLK, parallel_in_serial_out[6]:CLK, parallel_in_serial_out[13]: CLK, parallel_in_serial_out[10]:CLK, parallel_in_serial_out[8]: CLK, parallel_in_serial_out[5]:CLK. NET mhz_20_clock_10; mhz_20_clock_10, parallel_in_serial_out[2]: CLK, parallel_in_serial_out[3]:CLK, parallel_in_serial_out[0]: CLK, parallel_in_serial_out[1]:CLK. NET reset_1; reset_1, parallel_in_serial_out_1[2]:B, parallel_in_serial_out_1[0]:B, parallel_in_serial_out_1[1]:B. NET load_configuration_data; load_configuration_data, piso_parallel_in_serial_out_4[2]:S, piso_parallel_in_serial_out_4[5]:S, piso_parallel_in_serial_out_4[3]:S, piso_parallel_in_serial_out_4[0]:A, piso_parallel_in_serial_out_4[4]:S, piso_parallel_in_serial_out_4[1]:S. NET reset_2; reset_2, parallel_in_serial_out_1[9]:B, parallel_in_serial_out_1[12]:B, parallel_in_serial_out_1[7]:B, parallel_in_serial_out_1[4]:B, parallel_in_serial_out_1[13]:B, parallel_in_serial_out_1[6]:B, parallel_in_serial_out_1[8]:B, parallel_in_serial_out_1[3]:B, parallel_in_serial_out_1[11]:B, parallel_in_serial_out_1[5]:B, parallel_in_serial_out_1[10]:B, parallel_in_serial_out_1[14]:B. NET load_configuration_data_1; load_configuration_data_1, piso_parallel_in_serial_out_4[10]:S, piso_parallel_in_serial_out_4[11]:S, piso_parallel_in_serial_out_4[7]:S, piso_parallel_in_serial_out_4[6]:S, piso_parallel_in_serial_out_4[13]:S, piso_parallel_in_serial_out_4[14]:S, piso_parallel_in_serial_out_4[9]:S, piso_parallel_in_serial_out_4[12]:S, piso_parallel_in_serial_out_4[15]:S, piso_parallel_in_serial_out_4[8]:S. NET dac_data_opad_c; dac_data_opad_c, parallel_in_serial_out[23]: Q, parallel_in_serial_out_0[23]:B. NET reset_3; reset_3, parallel_in_serial_out_1[17]:B, parallel_in_serial_out_1[16]:B, parallel_in_serial_out_1[23]:B, parallel_in_serial_out_1[21]:B, parallel_in_serial_out_1[20]:B, parallel_in_serial_out_1[18]:B, parallel_in_serial_out_1[19]:B, parallel_in_serial_out_1[15]:B, parallel_in_serial_out_1[22]:B. NET load_configuration_data_0; load_configuration_data_0, un1_load_in_1_0:C, piso_parallel_in_serial_out_4[17]:S, piso_parallel_in_serial_out_4[20]:S, piso_parallel_in_serial_out_4[21]:S, piso_parallel_in_serial_out_4[16]:S, piso_parallel_in_serial_out_4[23]:S, piso_parallel_in_serial_out_4[18]:S, un1_load_in_1:C, piso_parallel_in_serial_out_4[19]:S, piso_parallel_in_serial_out_4[22]:S. NET write_clock_enable; write_clock_enable, un1_load_in_1_0:B, un1_load_in_1:B. NET shift_configuration_data; shift_configuration_data, un1_load_in_1_0:A, un1_load_in_1:A. NET un1_load_in_1_0; parallel_in_serial_out_0[18]:S, un1_load_in_1_0:Y, parallel_in_serial_out_0[13]:S, parallel_in_serial_out_0[22]:S, parallel_in_serial_out_0[19]:S, parallel_in_serial_out_0[14]:S, parallel_in_serial_out_0[23]:S, parallel_in_serial_out_0[15]:S, parallel_in_serial_out_0[21]:S, parallel_in_serial_out_0[20]:S, parallel_in_serial_out_0[17]:S, parallel_in_serial_out_0[16]:S, parallel_in_serial_out_0[12]:S. NET parallel_in_serial_out_1_0[23]; parallel_in_serial_out[23]:D, parallel_in_serial_out_1[23]:Y. NET parallel_in_serial_out_0_0[23]; parallel_in_serial_out_1[23]: A, parallel_in_serial_out_0[23]:Y. NET parallel_in_serial_out_4[23]; parallel_in_serial_out_0[23]:A, piso_parallel_in_serial_out_4[23]:Y. NET parallel_in_serial_out[22]; piso_parallel_in_serial_out_4[23]:A, parallel_in_serial_out_0[22]:B, parallel_in_serial_out[22]:Q. NET parallel_in_serial_out_1_0[22]; parallel_in_serial_out[22]:D, parallel_in_serial_out_1[22]:Y. NET parallel_in_serial_out_0[22]; parallel_in_serial_out_1[22]:A, parallel_in_serial_out_0[22]:Y. NET parallel_in_serial_out_4[22]; parallel_in_serial_out_0[22]:A, piso_parallel_in_serial_out_4[22]:Y. NET parallel_in_serial_out[21]; piso_parallel_in_serial_out_4[22]:A, parallel_in_serial_out[21]: Q, parallel_in_serial_out_0[21]:B. NET parallel_in_serial_out_1_0[21]; parallel_in_serial_out[21]:D, parallel_in_serial_out_1[21]:Y. NET parallel_in_serial_out_0_0[21]; parallel_in_serial_out_1[21]: A, parallel_in_serial_out_0[21]:Y. NET parallel_in_serial_out_4[21]; parallel_in_serial_out_0[21]:A, piso_parallel_in_serial_out_4[21]:Y. NET parallel_in_serial_out[20]; piso_parallel_in_serial_out_4[21]:A, parallel_in_serial_out_0[20]:B, parallel_in_serial_out[20]:Q. NET parallel_in_serial_out_1_0[20]; parallel_in_serial_out[20]:D, parallel_in_serial_out_1[20]:Y. NET parallel_in_serial_out_0_0[20]; parallel_in_serial_out_1[20]: A, parallel_in_serial_out_0[20]:Y. NET parallel_in_serial_out_4[20]; parallel_in_serial_out_0[20]:A, piso_parallel_in_serial_out_4[20]:Y. NET parallel_in_serial_out[19]; piso_parallel_in_serial_out_4[20]:A, parallel_in_serial_out_0[19]:B, parallel_in_serial_out[19]:Q. NET parallel_in_serial_out_1_0[19]; parallel_in_serial_out[19]:D, parallel_in_serial_out_1[19]:Y. NET parallel_in_serial_out_0_0[19]; parallel_in_serial_out_1[19]: A, parallel_in_serial_out_0[19]:Y. NET parallel_in_serial_out_4[19]; parallel_in_serial_out_0[19]:A, piso_parallel_in_serial_out_4[19]:Y. NET parallel_in_serial_out[18]; piso_parallel_in_serial_out_4[19]:A, parallel_in_serial_out[18]: Q, parallel_in_serial_out_0[18]:B. NET parallel_in_serial_out_1_0[18]; parallel_in_serial_out[18]:D, parallel_in_serial_out_1[18]:Y. NET parallel_in_serial_out_0_0[18]; parallel_in_serial_out_1[18]: A, parallel_in_serial_out_0[18]:Y. NET parallel_in_serial_out_4[18]; parallel_in_serial_out_0[18]:A, piso_parallel_in_serial_out_4[18]:Y. NET parallel_in_serial_out[17]; piso_parallel_in_serial_out_4[18]:A, parallel_in_serial_out[17]: Q, parallel_in_serial_out_0[17]:B. NET parallel_in_serial_out_1_0[17]; parallel_in_serial_out[17]:D, parallel_in_serial_out_1[17]:Y. NET parallel_in_serial_out_0_0[17]; parallel_in_serial_out_1[17]: A, parallel_in_serial_out_0[17]:Y. NET parallel_in_serial_out_4[17]; parallel_in_serial_out_0[17]:A, piso_parallel_in_serial_out_4[17]:Y. NET parallel_in_serial_out[16]; piso_parallel_in_serial_out_4[17]:A, parallel_in_serial_out_0[16]:B, parallel_in_serial_out[16]:Q. NET parallel_in_serial_out_1_0[16]; parallel_in_serial_out[16]:D, parallel_in_serial_out_1[16]:Y. NET parallel_in_serial_out_0_0[16]; parallel_in_serial_out_1[16]: A, parallel_in_serial_out_0[16]:Y. NET parallel_in_serial_out_4[16]; parallel_in_serial_out_0[16]:A, piso_parallel_in_serial_out_4[16]:Y. NET parallel_in_serial_out[15]; piso_parallel_in_serial_out_4[16]:A, parallel_in_serial_out_0[15]:B, parallel_in_serial_out[15]:Q. NET parallel_in_serial_out_1_0[15]; parallel_in_serial_out[15]:D, parallel_in_serial_out_1[15]:Y. NET parallel_in_serial_out_0_0[15]; parallel_in_serial_out_1[15]: A, parallel_in_serial_out_0[15]:Y. NET parallel_in_serial_out_4[15]; parallel_in_serial_out_0[15]:A, piso_parallel_in_serial_out_4[15]:Y. NET parallel_in_serial_out[14]; piso_parallel_in_serial_out_4[15]:A, parallel_in_serial_out_0[14]:B, parallel_in_serial_out[14]:Q. NET parallel_in_serial_out_1_0[14]; parallel_in_serial_out[14]:D, parallel_in_serial_out_1[14]:Y. NET parallel_in_serial_out_0_0[14]; parallel_in_serial_out_1[14]: A, parallel_in_serial_out_0[14]:Y. NET parallel_in_serial_out_4[14]; parallel_in_serial_out_0[14]:A, piso_parallel_in_serial_out_4[14]:Y. NET parallel_in_serial_out[13]; piso_parallel_in_serial_out_4[14]:A, parallel_in_serial_out_0[13]:B, parallel_in_serial_out[13]:Q. NET parallel_in_serial_out_1_0[13]; parallel_in_serial_out[13]:D, parallel_in_serial_out_1[13]:Y. NET parallel_in_serial_out_0_0[13]; parallel_in_serial_out_1[13]: A, parallel_in_serial_out_0[13]:Y. NET parallel_in_serial_out_4[13]; parallel_in_serial_out_0[13]:A, piso_parallel_in_serial_out_4[13]:Y. NET parallel_in_serial_out[12]; piso_parallel_in_serial_out_4[13]:A, parallel_in_serial_out[12]: Q, parallel_in_serial_out_0[12]:B. NET parallel_in_serial_out_1_0[12]; parallel_in_serial_out[12]:D, parallel_in_serial_out_1[12]:Y. NET parallel_in_serial_out_0_0[12]; parallel_in_serial_out_1[12]: A, parallel_in_serial_out_0[12]:Y. NET parallel_in_serial_out_4[12]; parallel_in_serial_out_0[12]:A, piso_parallel_in_serial_out_4[12]:Y. NET parallel_in_serial_out[11]; piso_parallel_in_serial_out_4[12]:A, parallel_in_serial_out_0[11]:B, parallel_in_serial_out[11]:Q. NET parallel_in_serial_out_1_0[11]; parallel_in_serial_out[11]:D, parallel_in_serial_out_1[11]:Y. NET parallel_in_serial_out_0_0[11]; parallel_in_serial_out_1[11]: A, parallel_in_serial_out_0[11]:Y. NET parallel_in_serial_out_4[11]; parallel_in_serial_out_0[11]:A, piso_parallel_in_serial_out_4[11]:Y. NET un1_load_in_1_0_0; parallel_in_serial_out_0[1]:S, parallel_in_serial_out_0[5]:S, parallel_in_serial_out_0[2]:S, parallel_in_serial_out_0[11]:S, parallel_in_serial_out_0[9]:S, parallel_in_serial_out_0[10]:S, parallel_in_serial_out_0[4]:S, parallel_in_serial_out_0[0]:S, parallel_in_serial_out_0[3]:S, parallel_in_serial_out_0[6]:S, un1_load_in_1:Y, parallel_in_serial_out_0[8]:S, parallel_in_serial_out_0[7]:S. NET parallel_in_serial_out[10]; piso_parallel_in_serial_out_4[11]:A, parallel_in_serial_out_0[10]:B, parallel_in_serial_out[10]:Q. NET parallel_in_serial_out_1_0[10]; parallel_in_serial_out[10]:D, parallel_in_serial_out_1[10]:Y. NET parallel_in_serial_out_0_0[10]; parallel_in_serial_out_1[10]: A, parallel_in_serial_out_0[10]:Y. NET parallel_in_serial_out_4[10]; parallel_in_serial_out_0[10]:A, piso_parallel_in_serial_out_4[10]:Y. NET parallel_in_serial_out[9]; piso_parallel_in_serial_out_4[10]: A, parallel_in_serial_out_0[9]:B, parallel_in_serial_out[9]:Q. NET parallel_in_serial_out_1_0[9]; parallel_in_serial_out[9]:D, parallel_in_serial_out_1[9]:Y. NET parallel_in_serial_out_0_0[9]; parallel_in_serial_out_1[9]:A, parallel_in_serial_out_0[9]:Y. NET parallel_in_serial_out_4[9]; parallel_in_serial_out_0[9]:A, piso_parallel_in_serial_out_4[9]:Y. NET parallel_in_serial_out[8]; piso_parallel_in_serial_out_4[9]: A, parallel_in_serial_out_0[8]:B, parallel_in_serial_out[8]:Q. NET parallel_in_serial_out_1_0[8]; parallel_in_serial_out[8]:D, parallel_in_serial_out_1[8]:Y. NET parallel_in_serial_out_0_0[8]; parallel_in_serial_out_1[8]:A, parallel_in_serial_out_0[8]:Y. NET parallel_in_serial_out_4[8]; parallel_in_serial_out_0[8]:A, piso_parallel_in_serial_out_4[8]:Y. NET parallel_in_serial_out[7]; piso_parallel_in_serial_out_4[8]: A, parallel_in_serial_out[7]:Q, parallel_in_serial_out_0[7]:B. NET parallel_in_serial_out_1_0[7]; parallel_in_serial_out[7]:D, parallel_in_serial_out_1[7]:Y. NET parallel_in_serial_out_0_0[7]; parallel_in_serial_out_1[7]:A, parallel_in_serial_out_0[7]:Y. NET parallel_in_serial_out_4[7]; parallel_in_serial_out_0[7]:A, piso_parallel_in_serial_out_4[7]:Y. NET parallel_in_serial_out[6]; piso_parallel_in_serial_out_4[7]: A, parallel_in_serial_out_0[6]:B, parallel_in_serial_out[6]:Q. NET parallel_in_serial_out_1_0[6]; parallel_in_serial_out[6]:D, parallel_in_serial_out_1[6]:Y. NET parallel_in_serial_out_0_0[6]; parallel_in_serial_out_1[6]:A, parallel_in_serial_out_0[6]:Y. NET parallel_in_serial_out_4[6]; parallel_in_serial_out_0[6]:A, piso_parallel_in_serial_out_4[6]:Y. NET parallel_in_serial_out[5]; piso_parallel_in_serial_out_4[6]: A, parallel_in_serial_out_0[5]:B, parallel_in_serial_out[5]:Q. NET parallel_in_serial_out_1_0[5]; parallel_in_serial_out[5]:D, parallel_in_serial_out_1[5]:Y. NET parallel_in_serial_out_0_0[5]; parallel_in_serial_out_1[5]:A, parallel_in_serial_out_0[5]:Y. NET parallel_in_serial_out_4[5]; parallel_in_serial_out_0[5]:A, piso_parallel_in_serial_out_4[5]:Y. NET parallel_in_serial_out[4]; piso_parallel_in_serial_out_4[5]: A, parallel_in_serial_out[4]:Q, parallel_in_serial_out_0[4]:B. NET parallel_in_serial_out_1_0[4]; parallel_in_serial_out[4]:D, parallel_in_serial_out_1[4]:Y. NET parallel_in_serial_out_0_0[4]; parallel_in_serial_out_1[4]:A, parallel_in_serial_out_0[4]:Y. NET parallel_in_serial_out_4[4]; parallel_in_serial_out_0[4]:A, piso_parallel_in_serial_out_4[4]:Y. NET parallel_in_serial_out[3]; piso_parallel_in_serial_out_4[4]: A, parallel_in_serial_out_0[3]:B, parallel_in_serial_out[3]:Q. NET parallel_in_serial_out_1_0[3]; parallel_in_serial_out[3]:D, parallel_in_serial_out_1[3]:Y. NET parallel_in_serial_out_0_0[3]; parallel_in_serial_out_1[3]:A, parallel_in_serial_out_0[3]:Y. NET parallel_in_serial_out_4[3]; parallel_in_serial_out_0[3]:A, piso_parallel_in_serial_out_4[3]:Y. NET parallel_in_serial_out[2]; piso_parallel_in_serial_out_4[3]: A, parallel_in_serial_out_0[2]:B, parallel_in_serial_out[2]:Q. NET parallel_in_serial_out_1_0[2]; parallel_in_serial_out[2]:D, parallel_in_serial_out_1[2]:Y. NET parallel_in_serial_out_0_0[2]; parallel_in_serial_out_1[2]:A, parallel_in_serial_out_0[2]:Y. NET parallel_in_serial_out_4[2]; parallel_in_serial_out_0[2]:A, piso_parallel_in_serial_out_4[2]:Y. NET parallel_in_serial_out[1]; piso_parallel_in_serial_out_4[2]: A, parallel_in_serial_out_0[1]:B, parallel_in_serial_out[1]:Q. NET parallel_in_serial_out_1_0[1]; parallel_in_serial_out[1]:D, parallel_in_serial_out_1[1]:Y. NET parallel_in_serial_out_0_0[1]; parallel_in_serial_out_1[1]:A, parallel_in_serial_out_0[1]:Y. NET parallel_in_serial_out_4[1]; parallel_in_serial_out_0[1]:A, piso_parallel_in_serial_out_4[1]:Y. NET parallel_in_serial_out[0]; piso_parallel_in_serial_out_4[1]: A, parallel_in_serial_out_0[0]:B, parallel_in_serial_out[0]:Q. NET parallel_in_serial_out_1_0[0]; parallel_in_serial_out[0]:D, parallel_in_serial_out_1[0]:Y. NET parallel_in_serial_out_0_0[0]; parallel_in_serial_out_1[0]:A, parallel_in_serial_out_0[0]:Y. NET parallel_in_serial_out_4[0]; parallel_in_serial_out_0[0]:A, piso_parallel_in_serial_out_4[0]:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF mxfe_clock_generator_1; mhz_20_clock_13, shift_configuration_data, dac_clock_opad_c, reset_0, write_clock_enable, dac_clock_enable, read_clock_enable. PIN mhz_20_clock_13; DIRECTION:INPUT. PIN shift_configuration_data; DIRECTION:INPUT. PIN dac_clock_opad_c; DIRECTION:OUTPUT. PIN reset_0; DIRECTION:INPUT. PIN write_clock_enable; DIRECTION:OUTPUT. PIN dac_clock_enable; DIRECTION:INPUT. PIN read_clock_enable; DIRECTION:OUTPUT. USE ADLIB:NOR2FT; toggle_q_1. USE ADLIB:XOR2FT; toggle_q_0. USE ADLIB:XOR2; gated_clock_q_0. USE ADLIB:NOR2FT; gated_clock_q_1. USE ADLIB:DFF; toggle_q. USE ADLIB:PWR; PWR_i. USE ADLIB:NOR2; read_clock_enable_out. USE ADLIB:NOR2FT; gated_clock_ff_un1_gate_clock_in. USE ADLIB:DFF; gated_clock_q. USE ADLIB:OR2FT; write_clock_enable_out. USE ADLIB:GND; GND_i. NET mhz_20_clock_13; mhz_20_clock_13, gated_clock_q:CLK, toggle_q:CLK. NET shift_configuration_data; shift_configuration_data, gated_clock_ff_un1_gate_clock_in:A. NET dac_clock_opad_c; dac_clock_opad_c, gated_clock_q:Q, gated_clock_q_0:B. NET reset_0; reset_0, gated_clock_q_1:B, toggle_q_1:B. NET write_clock_enable; write_clock_enable, write_clock_enable_out:Y. NET dac_clock_enable; dac_clock_enable, write_clock_enable_out:B, gated_clock_ff_un1_gate_clock_in:B, read_clock_enable_out:B, toggle_q_0:A. NET read_clock_enable; read_clock_enable, read_clock_enable_out: Y. NET toggle_q; read_clock_enable_out:A, write_clock_enable_out:A, toggle_q_0:B, toggle_q:Q. NET gated_clock_q_1_0; gated_clock_q:D, gated_clock_q_1:Y. NET gated_clock_q_0; gated_clock_q_1:A, gated_clock_q_0:Y. NET un1_gate_clock_in; gated_clock_q_0:A, gated_clock_ff_un1_gate_clock_in:Y. NET toggle_q_1_0; toggle_q:D, toggle_q_1:Y. NET toggle_q_0_0; toggle_q_1:A, toggle_q_0:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF dac_serializer_fsm; mhz_20_clock_13, mhz_20_clock_12, dac_cs_n_opad_c, shift_configuration_data, dac_transfer_busy, load_configuration_data, write_clock_enable, read_clock_enable, reset, dac_start, reset_1, mhz_20_clock_1, load_configuration_data_0, mhz_20_clock_0, load_configuration_data_1. PIN mhz_20_clock_13; DIRECTION:INPUT. PIN mhz_20_clock_12; DIRECTION:INPUT. PIN dac_cs_n_opad_c; DIRECTION:OUTPUT. PIN shift_configuration_data; DIRECTION:OUTPUT. PIN dac_transfer_busy; DIRECTION:OUTPUT. PIN load_configuration_data; DIRECTION:OUTPUT. PIN write_clock_enable; DIRECTION:INPUT. PIN read_clock_enable; DIRECTION:INPUT. PIN reset; DIRECTION:INPUT. PIN dac_start; DIRECTION:INPUT. PIN reset_1; DIRECTION:INPUT. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN load_configuration_data_0; DIRECTION:OUTPUT. PIN mhz_20_clock_0; DIRECTION:INPUT. PIN load_configuration_data_1; DIRECTION:OUTPUT. USE ADLIB:DFF; next_state_i[4]. USE ADLIB:DFF; int_load_configuration_data_out. USE ADLIB:AO21TTF; next_state_srsts_0[0]. USE ADLIB:NOR3FFT; next_state_nss_i_i[0]. USE ADLIB:DFF; int_done_out. USE ADLIB:OA21FTF; next_state_srsts_i_a3[2]. USE ADLIB:XOR2; un1_counter_I_17. USE ADLIB:NOR3; next_state_srsts_i[2]. USE ADLIB:AND2; next_state_CurrentState_counter_6[3]. USE ADLIB:DFF; counter[2]. USE ADLIB:AND2; next_state_CurrentState_counter_6[4]. USE ADLIB:OAI21; un1_next_state_8_i. USE ADLIB:DFF; next_state[1]. USE ADLIB:DFF; next_state[0]. USE ADLIB:NOR2FT; next_state_srsts_i_a2[2]. USE ADLIB:NOR2FT; int_shift_configuration_data_out_1. USE ADLIB:NOR3; next_state_srsts_i_a3_0[3]. USE ADLIB:AND2; next_state_CurrentState_counter_6[2]. USE ADLIB:NOR2FT; next_state_srsts_0_a3_0_0_0[0]. USE ADLIB:AND2; un1_counter_I_25. USE ADLIB:MUX2H; int_shift_configuration_data_out_0. USE ADLIB:OR2; int_select_dac_n_out_1. USE ADLIB:XOR2; un1_counter_I_20. USE ADLIB:AND2; un1_counter_I_28. USE ADLIB:OA21TTF; next_state_srsts_i_0[1]. USE ADLIB:NOR2FT; int_load_configuration_data_out_1. USE ADLIB:DFF; int_load_configuration_data_out_0_0. USE ADLIB:OR2FT; next_state_nss_i_i_a3[0]. USE ADLIB:MUX2H; int_load_configuration_data_out_0. USE ADLIB:NOR2FT; un1_reset_in_1_i. USE ADLIB:DFF; counter[4]. USE ADLIB:NAND2; un1_next_state_8_i_o2. USE ADLIB:GND; GND_i. USE ADLIB:DFF; next_state[2]. USE ADLIB:NAND3FFT; next_state_srsts_i_o2[3]. USE ADLIB:XOR2; un1_counter_I_22. USE ADLIB:DFF; counter[1]. USE ADLIB:AND2; next_state_CurrentState_counter_6[1]. USE ADLIB:DFF; counter[3]. USE ADLIB:OR2; next_state_nss_i_i_a3_0[0]. USE ADLIB:XOR2; un1_counter_I_19. USE ADLIB:AND3FFT; next_state_srsts_i[3]. USE ADLIB:DFF; int_shift_configuration_data_out. USE ADLIB:INV; int_select_dac_n_out_0_i. USE ADLIB:AND2; un1_counter_I_1. USE ADLIB:PWR; PWR_i. USE ADLIB:NAND2FT; next_state_srsts_i_o2_1[3]. USE ADLIB:DFF; int_select_dac_n_out. USE ADLIB:NOR2FT; int_done_out_1. USE ADLIB:MUX2H; int_select_dac_n_out_0. USE ADLIB:OR2FT; un1_next_state_2_i_a2. USE ADLIB:OR3FFT; next_state_srsts_0_a3[0]. USE ADLIB:XOR2; un1_counter_I_21. USE ADLIB:AND2; un1_counter_I_26. USE ADLIB:AND2; un1_counter_I_27. USE ADLIB:AND2; next_state_CurrentState_counter_6[0]. USE ADLIB:OA21; counter_0_sqmuxa_1_i. USE ADLIB:AOI21TTF; next_state_srsts_i[1]. USE ADLIB:DFF; next_state[3]. USE ADLIB:NAND2; next_state_srsts_i_o2_0[3]. USE ADLIB:AOI21FTF; int_done_out_0. USE ADLIB:OAI21TTF; next_state_srsts_i_0[3]. USE ADLIB:DFF; int_load_configuration_data_out_1_0. USE ADLIB:DFF; counter[0]. NET mhz_20_clock_13; mhz_20_clock_13, counter[0]:CLK, next_state[3]:CLK, counter[3]:CLK, counter[1]:CLK, next_state[2]:CLK, counter[4]:CLK, next_state[0]:CLK, next_state[1]:CLK, counter[2]:CLK, next_state_i[4]:CLK. NET mhz_20_clock_12; mhz_20_clock_12, int_select_dac_n_out:CLK, int_shift_configuration_data_out:CLK, int_done_out:CLK, int_load_configuration_data_out:CLK. NET dac_cs_n_opad_c; dac_cs_n_opad_c, int_select_dac_n_out_0:A, int_select_dac_n_out:Q. NET shift_configuration_data; shift_configuration_data, int_shift_configuration_data_out:Q, int_shift_configuration_data_out_0:A. NET dac_transfer_busy; dac_transfer_busy, int_done_out_0:A, int_done_out:Q. NET load_configuration_data; load_configuration_data, int_load_configuration_data_out_0:B, int_load_configuration_data_out:Q. NET write_clock_enable; write_clock_enable, next_state_srsts_0_a3[0]:B, un1_next_state_8_i_o2:B, next_state_nss_i_i_a3[0]:B. NET read_clock_enable; read_clock_enable, counter_0_sqmuxa_1_i:C, next_state_srsts_i_o2[3]:C. NET reset; reset, next_state_srsts_i_0[1]:C, int_select_dac_n_out_1:B, next_state_srsts_i[2]:C. NET dac_start; dac_start, next_state_nss_i_i_a3_0[0]:B, next_state_srsts_i_0[1]:B. NET reset_1; reset_1, next_state_srsts_i_0[3]:C, next_state_srsts_0_a3[0]:C, int_done_out_1:B, un1_reset_in_1_i: B, int_load_configuration_data_out_1:B, next_state_srsts_0_a3_0_0_0[0]:B, int_shift_configuration_data_out_1:B, next_state_nss_i_i[0]:C. NET mhz_20_clock_1; mhz_20_clock_1, int_load_configuration_data_out_0_0:CLK. NET load_configuration_data_0; load_configuration_data_0, int_load_configuration_data_out_0_0:Q. NET mhz_20_clock_0; mhz_20_clock_0, int_load_configuration_data_out_1_0:CLK. NET load_configuration_data_1; load_configuration_data_1, int_load_configuration_data_out_1_0:Q. NET int_load_configuration_data_out_1_0; int_load_configuration_data_out:D, int_load_configuration_data_out_1_0:D, int_load_configuration_data_out_0_0:D, int_load_configuration_data_out_1:Y. NET DWACT_ADD_CI_0_g_array_2[0]; un1_counter_I_22:B, un1_counter_I_27:Y. NET DWACT_ADD_CI_0_g_array_1[0]; un1_counter_I_25:A, un1_counter_I_27:A, un1_counter_I_26:Y, un1_counter_I_20:B. NET DWACT_ADD_CI_0_pog_array_1[0]; un1_counter_I_27:B, un1_counter_I_28:Y. NET DWACT_ADD_CI_0_g_array_12[0]; un1_counter_I_21:B, un1_counter_I_25:Y. NET counter[2]; un1_counter_I_20:A, next_state_srsts_i_o2_0[3]:B, un1_counter_I_28:A, un1_counter_I_25:B, counter[2]:Q. NET DWACT_ADD_CI_0_TMP[0]; un1_counter_I_26:A, un1_counter_I_19: B, un1_counter_I_1:Y. NET counter[1]; un1_counter_I_19:A, next_state_srsts_i_o2_0[3]:A, un1_counter_I_26:B, counter[1]:Q. NET next_state_nss_i_i_0[0]; next_state_i[4]:D, next_state_nss_i_i[0]:Y. NET next_state_nss_i_i_a3[0]; next_state_nss_i_i[0]:A, int_done_out_0:B, next_state_nss_i_i_a3[0]:Y. NET next_state_nss_i_i_a3_0[0]; next_state_nss_i_i[0]:B, next_state_nss_i_i_a3_0[0]:Y. NET next_state_i[4]; un1_reset_in_1_i:A, int_done_out_0:C, next_state_srsts_i[1]:B, un1_next_state_2_i_a2:A, next_state_nss_i_i_a3_0[0]:A, int_shift_configuration_data_out_0:B, next_state_i[4]:Q. NET next_state_srsts_i[3]; next_state[3]:D, next_state_srsts_i[3]:Y. NET N_77_i; next_state_srsts_i[3]:A, next_state_srsts_i_a3_0[3]: Y. NET next_state_srsts_i_0_i[3]; next_state_srsts_i[3]:B, next_state_srsts_i_0[3]:Y. NET un1_next_state_8_i_o2; next_state_srsts_i[1]:A, un1_next_state_8_i:C, next_state_srsts_i[3]:C, un1_next_state_8_i_o2:Y. NET next_state[3]; next_state_srsts_i_a3[2]:A, next_state_srsts_i_0[3]:A, next_state[3]:Q, counter_0_sqmuxa_1_i:B, un1_next_state_2_i_a2:B, int_select_dac_n_out_0_i:A. NET next_state[1]; next_state_srsts_i_0[1]:A, next_state_srsts_i_0[3]:B, un1_next_state_8_i_o2:A, int_load_configuration_data_out_0:A, un1_next_state_8_i:B, next_state_srsts_i_a3_0[3]:B, next_state[1]:Q. NET next_state_srsts_i_o2[3]; next_state_srsts_i_a3_0[3]:A, next_state_srsts_i_o2[3]:Y, next_state_srsts_i_a3[2]:B, next_state_srsts_i_a2[2]:B. NET counter[4]; next_state_srsts_i_a2[2]:A, un1_counter_I_22:A, counter[4]:Q, next_state_srsts_i_a3_0[3]:C. NET next_state_srsts_i[2]; next_state[2]:D, next_state_srsts_i[2]:Y. NET next_state_srsts_i_a3[2]; next_state_srsts_i[2]:A, next_state_srsts_i_a3[2]:Y. NET next_state_srsts_i_a2[2]; next_state_srsts_0[0]:A, next_state_srsts_i_a2[2]:Y, next_state_srsts_i[2]:B. NET next_state[2]; next_state_srsts_0_a3_0_0_0[0]:A, counter_0_sqmuxa_1_i:A, next_state[2]:Q, next_state_srsts_i_a3[2]:C. NET next_state_srsts_i_0[1]; next_state[1]:D, next_state_srsts_i[1]:Y. NET next_state_srsts_i_0_i[1]; next_state_srsts_i[1]:C, next_state_srsts_i_0[1]:Y. NET counter_0_sqmuxa_1_i; un1_counter_I_17:B, counter_0_sqmuxa_1_i:Y, un1_counter_I_1:B. NET next_state_nss[4]; next_state[0]:D, next_state_srsts_0[0]:Y. NET next_state_srsts_0_a3_0_0[0]; next_state_srsts_0[0]:B, next_state_srsts_0_a3_0_0_0[0]:Y. NET next_state_srsts_0_a3[0]; next_state_srsts_0[0]:C, next_state_srsts_0_a3[0]:Y. NET next_state_srsts_i_o2_0_i[3]; next_state_srsts_i_o2[3]:A, next_state_srsts_i_o2_0[3]:Y. NET next_state_srsts_i_o2_1_i[3]; next_state_srsts_i_o2[3]:B, next_state_srsts_i_o2_1[3]:Y. NET counter[3]; next_state_srsts_i_o2_1[3]:A, un1_counter_I_21:A, un1_counter_I_28:B, counter[3]:Q. NET counter[0]; un1_counter_I_17:A, counter[0]:Q, next_state_srsts_i_o2_1[3]:B, un1_counter_I_1:A. NET next_state[0]; next_state_nss_i_i_a3[0]:A, next_state_srsts_0_a3[0]:A, next_state[0]:Q. NET int_load_configuration_data_out_0_0; int_load_configuration_data_out_1:A, int_load_configuration_data_out_0:Y. NET un1_next_state_8_i; int_load_configuration_data_out_0:S, un1_next_state_8_i:Y. NET un1_next_state_2_i_a2; un1_next_state_8_i:A, un1_next_state_2_i_a2:Y, int_select_dac_n_out_0:S, int_shift_configuration_data_out_0:S. NET int_done_out_1_0; int_done_out:D, int_done_out_1:Y. NET int_done_out_0; int_done_out_1:A, int_done_out_0:Y. NET int_shift_configuration_data_out_1_0; int_shift_configuration_data_out:D, int_shift_configuration_data_out_1:Y. NET int_shift_configuration_data_out_0_0; int_shift_configuration_data_out_1:A, int_shift_configuration_data_out_0:Y. NET int_select_dac_n_out_1; int_select_dac_n_out:D, int_select_dac_n_out_1:Y. NET int_select_dac_n_out_0; int_select_dac_n_out_1:A, int_select_dac_n_out_0:Y. NET next_state_i_0[3]; int_select_dac_n_out_0:B, int_select_dac_n_out_0_i:Y. NET counter_6[4]; counter[4]:D, next_state_CurrentState_counter_6[4]:Y. NET un1_reset_in_1_i; next_state_CurrentState_counter_6[3]:A, next_state_CurrentState_counter_6[0]:A, next_state_CurrentState_counter_6[1]:A, un1_reset_in_1_i:Y, next_state_CurrentState_counter_6[2]:A, next_state_CurrentState_counter_6[4]:A. NET I_22_0; next_state_CurrentState_counter_6[4]:B, un1_counter_I_22:Y. NET counter_6[3]; counter[3]:D, next_state_CurrentState_counter_6[3]:Y. NET I_21_0; next_state_CurrentState_counter_6[3]:B, un1_counter_I_21:Y. NET counter_6[2]; counter[2]:D, next_state_CurrentState_counter_6[2]:Y. NET I_20_0; next_state_CurrentState_counter_6[2]:B, un1_counter_I_20:Y. NET counter_6[1]; counter[1]:D, next_state_CurrentState_counter_6[1]:Y. NET I_19_0; next_state_CurrentState_counter_6[1]:B, un1_counter_I_19:Y. NET counter_6[0]; counter[0]:D, next_state_CurrentState_counter_6[0]:Y. NET DWACT_ADD_CI_0_partial_sum[0]; next_state_CurrentState_counter_6[0]:B, un1_counter_I_17:Y. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF dac_serializer; dac_data<23>, dac_data<22>, dac_data<21>, dac_data<20>, dac_data<19>, dac_data<18>, dac_data<17>, dac_data<16>, dac_data<15>, dac_data<14>, dac_data<13>, dac_data<12>, dac_data<11>, dac_data<10>, dac_data<9>, dac_data<8>, dac_data<7>, dac_data<6>, dac_data<5>, dac_data<4>, dac_data<3>, dac_data<2>, dac_data<1>, dac_data<0>, dac_clock_enable, reset_0, dac_clock_opad_c, mhz_20_clock_0, mhz_20_clock_1, dac_start, reset, dac_transfer_busy, dac_cs_n_opad_c, mhz_20_clock_13, reset_3, dac_data_opad_c, reset_2, reset_1, mhz_20_clock_10, mhz_20_clock_11, mhz_20_clock_12; BUSFORMAT:%s<%d>. PIN dac_data<23>; ENM:'dac_data<23:0>', BUS:0, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:0/23/0/0. PIN dac_data<22>; ENM:'dac_data<23:0>', BUS:1, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:1/23/0/0. PIN dac_data<21>; ENM:'dac_data<23:0>', BUS:2, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:2/23/0/0. PIN dac_data<20>; ENM:'dac_data<23:0>', BUS:3, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:3/23/0/0. PIN dac_data<19>; ENM:'dac_data<23:0>', BUS:4, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:4/23/0/0. PIN dac_data<18>; ENM:'dac_data<23:0>', BUS:5, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:5/23/0/0. PIN dac_data<17>; ENM:'dac_data<23:0>', BUS:6, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:6/23/0/0. PIN dac_data<16>; ENM:'dac_data<23:0>', BUS:7, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:7/23/0/0. PIN dac_data<15>; ENM:'dac_data<23:0>', BUS:8, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:8/23/0/0. PIN dac_data<14>; ENM:'dac_data<23:0>', BUS:9, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:9/23/0/0. PIN dac_data<13>; ENM:'dac_data<23:0>', BUS:10, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:10/23/0/0. PIN dac_data<12>; ENM:'dac_data<23:0>', BUS:11, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:11/23/0/0. PIN dac_data<11>; ENM:'dac_data<23:0>', BUS:12, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:12/23/0/0. PIN dac_data<10>; ENM:'dac_data<23:0>', BUS:13, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:13/23/0/0. PIN dac_data<9>; ENM:'dac_data<23:0>', BUS:14, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:14/23/0/0. PIN dac_data<8>; ENM:'dac_data<23:0>', BUS:15, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:15/23/0/0. PIN dac_data<7>; ENM:'dac_data<23:0>', BUS:16, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:16/23/0/0. PIN dac_data<6>; ENM:'dac_data<23:0>', BUS:17, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:17/23/0/0. PIN dac_data<5>; ENM:'dac_data<23:0>', BUS:18, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:18/23/0/0. PIN dac_data<4>; ENM:'dac_data<23:0>', BUS:19, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:19/23/0/0. PIN dac_data<3>; ENM:'dac_data<23:0>', BUS:20, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:20/23/0/0. PIN dac_data<2>; ENM:'dac_data<23:0>', BUS:21, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:21/23/0/0. PIN dac_data<1>; ENM:'dac_data<23:0>', BUS:22, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:22/23/0/0. PIN dac_data<0>; ENM:'dac_data<23:0>', BUS:23, DIRECTION:INPUT, ORIGNAME:dac_data, BUSINFO:23/23/0/0. PIN dac_clock_enable; DIRECTION:INPUT. PIN reset_0; DIRECTION:INPUT. PIN dac_clock_opad_c; DIRECTION:OUTPUT. PIN mhz_20_clock_0; DIRECTION:INPUT. PIN mhz_20_clock_1; DIRECTION:INPUT. PIN dac_start; DIRECTION:INPUT. PIN reset; DIRECTION:INPUT. PIN dac_transfer_busy; DIRECTION:OUTPUT. PIN dac_cs_n_opad_c; DIRECTION:OUTPUT. PIN mhz_20_clock_13; DIRECTION:INPUT. PIN reset_3; DIRECTION:INPUT. PIN dac_data_opad_c; DIRECTION:OUTPUT. PIN reset_2; DIRECTION:INPUT. PIN reset_1; DIRECTION:INPUT. PIN mhz_20_clock_10; DIRECTION:INPUT. PIN mhz_20_clock_11; DIRECTION:INPUT. PIN mhz_20_clock_12; DIRECTION:INPUT. USE piso_shift_register_1; U2. USE mxfe_clock_generator_1; U4. USE ADLIB:PWR; PWR_i. USE dac_serializer_fsm; U3. USE ADLIB:GND; GND_i. NET dac_data[0]; dac_data<0>, U2:dac_data<0>. NET dac_data[1]; dac_data<1>, U2:dac_data<1>. NET dac_data[2]; dac_data<2>, U2:dac_data<2>. NET dac_data[3]; dac_data<3>, U2:dac_data<3>. NET dac_data[4]; dac_data<4>, U2:dac_data<4>. NET dac_data[5]; dac_data<5>, U2:dac_data<5>. NET dac_data[6]; dac_data<6>, U2:dac_data<6>. NET dac_data[7]; dac_data<7>, U2:dac_data<7>. NET dac_data[8]; dac_data<8>, U2:dac_data<8>. NET dac_data[9]; dac_data<9>, U2:dac_data<9>. NET dac_data[10]; dac_data<10>, U2:dac_data<10>. NET dac_data[11]; dac_data<11>, U2:dac_data<11>. NET dac_data[12]; dac_data<12>, U2:dac_data<12>. NET dac_data[13]; dac_data<13>, U2:dac_data<13>. NET dac_data[14]; dac_data<14>, U2:dac_data<14>. NET dac_data[15]; dac_data<15>, U2:dac_data<15>. NET dac_data[16]; dac_data<16>, U2:dac_data<16>. NET dac_data[17]; dac_data<17>, U2:dac_data<17>. NET dac_data[18]; dac_data<18>, U2:dac_data<18>. NET dac_data[19]; dac_data<19>, U2:dac_data<19>. NET dac_data[20]; dac_data<20>, U2:dac_data<20>. NET dac_data[21]; dac_data<21>, U2:dac_data<21>. NET dac_data[22]; dac_data<22>, U2:dac_data<22>. NET dac_data[23]; dac_data<23>, U2:dac_data<23>. NET dac_clock_enable; dac_clock_enable, U4:dac_clock_enable. NET reset_0; reset_0, U4:reset_0. NET dac_clock_opad_c; dac_clock_opad_c, U4:dac_clock_opad_c. NET mhz_20_clock_0; mhz_20_clock_0, U3:mhz_20_clock_0. NET mhz_20_clock_1; mhz_20_clock_1, U3:mhz_20_clock_1. NET dac_start; dac_start, U3:dac_start. NET reset; reset, U3:reset. NET dac_transfer_busy; dac_transfer_busy, U3:dac_transfer_busy. NET dac_cs_n_opad_c; dac_cs_n_opad_c, U3:dac_cs_n_opad_c. NET mhz_20_clock_13; mhz_20_clock_13, U3:mhz_20_clock_13, U4: mhz_20_clock_13. NET reset_3; reset_3, U2:reset_3. NET dac_data_opad_c; dac_data_opad_c, U2:dac_data_opad_c. NET reset_2; reset_2, U2:reset_2. NET reset_1; reset_1, U3:reset_1, U2:reset_1. NET mhz_20_clock_10; mhz_20_clock_10, U2:mhz_20_clock_10. NET mhz_20_clock_11; mhz_20_clock_11, U2:mhz_20_clock_11. NET mhz_20_clock_12; mhz_20_clock_12, U3:mhz_20_clock_12, U2: mhz_20_clock_12. NET load_configuration_data; U2:load_configuration_data, U3: load_configuration_data. NET load_configuration_data_1; U2:load_configuration_data_1, U3: load_configuration_data_1. NET load_configuration_data_0; U2:load_configuration_data_0, U3: load_configuration_data_0. NET write_clock_enable; U2:write_clock_enable, U3: write_clock_enable, U4:write_clock_enable. NET shift_configuration_data; U2:shift_configuration_data, U3: shift_configuration_data, U4:shift_configuration_data. NET read_clock_enable; U4:read_clock_enable, U3: read_clock_enable. NET VCC; PWR_i:Y. NET GND; GND_i:Y. END. DEF biosa; address_ipads<15>, address_ipads<14>, address_ipads<13>, address_ipads<12>, address_ipads<11>, address_ipads<10>, address_ipads<9>, address_ipads<8>, address_ipads<7>, address_ipads<6>, address_ipads<5>, address_ipads<4>, address_ipads<3>, address_ipads<2>, address_ipads<1>, address_ipads<0>, data_iopads<15>, data_iopads<14>, data_iopads<13>, data_iopads<12>, data_iopads<11>, data_iopads<10>, data_iopads<9>, data_iopads<8>, data_iopads<7>, data_iopads<6>, data_iopads<5>, data_iopads<4>, data_iopads<3>, data_iopads<2>, data_iopads<1>, data_iopads<0>, async_reset_n_ipad, cs_n_ipad, fpga_clock_n_ipad, fpga_clock_p_ipad, rd_n_ipad, spi_dio_ipad, wr_0_n_ipad, wr_1_n_ipad, dac_clock_opad, dac_cs_n_opad, dac_data_opad, interrupt_n_opad, spi_clock_opad, spi_cs_n_opad, spi_sdo_opad, stall_n_opad; BUSFORMAT:%s<%d>, NEW_TRANSLATE. PIN address_ipads<15>; ENM:'address_ipads<15:0>', BUS:0, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:0/15/0/1. PIN address_ipads<14>; ENM:'address_ipads<15:0>', BUS:1, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:1/15/0/1. PIN address_ipads<13>; ENM:'address_ipads<15:0>', BUS:2, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:2/15/0/1. PIN address_ipads<12>; ENM:'address_ipads<15:0>', BUS:3, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:3/15/0/1. PIN address_ipads<11>; ENM:'address_ipads<15:0>', BUS:4, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:4/15/0/1. PIN address_ipads<10>; ENM:'address_ipads<15:0>', BUS:5, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:5/15/0/1. PIN address_ipads<9>; ENM:'address_ipads<15:0>', BUS:6, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:6/15/0/1. PIN address_ipads<8>; ENM:'address_ipads<15:0>', BUS:7, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:7/15/0/1. PIN address_ipads<7>; ENM:'address_ipads<15:0>', BUS:8, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:8/15/0/1. PIN address_ipads<6>; ENM:'address_ipads<15:0>', BUS:9, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:9/15/0/1. PIN address_ipads<5>; ENM:'address_ipads<15:0>', BUS:10, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:10/15/0/1. PIN address_ipads<4>; ENM:'address_ipads<15:0>', BUS:11, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:11/15/0/1. PIN address_ipads<3>; ENM:'address_ipads<15:0>', BUS:12, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:12/15/0/1. PIN address_ipads<2>; ENM:'address_ipads<15:0>', BUS:13, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:13/15/0/1. PIN address_ipads<1>; ENM:'address_ipads<15:0>', BUS:14, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:14/15/0/1. PIN address_ipads<0>; ENM:'address_ipads<15:0>', BUS:15, DIRECTION: INPUT, ORIGNAME:address_ipads, BUSINFO:15/15/0/1. PIN data_iopads<15>; ENM:'data_iopads<15:0>', BUS:0, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:0/15/0/1. PIN data_iopads<14>; ENM:'data_iopads<15:0>', BUS:1, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:1/15/0/1. PIN data_iopads<13>; ENM:'data_iopads<15:0>', BUS:2, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:2/15/0/1. PIN data_iopads<12>; ENM:'data_iopads<15:0>', BUS:3, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:3/15/0/1. PIN data_iopads<11>; ENM:'data_iopads<15:0>', BUS:4, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:4/15/0/1. PIN data_iopads<10>; ENM:'data_iopads<15:0>', BUS:5, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:5/15/0/1. PIN data_iopads<9>; ENM:'data_iopads<15:0>', BUS:6, DIRECTION:INOUT, ORIGNAME:data_iopads, BUSINFO:6/15/0/1. PIN data_iopads<8>; ENM:'data_iopads<15:0>', BUS:7, DIRECTION:INOUT, ORIGNAME:data_iopads, BUSINFO:7/15/0/1. PIN data_iopads<7>; ENM:'data_iopads<15:0>', BUS:8, DIRECTION:INOUT, ORIGNAME:data_iopads, BUSINFO:8/15/0/1. PIN data_iopads<6>; ENM:'data_iopads<15:0>', BUS:9, DIRECTION:INOUT, ORIGNAME:data_iopads, BUSINFO:9/15/0/1. PIN data_iopads<5>; ENM:'data_iopads<15:0>', BUS:10, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:10/15/0/1. PIN data_iopads<4>; ENM:'data_iopads<15:0>', BUS:11, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:11/15/0/1. PIN data_iopads<3>; ENM:'data_iopads<15:0>', BUS:12, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:12/15/0/1. PIN data_iopads<2>; ENM:'data_iopads<15:0>', BUS:13, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:13/15/0/1. PIN data_iopads<1>; ENM:'data_iopads<15:0>', BUS:14, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:14/15/0/1. PIN data_iopads<0>; ENM:'data_iopads<15:0>', BUS:15, DIRECTION: INOUT, ORIGNAME:data_iopads, BUSINFO:15/15/0/1. PIN async_reset_n_ipad; DIRECTION:INPUT. PIN cs_n_ipad; DIRECTION:INPUT. PIN fpga_clock_n_ipad; DIRECTION:INPUT. PIN fpga_clock_p_ipad; DIRECTION:INPUT. PIN rd_n_ipad; DIRECTION:INPUT. PIN spi_dio_ipad; DIRECTION:INPUT. PIN wr_0_n_ipad; DIRECTION:INPUT. PIN wr_1_n_ipad; DIRECTION:INPUT. PIN dac_clock_opad; DIRECTION:OUTPUT. PIN dac_cs_n_opad; DIRECTION:OUTPUT. PIN dac_data_opad; DIRECTION:OUTPUT. PIN interrupt_n_opad; DIRECTION:OUTPUT. PIN spi_clock_opad; DIRECTION:OUTPUT. PIN spi_cs_n_opad; DIRECTION:OUTPUT. PIN spi_sdo_opad; DIRECTION:OUTPUT. PIN stall_n_opad; DIRECTION:OUTPUT. USE ADLIB:OB33PH; dac_clock_opad_pad. USE ADLIB:OB33PH; spi_cs_n_opad_pad. USE ADLIB:IOB33PH; data_iopads_pad[11]. USE ADLIB:OB33PH; spi_clock_opad_pad. USE ADLIB:IOB33PH; data_iopads_pad[15]. USE ADLIB:IB33; address_ipads_pad[10]. USE clock_prescalar; U5. USE ADLIB:IB33; wr_0_n_ipad_pad. USE ADLIB:IOB33PH; data_iopads_pad[9]. USE ADLIB:IB33; address_ipads_pad[6]. USE ADLIB:OB33PH; stall_n_opad_pad. USE ADLIB:IOB33PH; data_iopads_pad[5]. USE ADLIB:IB33; spi_dio_ipad_pad. USE ADLIB:IOB33PH; data_iopads_pad[8]. USE registers; U1. USE ADLIB:IB33; address_ipads_pad[2]. USE ADLIB:IB33; wr_1_n_ipad_pad. USE ADLIB:IOB33PH; data_iopads_pad[6]. USE ADLIB:IOB33PH; data_iopads_pad[1]. USE ADLIB:IB33; address_ipads_pad[14]. USE ADLIB:IB33; async_reset_n_ipad_pad. USE ADLIB:IB33; address_ipads_pad[9]. USE ADLIB:IB33; address_ipads_pad[12]. USE mxfe_configurator; U4. USE ADLIB:IOB33PH; data_iopads_pad[7]. USE ADLIB:IOB33PH; data_iopads_pad[2]. USE ADLIB:NOR2; data_iopads_pad_i[15]. USE ADLIB:IOB33PH; data_iopads_pad[0]. USE ADLIB:IB33; address_ipads_pad[8]. USE ADLIB:IB33; rd_n_ipad_pad. USE ADLIB:IOB33PH; data_iopads_pad[10]. USE ADLIB:IB33; address_ipads_pad[15]. USE ADLIB:IB33; address_ipads_pad[3]. USE ADLIB:GND; GND_i. USE ADLIB:IB33; address_ipads_pad[5]. USE ADLIB:IOB33PH; data_iopads_pad[4]. USE ADLIB:IOB33PH; data_iopads_pad[3]. USE ADLIB:IB33; address_ipads_pad[0]. USE ADLIB:OB33PH; dac_cs_n_opad_pad. USE reset_synchronizer; U2. USE ADLIB:NOR2; data_iopads_pad_i_0[15]. USE ADLIB:IOB33PH; data_iopads_pad[13]. USE ADLIB:PWR; PWR_i. USE ADLIB:OB33PH; spi_sdo_opad_pad. USE ADLIB:OB33PH; dac_data_opad_pad. USE ADLIB:IB33; cs_n_ipad_pad. USE ADLIB:OB33PH; interrupt_n_opad_pad. USE ADLIB:IB33; address_ipads_pad[7]. USE ADLIB:IOB33PH; data_iopads_pad[12]. USE ADLIB:IB33; address_ipads_pad[4]. USE ADLIB:IB33; address_ipads_pad[1]. USE ADLIB:GLPE; U6. USE ADLIB:IOB33PH; data_iopads_pad[14]. USE ADLIB:IB33; address_ipads_pad[11]. USE dac_serializer; U7. USE ADLIB:IB33; address_ipads_pad[13]. NET async_reset_n_ipad; async_reset_n_ipad, async_reset_n_ipad_pad:PAD. NET cs_n_ipad; cs_n_ipad, cs_n_ipad_pad:PAD. NET fpga_clock_n_ipad; fpga_clock_n_ipad, U6:PECLIN. NET fpga_clock_p_ipad; fpga_clock_p_ipad, U6:PECLREF. NET rd_n_ipad; rd_n_ipad, rd_n_ipad_pad:PAD. NET spi_dio_ipad; spi_dio_ipad, spi_dio_ipad_pad:PAD. NET wr_0_n_ipad; wr_0_n_ipad, wr_0_n_ipad_pad:PAD. NET wr_1_n_ipad; wr_1_n_ipad, wr_1_n_ipad_pad:PAD. NET address_ipads[0]; address_ipads<0>, address_ipads_pad[0]:PAD. NET address_ipads[1]; address_ipads<1>, address_ipads_pad[1]:PAD. NET address_ipads[2]; address_ipads<2>, address_ipads_pad[2]:PAD. NET address_ipads[3]; address_ipads<3>, address_ipads_pad[3]:PAD. NET address_ipads[4]; address_ipads<4>, address_ipads_pad[4]:PAD. NET address_ipads[5]; address_ipads<5>, address_ipads_pad[5]:PAD. NET address_ipads[6]; address_ipads<6>, address_ipads_pad[6]:PAD. NET address_ipads[7]; address_ipads<7>, address_ipads_pad[7]:PAD. NET address_ipads[8]; address_ipads<8>, address_ipads_pad[8]:PAD. NET address_ipads[9]; address_ipads<9>, address_ipads_pad[9]:PAD. NET address_ipads[10]; address_ipads<10>, address_ipads_pad[10]: PAD. NET address_ipads[11]; address_ipads<11>, address_ipads_pad[11]: PAD. NET address_ipads[12]; address_ipads<12>, address_ipads_pad[12]: PAD. NET address_ipads[13]; address_ipads<13>, address_ipads_pad[13]: PAD. NET address_ipads[14]; address_ipads<14>, address_ipads_pad[14]: PAD. NET address_ipads[15]; address_ipads<15>, address_ipads_pad[15]: PAD. NET dac_clock_opad; dac_clock_opad, dac_clock_opad_pad:PAD. NET dac_cs_n_opad; dac_cs_n_opad, dac_cs_n_opad_pad:PAD. NET dac_data_opad; dac_data_opad, dac_data_opad_pad:PAD. NET interrupt_n_opad; interrupt_n_opad, interrupt_n_opad_pad:PAD. NET spi_clock_opad; spi_clock_opad, spi_clock_opad_pad:PAD. NET spi_cs_n_opad; spi_cs_n_opad, spi_cs_n_opad_pad:PAD. NET spi_sdo_opad; spi_sdo_opad, spi_sdo_opad_pad:PAD. NET stall_n_opad; stall_n_opad, stall_n_opad_pad:PAD. NET data_iopads[0]; data_iopads<0>, data_iopads_pad[0]:PAD. NET data_iopads[1]; data_iopads<1>, data_iopads_pad[1]:PAD. NET data_iopads[2]; data_iopads<2>, data_iopads_pad[2]:PAD. NET data_iopads[3]; data_iopads<3>, data_iopads_pad[3]:PAD. NET data_iopads[4]; data_iopads<4>, data_iopads_pad[4]:PAD. NET data_iopads[5]; data_iopads<5>, data_iopads_pad[5]:PAD. NET data_iopads[6]; data_iopads<6>, data_iopads_pad[6]:PAD. NET data_iopads[7]; data_iopads<7>, data_iopads_pad[7]:PAD. NET data_iopads[8]; data_iopads<8>, data_iopads_pad[8]:PAD. NET data_iopads[9]; data_iopads<9>, data_iopads_pad[9]:PAD. NET data_iopads[10]; data_iopads<10>, data_iopads_pad[10]:PAD. NET data_iopads[11]; data_iopads<11>, data_iopads_pad[11]:PAD. NET data_iopads[12]; data_iopads<12>, data_iopads_pad[12]:PAD. NET data_iopads[13]; data_iopads<13>, data_iopads_pad[13]:PAD. NET data_iopads[14]; data_iopads<14>, data_iopads_pad[14]:PAD. NET data_iopads[15]; data_iopads<15>, data_iopads_pad[15]:PAD. NET N_350_0; data_iopads_pad[5]:EN, data_iopads_pad_i_0[15]:Y, data_iopads_pad[3]:EN, data_iopads_pad[4]:EN, data_iopads_pad[0]:EN, data_iopads_pad[2]:EN, data_iopads_pad[7]:EN, data_iopads_pad[1]:EN, data_iopads_pad[6]:EN, data_iopads_pad[8]:EN. NET rd_n_ipad_c; data_iopads_pad_i[15]:A, data_iopads_pad_i_0[15]:A, rd_n_ipad_pad:Y, U1:rd_n_ipad_c. NET U1_synced_cs_n; data_iopads_pad_i[15]:B, data_iopads_pad_i_0[15]:B, U1:synced_cs_n; ENM:'U1.synced_cs_n', ORIGNAME:'U1.synced_cs_n'. NET data_iopads_pad_i[15]; data_iopads_pad[11]:EN, data_iopads_pad[14]:EN, data_iopads_pad[12]:EN, data_iopads_pad[13]:EN, data_iopads_pad[10]:EN, data_iopads_pad_i[15]:Y, data_iopads_pad[9]:EN, data_iopads_pad[15]:EN. NET data_iopads_in[15]; U1:data_iopads_in<15>, data_iopads_pad[15]:Y. NET data_out[15]; data_iopads_pad[15]:A, U1:data_out_15. NET data_iopads_in[14]; U1:data_iopads_in<14>, data_iopads_pad[14]:Y. NET data_out_0_iv_i[14]; data_iopads_pad[14]:A, U1: data_out_0_iv_i<14>. NET data_iopads_in[13]; U1:data_iopads_in<13>, data_iopads_pad[13]:Y. NET data_out[13]; data_iopads_pad[13]:A, U1:data_out_13. NET data_iopads_in[12]; U1:data_iopads_in<12>, data_iopads_pad[12]:Y. NET data_out[12]; data_iopads_pad[12]:A, U1:data_out_12. NET data_iopads_in[11]; U1:data_iopads_in<11>, data_iopads_pad[11]:Y. NET data_out[11]; data_iopads_pad[11]:A, U1:data_out_11. NET data_iopads_in[10]; U1:data_iopads_in<10>, data_iopads_pad[10]:Y. NET data_out[10]; data_iopads_pad[10]:A, U1:data_out_10. NET data_iopads_in[9]; U1:data_iopads_in<9>, data_iopads_pad[9]: Y. NET data_out[9]; data_iopads_pad[9]:A, U1:data_out_9. NET data_iopads_in[8]; U1:data_iopads_in<8>, data_iopads_pad[8]: Y. NET data_out[8]; data_iopads_pad[8]:A, U1:data_out_8. NET data_iopads_in[7]; U1:data_iopads_in<7>, data_iopads_pad[7]: Y. NET data_out[7]; data_iopads_pad[7]:A, U1:data_out_7. NET data_iopads_in[6]; U1:data_iopads_in<6>, data_iopads_pad[6]: Y. NET data_out[6]; data_iopads_pad[6]:A, U1:data_out_6. NET data_iopads_in[5]; U1:data_iopads_in<5>, data_iopads_pad[5]: Y. NET data_out[5]; data_iopads_pad[5]:A, U1:data_out_5. NET data_iopads_in[4]; U1:data_iopads_in<4>, data_iopads_pad[4]: Y. NET data_out[4]; data_iopads_pad[4]:A, U1:data_out_4. NET data_iopads_in[3]; U1:data_iopads_in<3>, data_iopads_pad[3]: Y. NET data_out[3]; data_iopads_pad[3]:A, U1:data_out_3. NET data_iopads_in[2]; U1:data_iopads_in<2>, data_iopads_pad[2]: Y. NET data_out[2]; data_iopads_pad[2]:A, U1:data_out_2. NET data_iopads_in[1]; U1:data_iopads_in<1>, data_iopads_pad[1]: Y. NET data_out[1]; data_iopads_pad[1]:A, U1:data_out_1. NET data_iopads_in[0]; U1:data_iopads_in<0>, data_iopads_pad[0]: Y. NET data_out[0]; data_iopads_pad[0]:A, U1:data_out_0. NET VCC; stall_n_opad_pad:A, interrupt_n_opad_pad:A, PWR_i:Y. NET spi_sdo_opad_c; spi_sdo_opad_pad:A, U4:spi_sdo_opad_c. NET spi_cs_n_opad_c; spi_cs_n_opad_pad:A, U4:spi_cs_n_opad_c. NET spi_clock_opad_c; spi_clock_opad_pad:A, U4:spi_clock_opad_c. NET dac_data_opad_c; dac_data_opad_pad:A, U7:dac_data_opad_c. NET dac_cs_n_opad_c; dac_cs_n_opad_pad:A, U7:dac_cs_n_opad_c. NET dac_clock_opad_c; dac_clock_opad_pad:A, U7:dac_clock_opad_c. NET address_ipads_c[15]; U1:address_ipads_c_14, address_ipads_pad[15]:Y. NET address_ipads_c_i_0_i[14]; U1:address_ipads_c_i_0_i_14, address_ipads_pad[14]:Y. NET address_ipads_c[13]; U1:address_ipads_c_12, address_ipads_pad[13]:Y. NET address_ipads_c_i_0_i[12]; U1:address_ipads_c_i_0_i_12, address_ipads_pad[12]:Y. NET address_ipads_c[11]; U1:address_ipads_c_10, address_ipads_pad[11]:Y. NET address_ipads_c_i_0_i[10]; U1:address_ipads_c_i_0_i_10, address_ipads_pad[10]:Y. NET address_ipads_c[9]; U1:address_ipads_c_8, address_ipads_pad[9]:Y. NET address_ipads_c_i_0_i[8]; U1:address_ipads_c_i_0_i_8, address_ipads_pad[8]:Y. NET address_ipads_c[7]; U1:address_ipads_c_6, address_ipads_pad[7]:Y. NET address_ipads_c[6]; U1:address_ipads_c_5, address_ipads_pad[6]:Y. NET address_ipads_c[5]; U1:address_ipads_c_4, address_ipads_pad[5]:Y. NET address_ipads_c[4]; U1:address_ipads_c_3, address_ipads_pad[4]:Y. NET address_ipads_c[3]; U1:address_ipads_c_2, address_ipads_pad[3]:Y. NET address_ipads_c[2]; U1:address_ipads_c_1, address_ipads_pad[2]:Y. NET address_ipads_c[1]; U1:address_ipads_c_0, address_ipads_pad[1]:Y. NET address_ipads_c_i_0_i[0]; U1:address_ipads_c_i_0_i_0, address_ipads_pad[0]:Y. NET wr_1_n_ipad_c; U1:wr_1_n_ipad_c, wr_1_n_ipad_pad:Y. NET wr_0_n_ipad_c; U1:wr_0_n_ipad_c, wr_0_n_ipad_pad:Y. NET spi_dio_ipad_c; U4:spi_dio_ipad_c, spi_dio_ipad_pad:Y. NET cs_n_ipad_c; U1:cs_n_ipad_c, cs_n_ipad_pad:Y. NET async_reset_n_ipad_c; U2:async_reset_n_ipad_c, async_reset_n_ipad_pad:Y. NET mhz_80_clock; U6:GL, U5:mhz_80_clock. NET mxfe_register_data[0]; U1:mxfe_register_data<0>, U4: mxfe_register_data<0>. NET mxfe_register_data[1]; U1:mxfe_register_data<1>, U4: mxfe_register_data<1>. NET mxfe_register_data[2]; U1:mxfe_register_data<2>, U4: mxfe_register_data<2>. NET mxfe_register_data[3]; U1:mxfe_register_data<3>, U4: mxfe_register_data<3>. NET mxfe_register_data[4]; U1:mxfe_register_data<4>, U4: mxfe_register_data<4>. NET mxfe_register_data[5]; U1:mxfe_register_data<5>, U4: mxfe_register_data<5>. NET mxfe_register_data[6]; U1:mxfe_register_data<6>, U4: mxfe_register_data<6>. NET mxfe_register_data[7]; U1:mxfe_register_data<7>, U4: mxfe_register_data<7>. NET mxfe_configuration_data[0]; U1:mxfe_configuration_data<0>, U4:mxfe_configuration_data<0>. NET mxfe_configuration_data[1]; U1:mxfe_configuration_data<1>, U4:mxfe_configuration_data<1>. NET mxfe_configuration_data[2]; U1:mxfe_configuration_data<2>, U4:mxfe_configuration_data<2>. NET mxfe_configuration_data[3]; U1:mxfe_configuration_data<3>, U4:mxfe_configuration_data<3>. NET mxfe_configuration_data[4]; U1:mxfe_configuration_data<4>, U4:mxfe_configuration_data<4>. NET mxfe_configuration_data[5]; U1:mxfe_configuration_data<5>, U4:mxfe_configuration_data<5>. NET mxfe_configuration_data[6]; U1:mxfe_configuration_data<6>, U4:mxfe_configuration_data<6>. NET mxfe_configuration_data[7]; U1:mxfe_configuration_data<7>, U4:mxfe_configuration_data<7>. NET mxfe_configuration_data[8]; U1:mxfe_configuration_data<8>, U4:mxfe_configuration_data<8>. NET mxfe_configuration_data[9]; U1:mxfe_configuration_data<9>, U4:mxfe_configuration_data<9>. NET mxfe_configuration_data[10]; U1:mxfe_configuration_data<10>, U4:mxfe_configuration_data<10>. NET mxfe_configuration_data[11]; U1:mxfe_configuration_data<11>, U4:mxfe_configuration_data<11>. NET mxfe_configuration_data[12]; U1:mxfe_configuration_data<12>, U4:mxfe_configuration_data<12>. NET mxfe_configuration_data[13]; U1:mxfe_configuration_data<13>, U4:mxfe_configuration_data<13>. NET mxfe_configuration_data[14]; U1:mxfe_configuration_data<14>, U4:mxfe_configuration_data<14>. NET mxfe_configuration_data[15]; U1:mxfe_configuration_data<15>, U4:mxfe_configuration_data<15>. NET mxfe_configuration_data[16]; U1:mxfe_configuration_data<16>, U4:mxfe_configuration_data<16>. NET mxfe_configuration_data[17]; U1:mxfe_configuration_data<17>, U4:mxfe_configuration_data<17>. NET mxfe_configuration_data[18]; U1:mxfe_configuration_data<18>, U4:mxfe_configuration_data<18>. NET mxfe_configuration_data[19]; U1:mxfe_configuration_data<19>, U4:mxfe_configuration_data<19>. NET mxfe_configuration_data[20]; U1:mxfe_configuration_data<20>, U4:mxfe_configuration_data<20>. NET mxfe_configuration_data[21]; U1:mxfe_configuration_data<21>, U4:mxfe_configuration_data<21>. NET dac_data[0]; U1:dac_data<0>, U7:dac_data<0>. NET dac_data[1]; U1:dac_data<1>, U7:dac_data<1>. NET dac_data[2]; U1:dac_data<2>, U7:dac_data<2>. NET dac_data[3]; U1:dac_data<3>, U7:dac_data<3>. NET dac_data[4]; U1:dac_data<4>, U7:dac_data<4>. NET dac_data[5]; U1:dac_data<5>, U7:dac_data<5>. NET dac_data[6]; U1:dac_data<6>, U7:dac_data<6>. NET dac_data[7]; U1:dac_data<7>, U7:dac_data<7>. NET dac_data[8]; U1:dac_data<8>, U7:dac_data<8>. NET dac_data[9]; U1:dac_data<9>, U7:dac_data<9>. NET dac_data[10]; U1:dac_data<10>, U7:dac_data<10>. NET dac_data[11]; U1:dac_data<11>, U7:dac_data<11>. NET dac_data[12]; U1:dac_data<12>, U7:dac_data<12>. NET dac_data[13]; U1:dac_data<13>, U7:dac_data<13>. NET dac_data[14]; U1:dac_data<14>, U7:dac_data<14>. NET dac_data[15]; U1:dac_data<15>, U7:dac_data<15>. NET dac_data[16]; U1:dac_data<16>, U7:dac_data<16>. NET dac_data[17]; U1:dac_data<17>, U7:dac_data<17>. NET dac_data[18]; U1:dac_data<18>, U7:dac_data<18>. NET dac_data[19]; U1:dac_data<19>, U7:dac_data<19>. NET dac_data[20]; U1:dac_data<20>, U7:dac_data<20>. NET dac_data[21]; U1:dac_data<21>, U7:dac_data<21>. NET dac_data[22]; U1:dac_data<22>, U7:dac_data<22>. NET dac_data[23]; U1:dac_data<23>, U7:dac_data<23>. NET dac_transfer_busy; U1:dac_transfer_busy, U7: dac_transfer_busy. NET configuration_busy; U1:configuration_busy, U4: configuration_busy. NET mhz_20_clock_6; U5:mhz_20_clock_6, U2:mhz_20_clock_6, U4: mhz_20_clock_6, U1:mhz_20_clock_6. NET mhz_20_clock_5; U5:mhz_20_clock_5, U1:mhz_20_clock_5. NET mhz_20_clock_4; U5:mhz_20_clock_4, U1:mhz_20_clock_4. NET mhz_20_clock_3; U5:mhz_20_clock_3, U1:mhz_20_clock_3. NET mhz_20_clock_2; U5:mhz_20_clock_2, U1:mhz_20_clock_2. NET mhz_20_clock_1; U5:mhz_20_clock_1, U7:mhz_20_clock_1, U4: mhz_20_clock_1, U1:mhz_20_clock_1. NET mxfe_start; U1:mxfe_start, U4:mxfe_start. NET reset_0; U1:reset_0, U7:reset_0, U2:reset_0, U4:reset_0. NET dac_clock_enable; U1:dac_clock_enable, U7:dac_clock_enable, U4:dac_clock_enable. NET reset_6; U1:reset_6, U2:reset_6, U4:reset_6. NET dac_start; U1:dac_start, U7:dac_start. NET one_n_or_two; U1:one_n_or_two, U4:one_n_or_two. NET write_n_or_read; U1:write_n_or_read, U4:write_n_or_read. NET reset_7; U1:reset_7, U2:reset_7. NET reset_8; U1:reset_8, U2:reset_8. NET reset_9; U1:reset_9, U2:reset_9. NET reset_10; U1:reset_10, U2:reset_10. NET reset; U4:reset, U7:reset, U2:reset. NET reset_1; U4:reset_1, U7:reset_1, U2:reset_1. NET reset_2; U2:reset_2, U7:reset_2. NET reset_3; U4:reset_3, U7:reset_3, U2:reset_3. NET reset_4; U4:reset_4, U2:reset_4. NET reset_5; U4:reset_5, U2:reset_5. NET mhz_20_clock_0; U5:mhz_20_clock_0, U7:mhz_20_clock_0, U2: mhz_20_clock_0. NET mhz_20_clock_9; U5:mhz_20_clock_9, U4:mhz_20_clock_9. NET mhz_20_clock_7; U5:mhz_20_clock_7, U4:mhz_20_clock_7. NET mhz_20_clock_8; U5:mhz_20_clock_8, U4:mhz_20_clock_8. NET mhz_20_clock_10; U5:mhz_20_clock_10, U7:mhz_20_clock_10, U4: mhz_20_clock_10. NET mhz_20_clock_11; U5:mhz_20_clock_11, U7:mhz_20_clock_11. NET mhz_20_clock_12; U5:mhz_20_clock_12, U7:mhz_20_clock_12. NET mhz_20_clock_13; U5:mhz_20_clock_13, U7:mhz_20_clock_13. NET GND; GND_i:Y. END.