gfimporter V6.3.1 - 07/19/05 Design: C:\my_designs\biosa\MotherBoard\analog_io\implement\biosa.dtfStarted: Thu Feb 15 14:30:38 2007 Parameters on the command line: C:\my_designs\biosa\MotherBoard\analog_io\implement\biosa.dtf -constraints C:\my_designs\biosa\MotherBoard\analog_io\implement\biosa.dtf\master.gcf -family apa -format EDIF -part APA075 -package APA075-TQ100 -source ./biosa.adl -topcell biosa -temp 0:25:70 -voltage 2.30:2.50:2.70 -process Worst -jtag Extended -auto_ram_support -ngt_tdpr_support -mem_region_support -reportfanout 20 Info: [no_load]: The following nets have no load: GND U5/VCC U5/GND U1/VCC U1/GND U1/mxfe_busy_ff/VCC U1/mxfe_busy_ff/GND U1/sync2/VCC U1/sync2/GND U1/sync1/VCC U1/sync1/GND U1/fed1/VCC U1/fed1/GND U1/dac_busy_ff/VCC U1/dac_busy_ff/GND U4/VCC U4/GND U4/U2/VCC U4/U2/GND U4/U4/VCC U4/U4/GND U4/U3/VCC U4/U3/GND U4/U1/VCC U4/U1/GND U2/VCC U7/VCC U7/GND U7/U2/VCC U7/U2/GND U7/U4/VCC U7/U4/GND U7/U3/VCC U7/U3/GND Info: [removed_pwr_gnd_cells]: Removed 36 power/ground cells from the design. The list of high fanout nets arranged by fanout: Fanout Type Driver Name ---------------------------------------------------------------------- 168 CLK_NET U5/counter_bits[1] U5/counter_bits[1] 13 SET/RESET_NET async_reset_n_ipad_pad async_reset_n_ipad_c 12 INT_NET U2/sync_reset_out_8 reset_8 12 INT_NET U2/sync_reset_out_9 reset_9 12 INT_NET U7/U2/un1_load_in_1_0 U7/U2/un1_load_in_1_0 12 INT_NET U2/reset_ff U2/reset_ff 12 INT_NET U2/sync_reset_out_5 reset_5 12 INT_NET U2/sync_reset_out_6 reset_6 12 INT_NET U2/sync_reset_out_1 reset_1 12 INT_NET U2/sync_reset_out_2 reset_2 12 INT_NET U4/U2/un1_load_in_1_0 U4/U2/un1_load_in_1_0 12 INT_NET U7/U2/un1_load_in_1 U7/U2/un1_load_in_1_0_0 12 INT_NET U2/sync_reset_out_3 reset_3 12 INT_NET U2/sync_reset_out_7 reset_7 12 INT_NET U2/sync_reset_out_4 reset_4 12 INT_NET U2/sync_reset_out_0 reset_0 12 INT_NET U4/U2/un1_load_in_1 U4/U2/un1_load_in_1 12 INT_NET U1/un3_dac_start_0_a3 dac_start 12 INT_NET U2/sync_reset_out_10 reset_10 10 INT_NET U2/sync_reset_out reset The list of high fanout nets bypassing the buffers and invertors: Fanout Type Driver Name ---------------------------------------------------------------------- 168 CLK_NET U5/counter_bits[1] U5/counter_bits[1] 13 SET/RESET_NET async_reset_n_ipad_pad async_reset_n_ipad_c 12 INT_NET U2/sync_reset_out_8 reset_8 12 INT_NET U2/sync_reset_out_9 reset_9 12 INT_NET U7/U2/un1_load_in_1_0 U7/U2/un1_load_in_1_0 12 INT_NET U2/reset_ff U2/reset_ff 12 INT_NET U2/sync_reset_out_5 reset_5 12 INT_NET U2/sync_reset_out_6 reset_6 12 INT_NET U2/sync_reset_out_1 reset_1 12 INT_NET U2/sync_reset_out_2 reset_2 12 INT_NET U4/U2/un1_load_in_1_0 U4/U2/un1_load_in_1_0 12 INT_NET U7/U2/un1_load_in_1 U7/U2/un1_load_in_1_0_0 12 INT_NET U2/sync_reset_out_3 reset_3 12 INT_NET U2/sync_reset_out_7 reset_7 12 INT_NET U2/sync_reset_out_4 reset_4 12 INT_NET U2/sync_reset_out_0 reset_0 12 INT_NET U4/U2/un1_load_in_1 U4/U2/un1_load_in_1 12 INT_NET U1/un3_dac_start_0_a3 dac_start 12 INT_NET U2/sync_reset_out_10 reset_10 10 INT_NET U2/sync_reset_out reset Info: [too_few_globals]: Too few global nets could be promoted. Total:2. Available global resources:4. The fanout required for promotion was set to 32. The following nets are assigned to global resources: Fanout Name Reason for being global -------------------------------------------------------------- 2 mhz_80_clock output of a global IO cell GLPE 168 U5/counter_bits[1] Promoted to global by using internal global cell Netlist Optimization Summary ============================ Unnecessary block removal: dangling net drivers: 0 buffers: 15 inverters: 6 Constant propagation block removal (by block type): AND : 0 NAND: 0 OR : 0 NOR : 0 XOR : 0 XNOR: 0 MUX : 0 AOI : 0 OA : 0 Total 0 Total blocks removed: 21 Design Difficulty Constants: 5318 - 7.3 59.89 percent Connectivity Fanout <= 3 71.36 percent Connectivity Fanout <= 6 99.13 percent Connectivity Fanout <= 12 100.00 percent Connectivity Fanout <= 28 100.00 percent Connectivity Fanout <= 44 100.00 percent Connectivity Fanout <= 80 Importer Summary =============== Part-Package: APA075-TQ100 Core Slots: 3072 RAM/FIFO Slots: 12 I/O Slots: 66 (Globals: 4) (PLLs: 2) Core Cells: 678 --> Usage: 22.1 percent RAM/FIFO Cells: 0 --> Usage: 0.0 percent IOs: 47 --> Usage: 72.3 percent PLLs: 0 --> Usage: 0.0 percent Constraints processed: IO constraints: 0 Path constraints: 0 Placement constraints: 0 Net constraints: 0 I/O Cells: Core cells: | Instances | Gates | Tiles Input. IOs: 22 ----------|-----------|--------|------- Bidir IOs: 16 Logic | 509 | 1127 | 509 Output IOs: 8 Storage | 169 | 1196 | 169 Global IOs: 1 RAM/FIFO | 0 | 0 | 0 Internal Global: 0 | | | ----------------------- ----------|-----------|--------|------- Total IOs: 47 Total | 678 | 2323 | 678 Nets | Count | Average Fanout | Max. Fanout ---------------|--------|----------------|------------ Global | 2 | 85.0 | 168 External | 63 | 2.3 | 13 Internal | 653 | 2.1 | 12 ---------------|--------|----------------|------------ Total | 718 | 2.3 | 168 gfimporter completed successfully. Design: C:\my_designs\biosa\MotherBoard\analog_io\implement\biosa.dtf Finished: Thu Feb 15 14:30:40 2007 Information messages reported: 1 Total CPU Time: 00:00:01 Total Elapsed Time: 00:00:02 o - o - o - o - o - o