library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock_prescalar is
	 port(
		 clock_in 	: in 	std_logic;
		 mhz_20_out	: out 	std_logic
	 );
end clock_prescalar;

architecture synthesis of clock_prescalar is	 
	signal counter_bits	: std_logic_vector(1 downto 0) := "00";
begin
	
	two_bit_counter : process (clock_in)
	begin
		if rising_edge(clock_in) then 
			counter_bits <= counter_bits + 1;
		end if;
	end process two_bit_counter;
	
	mhz_20_out <= counter_bits(1);
			
end synthesis;