library IEEE;
use IEEE.std_logic_1164.all;

entity jk_ff is
	 port(
		 clock_in 	: in 	std_logic;
		 reset_in 	: in 	std_logic; 
		 enable_in	: in	std_logic;
		 j_in 		: in 	std_logic;
		 k_in 		: in 	std_logic;
		 q_out 		: out 	std_logic
	 );
end jk_ff;

architecture synthesis of jk_ff is	   
	signal q	: std_logic;
	signal qns	: std_logic;
begin		 
	ff : process (clock_in)
	begin
		if rising_edge(clock_in) then 
			if reset_in = '1' then
				q <= '0';
			elsif enable_in = '1' then
				q <= qns;
			end if;
		end if;
	end process ff;
	
    jk_next_state : process (j_in, k_in, q)
    	variable jk : std_logic_vector (1 downto 0);
    begin
    	jk := (j_in & k_in);
	    case jk is
		    when "01"	=> qns <= '0';
		    when "10"	=> qns <= '1';
		    when "11"	=> qns <= not (q);
		    when "00"	=> qns <= q;   
			when others => null;
		end case;
	end process jk_next_state;
	
    q_out <= q;

end synthesis;