library ieee;
use ieee.std_logic_1164.all;

entity piso_shift_register is
	 port(
		 clock_in	: in 	std_logic;
		 reset_in 	: in 	std_logic;	
		 enable_in	: in	std_logic;
		 load_in 	: in 	std_logic;
		 shift_in	: in 	std_logic;
		 data_in 	: in 	std_logic_vector(23 downto 0);		
		 data_out 	: out	std_logic
	 );
end piso_shift_register;

architecture synthesis of piso_shift_register is
	signal parallel_in_serial_out : std_logic_vector(23 downto 0);
begin		 
	
	piso : process( clock_in )	  
	begin
		if rising_edge (clock_in) then	 
			if reset_in = '1' then		
				parallel_in_serial_out <= (others => '0');	
			elsif load_in = '1' then
				parallel_in_serial_out <= data_in;
			elsif shift_in = '1' and enable_in = '1'  then
				parallel_in_serial_out <= parallel_in_serial_out(22 downto 0) & '0';
			end if;
		end if;
	end process piso;		  
	
	data_out <= parallel_in_serial_out(23);

end synthesis;