library ieee;
use ieee.std_logic_1164.all;

entity sipo_shift_register is
	 port(
		 clock_in	: in 	std_logic;
		 reset_in 	: in 	std_logic; 
		 enable_in	: in	std_logic;
		 shift_in	: in 	std_logic;
		 data_in 	: in 	std_logic;		
		 data_out 	: out	std_logic_vector(7 downto 0)
	 );
end sipo_shift_register;

architecture synthesis of sipo_shift_register is
	signal serial_in_parallel_out : std_logic_vector(7 downto 0);
begin		 
	
	sipo : process( clock_in )	  
	begin
		if rising_edge (clock_in) then	 
			if reset_in = '1' then		
				serial_in_parallel_out <= (others => '0');
			elsif shift_in = '1' and enable_in = '1' then
				serial_in_parallel_out <= serial_in_parallel_out(6 downto 0) & data_in;
			end if;
		end if;
	end process sipo;		  	   
	
	data_out <= serial_in_parallel_out;

end synthesis;