@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\biosa.vhd":32:7:32:11|Synthesizing analog_io.biosa.synthesis 
@W: CD280 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\biosa.vhd":134:10:134:13|Unbound component glpe mapped to black box
@W: CD280 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\biosa.vhd":152:10:152:12|Unbound component pwr mapped to black box
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\biosa.vhd":152:10:152:12|Synthesizing analog_io.pwr.syn_black_box 
Post processing for analog_io.pwr.syn_black_box
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\dac_serializer.vhd":28:7:28:20|Synthesizing analog_io.dac_serializer.dac_serializer 
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\mxfe_clock_generator.vhd":4:7:4:26|Synthesizing analog_io.mxfe_clock_generator.synthesis 
Post processing for analog_io.mxfe_clock_generator.synthesis
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\dac_serializer_fsm.vhd":26:7:26:24|Synthesizing analog_io.dac_serializer_fsm.synthesis 
@N: CD234 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\dac_serializer_fsm.vhd":46:21:46:22|Using user defined encoding for type next_state_type
Post processing for analog_io.dac_serializer_fsm.synthesis
@N: CL201 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\dac_serializer_fsm.vhd":144:1:144:2|Trying to extract state machine for register next_state
Extracted state machine for register next_state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\piso_shift_register.vhd":4:7:4:25|Synthesizing analog_io.piso_shift_register.synthesis 
Post processing for analog_io.piso_shift_register.synthesis
Post processing for analog_io.dac_serializer.dac_serializer
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\biosa.vhd":134:10:134:13|Synthesizing analog_io.glpe.syn_black_box 
Post processing for analog_io.glpe.syn_black_box
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\clock_prescalar.vhd":5:7:5:21|Synthesizing analog_io.clock_prescalar.synthesis 
Post processing for analog_io.clock_prescalar.synthesis
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\compile\mxfe_configurator.vhd":28:7:28:23|Synthesizing analog_io.mxfe_configurator.synthesis 
@N: CD630 :"C:\my_designs\biosa\MotherBoard\analog_io\compile\mxfe_serializer_fsm.vhd":26:7:26:25|Synthesizing work.mxfe_serializer_fsm.synthesis 
@N: CD234 :"C:\my_designs\biosa\MotherBoard\analog_io\compile\mxfe_serializer_fsm.vhd":49:21:49:22|Using user defined encoding for type next_state_type
Post processing for work.mxfe_serializer_fsm.synthesis
@N: CL201 :"C:\my_designs\biosa\MotherBoard\analog_io\compile\mxfe_serializer_fsm.vhd":172:1:172:2|Trying to extract state machine for register next_state
Extracted state machine for register next_state
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\sipo_shift_register.vhd":4:7:4:25|Synthesizing analog_io.sipo_shift_register.synthesis 
Post processing for analog_io.sipo_shift_register.synthesis
Post processing for analog_io.mxfe_configurator.synthesis
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\busbidi.vhd":4:7:4:30|Synthesizing analog_io.bus_bidirectional_buffer.synthesis 
Post processing for analog_io.bus_bidirectional_buffer.synthesis
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\reset_sync.vhd":4:7:4:24|Synthesizing analog_io.reset_synchronizer.synthesis 
Post processing for analog_io.reset_synchronizer.synthesis
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\registers.vhd":6:7:6:15|Synthesizing analog_io.registers.synthesis 
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\jk_ff.vhd":4:7:4:11|Synthesizing analog_io.jk_ff.synthesis 
Post processing for analog_io.jk_ff.synthesis
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\falling_edge_detector.vhd":4:7:4:27|Synthesizing analog_io.falling_edge_detector.synthesis 
Post processing for analog_io.falling_edge_detector.synthesis
@N: CD630 :"c:\my_designs\biosa\MotherBoard\analog_io\src\dual_rank_sync.vhd":4:7:4:28|Synthesizing analog_io.dual_rank_synchronizer.synthesis 
Post processing for analog_io.dual_rank_synchronizer.synthesis
Post processing for analog_io.registers.synthesis
@W: CL169 :"c:\my_designs\biosa\MotherBoard\analog_io\src\registers.vhd":128:2:128:3|Pruning Register mxfe_configuration_command_register(7 downto 0)  
Post processing for analog_io.biosa.synthesis