-- -- Written by Synplicity -- Thu Feb 15 14:28:44 2007 -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity mxfe_serializer_fsm is port( mhz_20_clock_9 : in std_logic; mhz_20_clock_8 : in std_logic; spi_cs_n_opad_c : out std_logic; shift_configuration_data : out std_logic; configuration_busy : out std_logic; shift_mxfe_data : out std_logic; reset_3 : in std_logic; load_configuration_data : out std_logic; reset_4 : in std_logic; write_clock_enable : in std_logic; mxfe_start : in std_logic; read_clock_enable_i_0_i : in std_logic; one_n_or_two : in std_logic; reset : in std_logic; write_n_or_read : in std_logic; load_configuration_data_0 : out std_logic; mhz_20_clock_1 : in std_logic; load_configuration_data_1 : out std_logic); end mxfe_serializer_fsm; architecture beh of mxfe_serializer_fsm is signal DWACT_ADD_CI_0_G_ARRAY_2 : std_logic_vector (0 to 0); signal DWACT_ADD_CI_0_G_ARRAY_1 : std_logic_vector (0 to 0); signal DWACT_ADD_CI_0_POG_ARRAY_1 : std_logic_vector (0 to 0); signal DWACT_ADD_CI_0_G_ARRAY_12 : std_logic_vector (0 to 0); signal COUNTER : std_logic_vector (4 downto 0); signal DWACT_ADD_CI_0_TMP : std_logic_vector (0 to 0); signal NEXT_STATE_SRSTS_I_O3_0 : std_logic_vector (3 to 3); signal NEXT_STATE : std_logic_vector (5 downto 0); signal NEXT_STATE_NSS_I_I : std_logic_vector (0 to 0); signal NEXT_STATE_I : std_logic_vector (6 to 6); signal NEXT_STATE_SRSTS_I : std_logic_vector (5 downto 1); signal NEXT_STATE_SRSTS_I_O3 : std_logic_vector (4 to 4); signal NEXT_STATE_NSS : std_logic_vector (6 to 6); signal NEXT_STATE_SRSTS_0_0_I : std_logic_vector (0 to 0); signal NEXT_STATE_SRSTS_0_A3_0 : std_logic_vector (0 to 0); signal NEXT_STATE_SRSTS_0_O3 : std_logic_vector (0 to 0); signal NEXT_STATE_SRSTS_0_A3_0_1_I : std_logic_vector (0 to 0); signal NEXT_STATE_SRSTS_0_O3_0 : std_logic_vector (0 to 0); signal NEXT_STATE_I_0 : std_logic_vector (5 to 5); signal COUNTER_6 : std_logic_vector (4 downto 0); signal DWACT_ADD_CI_0_PARTIAL_SUM : std_logic_vector (0 to 0); signal SPI_CS_N_OPAD_C_INT_63 : std_logic ; signal SHIFT_CONFIGURATION_DATA_INT_64 : std_logic ; signal CONFIGURATION_BUSY_INT_65 : std_logic ; signal SHIFT_MXFE_DATA_INT_66 : std_logic ; signal LOAD_CONFIGURATION_DATA_INT_67 : std_logic ; signal INT_LOAD_CONFIGURATION_DATA_OUT_1 : std_logic ; signal N_77_I_0 : std_logic ; signal N_79_1_I_I : std_logic ; signal N_92 : std_logic ; signal N_75_I_0 : std_logic ; signal N_102_I : std_logic ; signal N_107 : std_logic ; signal N_94 : std_logic ; signal COUNTER_0_SQMUXA : std_logic ; signal N_113 : std_logic ; signal N_114 : std_logic ; signal N_111 : std_logic ; signal N_112 : std_logic ; signal N_90 : std_logic ; signal N_93 : std_logic ; signal N_91_I_0 : std_logic ; signal N_105 : std_logic ; signal N_106 : std_logic ; signal N_104_I : std_logic ; signal N_103_I : std_logic ; signal INT_LOAD_CONFIGURATION_DATA_OUT_0 : std_logic ; signal UN1_NEXT_STATE_12 : std_logic ; signal UN1_NEXT_STATE_2 : std_logic ; signal INT_SHIFT_MXFE_REGISTER_DATA_OUT_1 : std_logic ; signal INT_SHIFT_MXFE_REGISTER_DATA_OUT_0 : std_logic ; signal UN1_NEXT_STATE_10 : std_logic ; signal INT_DONE_OUT_1 : std_logic ; signal N_6 : std_logic ; signal UN1_NEXT_STATE_9 : std_logic ; signal INT_SHIFT_CONFIGURATION_DATA_OUT_1 : std_logic ; signal INT_SHIFT_CONFIGURATION_DATA_OUT_0 : std_logic ; signal INT_CONFIGURE_MXFE_OUT_1 : std_logic ; signal INT_CONFIGURE_MXFE_OUT_0 : std_logic ; signal N_69 : std_logic ; signal I_22 : std_logic ; signal I_21 : std_logic ; signal I_20 : std_logic ; signal I_19 : std_logic ; signal N_20 : std_logic ; signal N_19 : std_logic ; signal N_18 : std_logic ; signal N_17 : std_logic ; signal N_16 : std_logic ; signal N_15 : std_logic ; signal N_14 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component AND2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component OA21 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AND2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AO21 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AND3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR3 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR3FTT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AOI21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OR3 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AO21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NAND3FTT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NAND3 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component MUX2H port( Y : out std_logic; A : in std_logic; B : in std_logic; S : in std_logic ); end component; component OR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component OAI21FTT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component INV port( Y : out std_logic; A : in std_logic ); end component; component XOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_int_load_configuration_data_out_1_0: DFF port map ( Q => load_configuration_data_1, CLK => mhz_20_clock_1, D => INT_LOAD_CONFIGURATION_DATA_OUT_1); II_int_load_configuration_data_out_0_0: DFF port map ( Q => load_configuration_data_0, CLK => mhz_20_clock_1, D => INT_LOAD_CONFIGURATION_DATA_OUT_1); \II_un1_counter.I_27\: AND2 port map ( Y => DWACT_ADD_CI_0_G_ARRAY_2(0), A => DWACT_ADD_CI_0_G_ARRAY_1(0), B => DWACT_ADD_CI_0_POG_ARRAY_1(0)); \II_un1_counter.I_25\: AND2 port map ( Y => DWACT_ADD_CI_0_G_ARRAY_12(0), A => DWACT_ADD_CI_0_G_ARRAY_1(0), B => COUNTER(2)); \II_un1_counter.I_26\: AND2 port map ( Y => DWACT_ADD_CI_0_G_ARRAY_1(0), A => DWACT_ADD_CI_0_TMP(0), B => COUNTER(1)); \II_next_state_srsts_i[3]\: OA21 port map ( Y => N_77_I_0, A => NEXT_STATE_SRSTS_I_O3_0(3), B => NEXT_STATE(3), C => N_79_1_I_I); \II_next_state_srsts_i_o3_0[3]\: AND2FT port map ( Y => NEXT_STATE_SRSTS_I_O3_0(3), A => write_n_or_read, B => N_92); \II_next_state_srsts_i[2]\: NOR3FFT port map ( Y => N_75_I_0, A => N_102_I, B => N_107, C => reset); \II_next_state_srsts_i_a3[2]\: AO21 port map ( Y => N_107, A => N_94, B => one_n_or_two, C => NEXT_STATE(2)); II_counter_0_sqmuxa_0_a3: AND3FFT port map ( Y => COUNTER_0_SQMUXA, A => NEXT_STATE(1), B => NEXT_STATE(0), C => read_clock_enable_i_0_i); \II_next_state_nss_i_i[0]\: NOR3 port map ( Y => NEXT_STATE_NSS_I_I(0), A => N_113, B => N_114, C => reset); \II_next_state_nss_i_i_a3_0[0]\: NOR2 port map ( Y => N_114, A => NEXT_STATE_I(6), B => mxfe_start); \II_next_state_srsts_i[5]\: NOR3 port map ( Y => NEXT_STATE_SRSTS_I(5), A => N_111, B => N_112, C => reset); \II_next_state_srsts_i_a3_0[5]\: NOR3FTT port map ( Y => N_112, A => N_90, B => NEXT_STATE(1), C => COUNTER(3)); \II_next_state_srsts_i_a3[5]\: NOR2 port map ( Y => N_111, A => N_93, B => NEXT_STATE(5)); \II_next_state_srsts_i[4]\: OA21 port map ( Y => NEXT_STATE_SRSTS_I(4), A => NEXT_STATE_SRSTS_I_O3(4), B => NEXT_STATE(4), C => N_79_1_I_I); \II_next_state_srsts_i_o3[4]\: AND2 port map ( Y => NEXT_STATE_SRSTS_I_O3(4), A => N_92, B => write_n_or_read); \II_next_state_srsts_i_o3_1[3]\: AND2 port map ( Y => N_92, A => NEXT_STATE(5), B => N_90); \II_next_state_srsts_i_1[4]\: NOR2 port map ( Y => N_79_1_I_I, A => N_91_I_0, B => reset); \II_next_state_srsts_i[1]\: NOR3 port map ( Y => NEXT_STATE_SRSTS_I(1), A => N_105, B => N_106, C => reset); \II_next_state_srsts_i_a3_0[1]\: NOR2 port map ( Y => N_106, A => NEXT_STATE(1), B => mxfe_start); \II_next_state_srsts_i_a3[1]\: AOI21TTF port map ( Y => N_105, A => write_clock_enable, B => NEXT_STATE(1), C => NEXT_STATE_I(6)); \II_next_state_srsts_0[0]\: OR3 port map ( Y => NEXT_STATE_NSS(6), A => N_104_I, B => N_103_I, C => NEXT_STATE_SRSTS_0_0_I(0)); \II_next_state_srsts_0_0[0]\: AO21TTF port map ( Y => NEXT_STATE_SRSTS_0_0_I(0), A => write_clock_enable, B => NEXT_STATE_SRSTS_0_A3_0(0), C => N_102_I); \II_next_state_srsts_0_a3_0_3[0]\: NOR2FT port map ( Y => NEXT_STATE_SRSTS_0_A3_0(0), A => NEXT_STATE(0), B => reset_4); \II_next_state_srsts_0_a3_0[0]\: OR3 port map ( Y => N_102_I, A => reset_4, B => NEXT_STATE_SRSTS_0_O3(0), C => NEXT_STATE_SRSTS_0_A3_0_1_I(0)); \II_next_state_srsts_0_a3_0_1[0]\: NAND3FTT port map ( Y => NEXT_STATE_SRSTS_0_A3_0_1_I(0), A => COUNTER(3), B => COUNTER(4), C => NEXT_STATE(2)); \II_next_state_srsts_0_a3_1[0]\: NOR3FFT port map ( Y => N_103_I, A => NEXT_STATE(4), B => N_91_I_0, C => reset_4); \II_next_state_srsts_0_a3_2[0]\: NOR3FTT port map ( Y => N_104_I, A => N_94, B => reset_4, C => one_n_or_two); \II_next_state_srsts_0_o3_0[0]\: AND2 port map ( Y => N_94, A => N_91_I_0, B => NEXT_STATE(3)); \II_next_state_srsts_i_o3[3]\: AND2 port map ( Y => N_91_I_0, A => N_90, B => COUNTER(3)); \II_next_state_srsts_i_o3_0[5]\: NOR2 port map ( Y => N_90, A => NEXT_STATE_SRSTS_0_O3(0), B => COUNTER(4)); \II_next_state_srsts_0_o3[0]\: NAND3 port map ( Y => NEXT_STATE_SRSTS_0_O3(0), A => read_clock_enable_i_0_i, B => NEXT_STATE_SRSTS_0_O3_0(0), C => COUNTER(0)); \II_next_state_srsts_0_o3_0_0[0]\: AND2 port map ( Y => NEXT_STATE_SRSTS_0_O3_0(0), A => COUNTER(1), B => COUNTER(2)); II_int_load_configuration_data_out_1: NOR2FT port map ( Y => INT_LOAD_CONFIGURATION_DATA_OUT_1, A => INT_LOAD_CONFIGURATION_DATA_OUT_0, B => reset_4); II_int_load_configuration_data_out_0: MUX2H port map ( Y => INT_LOAD_CONFIGURATION_DATA_OUT_0, A => LOAD_CONFIGURATION_DATA_INT_67, B => NEXT_STATE(1), S => UN1_NEXT_STATE_12); II_un1_next_state_12_0: OR2 port map ( Y => UN1_NEXT_STATE_12, A => N_93, B => UN1_NEXT_STATE_2); \II_next_state_srsts_i_o3[5]\: NOR2FT port map ( Y => N_93, A => NEXT_STATE(1), B => write_clock_enable); II_int_shift_mxfe_register_data_out_1: NOR2FT port map ( Y => INT_SHIFT_MXFE_REGISTER_DATA_OUT_1, A => INT_SHIFT_MXFE_REGISTER_DATA_OUT_0, B => reset_3); II_int_shift_mxfe_register_data_out_0: MUX2H port map ( Y => INT_SHIFT_MXFE_REGISTER_DATA_OUT_0, A => SHIFT_MXFE_DATA_INT_66, B => NEXT_STATE_I(6), S => UN1_NEXT_STATE_10); II_un1_next_state_10_0: OAI21FTT port map ( Y => UN1_NEXT_STATE_10, A => NEXT_STATE(4), B => write_clock_enable, C => NEXT_STATE_I(6)); II_int_done_out_1: NOR2FT port map ( Y => INT_DONE_OUT_1, A => N_6, B => reset_3); II_int_done_out_0: MUX2H port map ( Y => N_6, A => CONFIGURATION_BUSY_INT_65, B => NEXT_STATE_I(6), S => UN1_NEXT_STATE_9); II_un1_next_state_9_0: OR2FT port map ( Y => UN1_NEXT_STATE_9, A => NEXT_STATE_I(6), B => N_113); \II_next_state_nss_i_i_a3[0]\: AND2FT port map ( Y => N_113, A => write_clock_enable, B => NEXT_STATE(0)); II_int_shift_configuration_data_out_1: NOR2FT port map ( Y => INT_SHIFT_CONFIGURATION_DATA_OUT_1, A => INT_SHIFT_CONFIGURATION_DATA_OUT_0, B => reset_3); II_int_shift_configuration_data_out_0: MUX2H port map ( Y => INT_SHIFT_CONFIGURATION_DATA_OUT_0, A => SHIFT_CONFIGURATION_DATA_INT_64, B => NEXT_STATE_I(6), S => UN1_NEXT_STATE_2); II_int_configure_mxfe_out_1: OR2 port map ( Y => INT_CONFIGURE_MXFE_OUT_1, A => INT_CONFIGURE_MXFE_OUT_0, B => reset); II_int_configure_mxfe_out_0: MUX2H port map ( Y => INT_CONFIGURE_MXFE_OUT_0, A => SPI_CS_N_OPAD_C_INT_63, B => NEXT_STATE_I_0(5), S => UN1_NEXT_STATE_2); II_un1_next_state_2_0: OR2FT port map ( Y => UN1_NEXT_STATE_2, A => NEXT_STATE_I(6), B => NEXT_STATE(5)); II_int_configure_mxfe_out_0_i: INV port map ( Y => NEXT_STATE_I_0(5), A => NEXT_STATE(5)); \II_next_state_CurrentState.counter_6[4]\: AND2 port map ( Y => COUNTER_6(4), A => N_69, B => I_22); \II_next_state_CurrentState.counter_6[3]\: AND2 port map ( Y => COUNTER_6(3), A => N_69, B => I_21); \II_next_state_CurrentState.counter_6[2]\: AND2 port map ( Y => COUNTER_6(2), A => N_69, B => I_20); \II_next_state_CurrentState.counter_6[1]\: AND2 port map ( Y => COUNTER_6(1), A => N_69, B => I_19); \II_next_state_CurrentState.counter_6[0]\: AND2 port map ( Y => COUNTER_6(0), A => N_69, B => DWACT_ADD_CI_0_PARTIAL_SUM(0)); II_un1_reset_in_1_i: NOR2FT port map ( Y => N_69, A => NEXT_STATE_I(6), B => reset); II_int_configure_mxfe_out: DFF port map ( Q => SPI_CS_N_OPAD_C_INT_63, CLK => mhz_20_clock_8, D => INT_CONFIGURE_MXFE_OUT_1); II_int_shift_configuration_data_out: DFF port map ( Q => SHIFT_CONFIGURATION_DATA_INT_64, CLK => mhz_20_clock_8, D => INT_SHIFT_CONFIGURATION_DATA_OUT_1); II_int_done_out: DFF port map ( Q => CONFIGURATION_BUSY_INT_65, CLK => mhz_20_clock_8, D => INT_DONE_OUT_1); II_int_shift_mxfe_register_data_out: DFF port map ( Q => SHIFT_MXFE_DATA_INT_66, CLK => mhz_20_clock_8, D => INT_SHIFT_MXFE_REGISTER_DATA_OUT_1); II_int_load_configuration_data_out: DFF port map ( Q => LOAD_CONFIGURATION_DATA_INT_67, CLK => mhz_20_clock_8, D => INT_LOAD_CONFIGURATION_DATA_OUT_1); \II_next_state_i[6]\: DFF port map ( Q => NEXT_STATE_I(6), CLK => mhz_20_clock_8, D => NEXT_STATE_NSS_I_I(0)); \II_next_state[5]\: DFF port map ( Q => NEXT_STATE(5), CLK => mhz_20_clock_8, D => NEXT_STATE_SRSTS_I(5)); \II_next_state[4]\: DFF port map ( Q => NEXT_STATE(4), CLK => mhz_20_clock_9, D => NEXT_STATE_SRSTS_I(4)); \II_next_state[3]\: DFF port map ( Q => NEXT_STATE(3), CLK => mhz_20_clock_9, D => N_77_I_0); \II_next_state[2]\: DFF port map ( Q => NEXT_STATE(2), CLK => mhz_20_clock_9, D => N_75_I_0); \II_next_state[1]\: DFF port map ( Q => NEXT_STATE(1), CLK => mhz_20_clock_9, D => NEXT_STATE_SRSTS_I(1)); \II_next_state[0]\: DFF port map ( Q => NEXT_STATE(0), CLK => mhz_20_clock_9, D => NEXT_STATE_NSS(6)); \II_counter[0]\: DFF port map ( Q => COUNTER(0), CLK => mhz_20_clock_9, D => COUNTER_6(0)); \II_counter[1]\: DFF port map ( Q => COUNTER(1), CLK => mhz_20_clock_9, D => COUNTER_6(1)); \II_counter[2]\: DFF port map ( Q => COUNTER(2), CLK => mhz_20_clock_9, D => COUNTER_6(2)); \II_counter[3]\: DFF port map ( Q => COUNTER(3), CLK => mhz_20_clock_9, D => COUNTER_6(3)); \II_counter[4]\: DFF port map ( Q => COUNTER(4), CLK => mhz_20_clock_9, D => COUNTER_6(4)); \II_un1_counter.I_28\: AND2 port map ( Y => DWACT_ADD_CI_0_POG_ARRAY_1(0), A => COUNTER(2), B => COUNTER(3)); \II_un1_counter.I_22\: XOR2 port map ( Y => I_22, A => COUNTER(4), B => DWACT_ADD_CI_0_G_ARRAY_2(0)); \II_un1_counter.I_21\: XOR2 port map ( Y => I_21, A => COUNTER(3), B => DWACT_ADD_CI_0_G_ARRAY_12(0)); \II_un1_counter.I_20\: XOR2 port map ( Y => I_20, A => COUNTER(2), B => DWACT_ADD_CI_0_G_ARRAY_1(0)); \II_un1_counter.I_19\: XOR2 port map ( Y => I_19, A => COUNTER(1), B => DWACT_ADD_CI_0_TMP(0)); \II_un1_counter.I_17\: XOR2 port map ( Y => DWACT_ADD_CI_0_PARTIAL_SUM(0), A => COUNTER(0), B => COUNTER_0_SQMUXA); \II_un1_counter.I_1\: AND2 port map ( Y => DWACT_ADD_CI_0_TMP(0), A => COUNTER(0), B => COUNTER_0_SQMUXA); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); spi_cs_n_opad_c <= SPI_CS_N_OPAD_C_INT_63; shift_configuration_data <= SHIFT_CONFIGURATION_DATA_INT_64; configuration_busy <= CONFIGURATION_BUSY_INT_65; shift_mxfe_data <= SHIFT_MXFE_DATA_INT_66; load_configuration_data <= LOAD_CONFIGURATION_DATA_INT_67; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity mxfe_clock_generator_1 is port( mhz_20_clock_13 : in std_logic; shift_configuration_data : in std_logic; dac_clock_opad_c : out std_logic; reset_0 : in std_logic; write_clock_enable : out std_logic; dac_clock_enable : in std_logic; read_clock_enable : out std_logic); end mxfe_clock_generator_1; architecture beh of mxfe_clock_generator_1 is signal DAC_CLOCK_OPAD_C_INT_75 : std_logic ; signal TOGGLE_Q : std_logic ; signal GATED_CLOCK_Q_1_0 : std_logic ; signal GATED_CLOCK_Q_0 : std_logic ; signal UN1_GATE_CLOCK_IN : std_logic ; signal TOGGLE_Q_1_0 : std_logic ; signal TOGGLE_Q_0_0 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component NOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component OR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component XOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component XOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_read_clock_enable_out: NOR2 port map ( Y => read_clock_enable, A => TOGGLE_Q, B => dac_clock_enable); II_write_clock_enable_out: OR2FT port map ( Y => write_clock_enable, A => TOGGLE_Q, B => dac_clock_enable); II_gated_clock_q_1: NOR2FT port map ( Y => GATED_CLOCK_Q_1_0, A => GATED_CLOCK_Q_0, B => reset_0); II_gated_clock_q_0: XOR2 port map ( Y => GATED_CLOCK_Q_0, A => UN1_GATE_CLOCK_IN, B => DAC_CLOCK_OPAD_C_INT_75); \II_gated_clock_ff.un1_gate_clock_in\: NOR2FT port map ( Y => UN1_GATE_CLOCK_IN, A => shift_configuration_data, B => dac_clock_enable); II_toggle_q_1: NOR2FT port map ( Y => TOGGLE_Q_1_0, A => TOGGLE_Q_0_0, B => reset_0); II_toggle_q_0: XOR2FT port map ( Y => TOGGLE_Q_0_0, A => dac_clock_enable, B => TOGGLE_Q); II_toggle_q: DFF port map ( Q => TOGGLE_Q, CLK => mhz_20_clock_13, D => TOGGLE_Q_1_0); II_gated_clock_q: DFF port map ( Q => DAC_CLOCK_OPAD_C_INT_75, CLK => mhz_20_clock_13, D => GATED_CLOCK_Q_1_0); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); dac_clock_opad_c <= DAC_CLOCK_OPAD_C_INT_75; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity dac_serializer_fsm is port( mhz_20_clock_13 : in std_logic; mhz_20_clock_12 : in std_logic; dac_cs_n_opad_c : out std_logic; shift_configuration_data : out std_logic; dac_transfer_busy : out std_logic; load_configuration_data : out std_logic; write_clock_enable : in std_logic; read_clock_enable : in std_logic; reset : in std_logic; dac_start : in std_logic; reset_1 : in std_logic; mhz_20_clock_1 : in std_logic; load_configuration_data_0 : out std_logic; mhz_20_clock_0 : in std_logic; load_configuration_data_1 : out std_logic); end dac_serializer_fsm; architecture beh of dac_serializer_fsm is signal DWACT_ADD_CI_0_G_ARRAY_2 : std_logic_vector (0 to 0); signal DWACT_ADD_CI_0_G_ARRAY_1 : std_logic_vector (0 to 0); signal DWACT_ADD_CI_0_POG_ARRAY_1 : std_logic_vector (0 to 0); signal DWACT_ADD_CI_0_G_ARRAY_12 : std_logic_vector (0 to 0); signal COUNTER : std_logic_vector (4 downto 0); signal DWACT_ADD_CI_0_TMP : std_logic_vector (0 to 0); signal NEXT_STATE_NSS_I_I_0 : std_logic_vector (0 to 0); signal NEXT_STATE_NSS_I_I_A3 : std_logic_vector (0 to 0); signal NEXT_STATE_NSS_I_I_A3_0 : std_logic_vector (0 to 0); signal NEXT_STATE_I : std_logic_vector (4 to 4); signal NEXT_STATE_SRSTS_I : std_logic_vector (3 downto 2); signal NEXT_STATE_SRSTS_I_0_I : std_logic_vector (3 downto 1); signal NEXT_STATE : std_logic_vector (3 downto 0); signal NEXT_STATE_SRSTS_I_O2 : std_logic_vector (3 to 3); signal NEXT_STATE_SRSTS_I_A3 : std_logic_vector (2 to 2); signal NEXT_STATE_SRSTS_I_A2 : std_logic_vector (2 to 2); signal NEXT_STATE_SRSTS_I_0 : std_logic_vector (1 to 1); signal NEXT_STATE_NSS : std_logic_vector (4 to 4); signal NEXT_STATE_SRSTS_0_A3_0_0 : std_logic_vector (0 to 0); signal NEXT_STATE_SRSTS_0_A3 : std_logic_vector (0 to 0); signal NEXT_STATE_SRSTS_I_O2_0_I : std_logic_vector (3 to 3); signal NEXT_STATE_SRSTS_I_O2_1_I : std_logic_vector (3 to 3); signal NEXT_STATE_I_0 : std_logic_vector (3 to 3); signal COUNTER_6 : std_logic_vector (4 downto 0); signal DWACT_ADD_CI_0_PARTIAL_SUM : std_logic_vector (0 to 0); signal DAC_CS_N_OPAD_C_INT_71 : std_logic ; signal SHIFT_CONFIGURATION_DATA_INT_72 : std_logic ; signal DAC_TRANSFER_BUSY_INT_73 : std_logic ; signal LOAD_CONFIGURATION_DATA_INT_74 : std_logic ; signal INT_LOAD_CONFIGURATION_DATA_OUT_1_0 : std_logic ; signal N_77_I : std_logic ; signal UN1_NEXT_STATE_8_I_O2 : std_logic ; signal COUNTER_0_SQMUXA_1_I : std_logic ; signal INT_LOAD_CONFIGURATION_DATA_OUT_0_0 : std_logic ; signal UN1_NEXT_STATE_8_I : std_logic ; signal UN1_NEXT_STATE_2_I_A2 : std_logic ; signal INT_DONE_OUT_1_0 : std_logic ; signal INT_DONE_OUT_0 : std_logic ; signal INT_SHIFT_CONFIGURATION_DATA_OUT_1_0 : std_logic ; signal INT_SHIFT_CONFIGURATION_DATA_OUT_0_0 : std_logic ; signal INT_SELECT_DAC_N_OUT_1 : std_logic ; signal INT_SELECT_DAC_N_OUT_0 : std_logic ; signal UN1_RESET_IN_1_I : std_logic ; signal I_22_0 : std_logic ; signal I_21_0 : std_logic ; signal I_20_0 : std_logic ; signal I_19_0 : std_logic ; signal N_14 : std_logic ; signal N_13 : std_logic ; signal N_12 : std_logic ; signal N_11 : std_logic ; signal N_10 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component AND2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component AND3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OAI21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR3 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OA21FTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AOI21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OA21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OA21 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AO21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NAND3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NAND2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NAND2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component OR3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component MUX2H port( Y : out std_logic; A : in std_logic; B : in std_logic; S : in std_logic ); end component; component OAI21 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AOI21FTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component INV port( Y : out std_logic; A : in std_logic ); end component; component XOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_int_load_configuration_data_out_1_0: DFF port map ( Q => load_configuration_data_1, CLK => mhz_20_clock_0, D => INT_LOAD_CONFIGURATION_DATA_OUT_1_0); II_int_load_configuration_data_out_0_0: DFF port map ( Q => load_configuration_data_0, CLK => mhz_20_clock_1, D => INT_LOAD_CONFIGURATION_DATA_OUT_1_0); \II_un1_counter.I_27\: AND2 port map ( Y => DWACT_ADD_CI_0_G_ARRAY_2(0), A => DWACT_ADD_CI_0_G_ARRAY_1(0), B => DWACT_ADD_CI_0_POG_ARRAY_1(0)); \II_un1_counter.I_25\: AND2 port map ( Y => DWACT_ADD_CI_0_G_ARRAY_12(0), A => DWACT_ADD_CI_0_G_ARRAY_1(0), B => COUNTER(2)); \II_un1_counter.I_26\: AND2 port map ( Y => DWACT_ADD_CI_0_G_ARRAY_1(0), A => DWACT_ADD_CI_0_TMP(0), B => COUNTER(1)); \II_next_state_nss_i_i[0]\: NOR3FFT port map ( Y => NEXT_STATE_NSS_I_I_0(0), A => NEXT_STATE_NSS_I_I_A3(0), B => NEXT_STATE_NSS_I_I_A3_0(0), C => reset_1); \II_next_state_nss_i_i_a3_0[0]\: OR2 port map ( Y => NEXT_STATE_NSS_I_I_A3_0(0), A => NEXT_STATE_I(4), B => dac_start); \II_next_state_srsts_i[3]\: AND3FFT port map ( Y => NEXT_STATE_SRSTS_I(3), A => N_77_I, B => NEXT_STATE_SRSTS_I_0_I(3), C => UN1_NEXT_STATE_8_I_O2); \II_next_state_srsts_i_0[3]\: OAI21TTF port map ( Y => NEXT_STATE_SRSTS_I_0_I(3), A => NEXT_STATE(3), B => NEXT_STATE(1), C => reset_1); \II_next_state_srsts_i_a3_0[3]\: NOR3 port map ( Y => N_77_I, A => NEXT_STATE_SRSTS_I_O2(3), B => NEXT_STATE(1), C => COUNTER(4)); \II_next_state_srsts_i[2]\: NOR3 port map ( Y => NEXT_STATE_SRSTS_I(2), A => NEXT_STATE_SRSTS_I_A3(2), B => NEXT_STATE_SRSTS_I_A2(2), C => reset); \II_next_state_srsts_i_a3[2]\: OA21FTF port map ( Y => NEXT_STATE_SRSTS_I_A3(2), A => NEXT_STATE(3), B => NEXT_STATE_SRSTS_I_O2(3), C => NEXT_STATE(2)); \II_next_state_srsts_i[1]\: AOI21TTF port map ( Y => NEXT_STATE_SRSTS_I_0(1), A => UN1_NEXT_STATE_8_I_O2, B => NEXT_STATE_I(4), C => NEXT_STATE_SRSTS_I_0_I(1)); \II_next_state_srsts_i_0[1]\: OA21TTF port map ( Y => NEXT_STATE_SRSTS_I_0_I(1), A => NEXT_STATE(1), B => dac_start, C => reset); II_counter_0_sqmuxa_1_i: OA21 port map ( Y => COUNTER_0_SQMUXA_1_I, A => NEXT_STATE(2), B => NEXT_STATE(3), C => read_clock_enable); \II_next_state_srsts_0[0]\: AO21TTF port map ( Y => NEXT_STATE_NSS(4), A => NEXT_STATE_SRSTS_I_A2(2), B => NEXT_STATE_SRSTS_0_A3_0_0(0), C => NEXT_STATE_SRSTS_0_A3(0)); \II_next_state_srsts_0_a3_0_0_0[0]\: NOR2FT port map ( Y => NEXT_STATE_SRSTS_0_A3_0_0(0), A => NEXT_STATE(2), B => reset_1); \II_next_state_srsts_i_a2[2]\: NOR2FT port map ( Y => NEXT_STATE_SRSTS_I_A2(2), A => COUNTER(4), B => NEXT_STATE_SRSTS_I_O2(3)); \II_next_state_srsts_i_o2[3]\: NAND3FFT port map ( Y => NEXT_STATE_SRSTS_I_O2(3), A => NEXT_STATE_SRSTS_I_O2_0_I(3), B => NEXT_STATE_SRSTS_I_O2_1_I(3), C => read_clock_enable); \II_next_state_srsts_i_o2_1[3]\: NAND2FT port map ( Y => NEXT_STATE_SRSTS_I_O2_1_I(3), A => COUNTER(3), B => COUNTER(0)); \II_next_state_srsts_i_o2_0[3]\: NAND2 port map ( Y => NEXT_STATE_SRSTS_I_O2_0_I(3), A => COUNTER(1), B => COUNTER(2)); \II_next_state_srsts_0_a3[0]\: OR3FFT port map ( Y => NEXT_STATE_SRSTS_0_A3(0), A => NEXT_STATE(0), B => write_clock_enable, C => reset_1); II_int_load_configuration_data_out_1: NOR2FT port map ( Y => INT_LOAD_CONFIGURATION_DATA_OUT_1_0, A => INT_LOAD_CONFIGURATION_DATA_OUT_0_0, B => reset_1); II_int_load_configuration_data_out_0: MUX2H port map ( Y => INT_LOAD_CONFIGURATION_DATA_OUT_0_0, A => NEXT_STATE(1), B => LOAD_CONFIGURATION_DATA_INT_74, S => UN1_NEXT_STATE_8_I); II_un1_next_state_8_i: OAI21 port map ( Y => UN1_NEXT_STATE_8_I, A => UN1_NEXT_STATE_2_I_A2, B => NEXT_STATE(1), C => UN1_NEXT_STATE_8_I_O2); II_un1_next_state_8_i_o2: NAND2 port map ( Y => UN1_NEXT_STATE_8_I_O2, A => NEXT_STATE(1), B => write_clock_enable); II_int_done_out_1: NOR2FT port map ( Y => INT_DONE_OUT_1_0, A => INT_DONE_OUT_0, B => reset_1); II_int_done_out_0: AOI21FTF port map ( Y => INT_DONE_OUT_0, A => DAC_TRANSFER_BUSY_INT_73, B => NEXT_STATE_NSS_I_I_A3(0), C => NEXT_STATE_I(4)); \II_next_state_nss_i_i_a3[0]\: OR2FT port map ( Y => NEXT_STATE_NSS_I_I_A3(0), A => NEXT_STATE(0), B => write_clock_enable); II_int_shift_configuration_data_out_1: NOR2FT port map ( Y => INT_SHIFT_CONFIGURATION_DATA_OUT_1_0, A => INT_SHIFT_CONFIGURATION_DATA_OUT_0_0, B => reset_1); II_int_shift_configuration_data_out_0: MUX2H port map ( Y => INT_SHIFT_CONFIGURATION_DATA_OUT_0_0, A => SHIFT_CONFIGURATION_DATA_INT_72, B => NEXT_STATE_I(4), S => UN1_NEXT_STATE_2_I_A2); II_int_select_dac_n_out_1: OR2 port map ( Y => INT_SELECT_DAC_N_OUT_1, A => INT_SELECT_DAC_N_OUT_0, B => reset); II_int_select_dac_n_out_0: MUX2H port map ( Y => INT_SELECT_DAC_N_OUT_0, A => DAC_CS_N_OPAD_C_INT_71, B => NEXT_STATE_I_0(3), S => UN1_NEXT_STATE_2_I_A2); II_un1_next_state_2_i_a2: OR2FT port map ( Y => UN1_NEXT_STATE_2_I_A2, A => NEXT_STATE_I(4), B => NEXT_STATE(3)); II_int_select_dac_n_out_0_i: INV port map ( Y => NEXT_STATE_I_0(3), A => NEXT_STATE(3)); \II_next_state_CurrentState.counter_6[4]\: AND2 port map ( Y => COUNTER_6(4), A => UN1_RESET_IN_1_I, B => I_22_0); \II_next_state_CurrentState.counter_6[3]\: AND2 port map ( Y => COUNTER_6(3), A => UN1_RESET_IN_1_I, B => I_21_0); \II_next_state_CurrentState.counter_6[2]\: AND2 port map ( Y => COUNTER_6(2), A => UN1_RESET_IN_1_I, B => I_20_0); \II_next_state_CurrentState.counter_6[1]\: AND2 port map ( Y => COUNTER_6(1), A => UN1_RESET_IN_1_I, B => I_19_0); \II_next_state_CurrentState.counter_6[0]\: AND2 port map ( Y => COUNTER_6(0), A => UN1_RESET_IN_1_I, B => DWACT_ADD_CI_0_PARTIAL_SUM(0)); II_un1_reset_in_1_i: NOR2FT port map ( Y => UN1_RESET_IN_1_I, A => NEXT_STATE_I(4), B => reset_1); II_int_select_dac_n_out: DFF port map ( Q => DAC_CS_N_OPAD_C_INT_71, CLK => mhz_20_clock_12, D => INT_SELECT_DAC_N_OUT_1); II_int_shift_configuration_data_out: DFF port map ( Q => SHIFT_CONFIGURATION_DATA_INT_72, CLK => mhz_20_clock_12, D => INT_SHIFT_CONFIGURATION_DATA_OUT_1_0); II_int_done_out: DFF port map ( Q => DAC_TRANSFER_BUSY_INT_73, CLK => mhz_20_clock_12, D => INT_DONE_OUT_1_0); II_int_load_configuration_data_out: DFF port map ( Q => LOAD_CONFIGURATION_DATA_INT_74, CLK => mhz_20_clock_12, D => INT_LOAD_CONFIGURATION_DATA_OUT_1_0); \II_next_state_i[4]\: DFF port map ( Q => NEXT_STATE_I(4), CLK => mhz_20_clock_13, D => NEXT_STATE_NSS_I_I_0(0)); \II_next_state[3]\: DFF port map ( Q => NEXT_STATE(3), CLK => mhz_20_clock_13, D => NEXT_STATE_SRSTS_I(3)); \II_next_state[2]\: DFF port map ( Q => NEXT_STATE(2), CLK => mhz_20_clock_13, D => NEXT_STATE_SRSTS_I(2)); \II_next_state[1]\: DFF port map ( Q => NEXT_STATE(1), CLK => mhz_20_clock_13, D => NEXT_STATE_SRSTS_I_0(1)); \II_next_state[0]\: DFF port map ( Q => NEXT_STATE(0), CLK => mhz_20_clock_13, D => NEXT_STATE_NSS(4)); \II_counter[0]\: DFF port map ( Q => COUNTER(0), CLK => mhz_20_clock_13, D => COUNTER_6(0)); \II_counter[1]\: DFF port map ( Q => COUNTER(1), CLK => mhz_20_clock_13, D => COUNTER_6(1)); \II_counter[2]\: DFF port map ( Q => COUNTER(2), CLK => mhz_20_clock_13, D => COUNTER_6(2)); \II_counter[3]\: DFF port map ( Q => COUNTER(3), CLK => mhz_20_clock_13, D => COUNTER_6(3)); \II_counter[4]\: DFF port map ( Q => COUNTER(4), CLK => mhz_20_clock_13, D => COUNTER_6(4)); \II_un1_counter.I_28\: AND2 port map ( Y => DWACT_ADD_CI_0_POG_ARRAY_1(0), A => COUNTER(2), B => COUNTER(3)); \II_un1_counter.I_22\: XOR2 port map ( Y => I_22_0, A => COUNTER(4), B => DWACT_ADD_CI_0_G_ARRAY_2(0)); \II_un1_counter.I_21\: XOR2 port map ( Y => I_21_0, A => COUNTER(3), B => DWACT_ADD_CI_0_G_ARRAY_12(0)); \II_un1_counter.I_20\: XOR2 port map ( Y => I_20_0, A => COUNTER(2), B => DWACT_ADD_CI_0_G_ARRAY_1(0)); \II_un1_counter.I_19\: XOR2 port map ( Y => I_19_0, A => COUNTER(1), B => DWACT_ADD_CI_0_TMP(0)); \II_un1_counter.I_17\: XOR2 port map ( Y => DWACT_ADD_CI_0_PARTIAL_SUM(0), A => COUNTER(0), B => COUNTER_0_SQMUXA_1_I); \II_un1_counter.I_1\: AND2 port map ( Y => DWACT_ADD_CI_0_TMP(0), A => COUNTER(0), B => COUNTER_0_SQMUXA_1_I); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); dac_cs_n_opad_c <= DAC_CS_N_OPAD_C_INT_71; shift_configuration_data <= SHIFT_CONFIGURATION_DATA_INT_72; dac_transfer_busy <= DAC_TRANSFER_BUSY_INT_73; load_configuration_data <= LOAD_CONFIGURATION_DATA_INT_74; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity piso_shift_register_1 is port( dac_data : in std_logic_vector (23 downto 0); mhz_20_clock_12 : in std_logic; mhz_20_clock_11 : in std_logic; mhz_20_clock_10 : in std_logic; reset_1 : in std_logic; load_configuration_data : in std_logic; reset_2 : in std_logic; load_configuration_data_1 : in std_logic; dac_data_opad_c : out std_logic; reset_3 : in std_logic; load_configuration_data_0 : in std_logic; write_clock_enable : in std_logic; shift_configuration_data : in std_logic); end piso_shift_register_1; architecture beh of piso_shift_register_1 is signal PARALLEL_IN_SERIAL_OUT_1_0 : std_logic_vector (23 downto 0); signal PARALLEL_IN_SERIAL_OUT_0_0 : std_logic_vector (23 downto 0); signal PARALLEL_IN_SERIAL_OUT_4 : std_logic_vector (23 downto 0); signal PARALLEL_IN_SERIAL_OUT : std_logic_vector (22 downto 0); signal PARALLEL_IN_SERIAL_OUT_0 : std_logic_vector (22 to 22); signal DAC_DATA_OPAD_C_INT_70 : std_logic ; signal UN1_LOAD_IN_1_0 : std_logic ; signal UN1_LOAD_IN_1_0_0 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component OA21FTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component MUX2H port( Y : out std_logic; A : in std_logic; B : in std_logic; S : in std_logic ); end component; component AND2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_un1_load_in_1_0: OA21FTF port map ( Y => UN1_LOAD_IN_1_0, A => shift_configuration_data, B => write_clock_enable, C => load_configuration_data_0); \II_parallel_in_serial_out_1[23]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(23), A => PARALLEL_IN_SERIAL_OUT_0_0(23), B => reset_3); \II_parallel_in_serial_out_0[23]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(23), A => PARALLEL_IN_SERIAL_OUT_4(23), B => DAC_DATA_OPAD_C_INT_70, S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[23]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(23), A => PARALLEL_IN_SERIAL_OUT(22), B => dac_data(23), S => load_configuration_data_0); \II_parallel_in_serial_out_1[22]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(22), A => PARALLEL_IN_SERIAL_OUT_0(22), B => reset_3); \II_parallel_in_serial_out_0[22]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(22), A => PARALLEL_IN_SERIAL_OUT_4(22), B => PARALLEL_IN_SERIAL_OUT(22), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[22]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(22), A => PARALLEL_IN_SERIAL_OUT(21), B => dac_data(22), S => load_configuration_data_0); \II_parallel_in_serial_out_1[21]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(21), A => PARALLEL_IN_SERIAL_OUT_0_0(21), B => reset_3); \II_parallel_in_serial_out_0[21]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(21), A => PARALLEL_IN_SERIAL_OUT_4(21), B => PARALLEL_IN_SERIAL_OUT(21), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[21]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(21), A => PARALLEL_IN_SERIAL_OUT(20), B => dac_data(21), S => load_configuration_data_0); \II_parallel_in_serial_out_1[20]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(20), A => PARALLEL_IN_SERIAL_OUT_0_0(20), B => reset_3); \II_parallel_in_serial_out_0[20]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(20), A => PARALLEL_IN_SERIAL_OUT_4(20), B => PARALLEL_IN_SERIAL_OUT(20), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[20]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(20), A => PARALLEL_IN_SERIAL_OUT(19), B => dac_data(20), S => load_configuration_data_0); \II_parallel_in_serial_out_1[19]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(19), A => PARALLEL_IN_SERIAL_OUT_0_0(19), B => reset_3); \II_parallel_in_serial_out_0[19]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(19), A => PARALLEL_IN_SERIAL_OUT_4(19), B => PARALLEL_IN_SERIAL_OUT(19), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[19]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(19), A => PARALLEL_IN_SERIAL_OUT(18), B => dac_data(19), S => load_configuration_data_0); \II_parallel_in_serial_out_1[18]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(18), A => PARALLEL_IN_SERIAL_OUT_0_0(18), B => reset_3); \II_parallel_in_serial_out_0[18]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(18), A => PARALLEL_IN_SERIAL_OUT_4(18), B => PARALLEL_IN_SERIAL_OUT(18), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[18]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(18), A => PARALLEL_IN_SERIAL_OUT(17), B => dac_data(18), S => load_configuration_data_0); \II_parallel_in_serial_out_1[17]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(17), A => PARALLEL_IN_SERIAL_OUT_0_0(17), B => reset_3); \II_parallel_in_serial_out_0[17]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(17), A => PARALLEL_IN_SERIAL_OUT_4(17), B => PARALLEL_IN_SERIAL_OUT(17), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[17]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(17), A => PARALLEL_IN_SERIAL_OUT(16), B => dac_data(17), S => load_configuration_data_0); \II_parallel_in_serial_out_1[16]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(16), A => PARALLEL_IN_SERIAL_OUT_0_0(16), B => reset_3); \II_parallel_in_serial_out_0[16]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(16), A => PARALLEL_IN_SERIAL_OUT_4(16), B => PARALLEL_IN_SERIAL_OUT(16), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[16]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(16), A => PARALLEL_IN_SERIAL_OUT(15), B => dac_data(16), S => load_configuration_data_0); \II_parallel_in_serial_out_1[15]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(15), A => PARALLEL_IN_SERIAL_OUT_0_0(15), B => reset_3); \II_parallel_in_serial_out_0[15]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(15), A => PARALLEL_IN_SERIAL_OUT_4(15), B => PARALLEL_IN_SERIAL_OUT(15), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[15]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(15), A => PARALLEL_IN_SERIAL_OUT(14), B => dac_data(15), S => load_configuration_data_1); \II_parallel_in_serial_out_1[14]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(14), A => PARALLEL_IN_SERIAL_OUT_0_0(14), B => reset_2); \II_parallel_in_serial_out_0[14]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(14), A => PARALLEL_IN_SERIAL_OUT_4(14), B => PARALLEL_IN_SERIAL_OUT(14), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[14]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(14), A => PARALLEL_IN_SERIAL_OUT(13), B => dac_data(14), S => load_configuration_data_1); \II_parallel_in_serial_out_1[13]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(13), A => PARALLEL_IN_SERIAL_OUT_0_0(13), B => reset_2); \II_parallel_in_serial_out_0[13]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(13), A => PARALLEL_IN_SERIAL_OUT_4(13), B => PARALLEL_IN_SERIAL_OUT(13), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[13]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(13), A => PARALLEL_IN_SERIAL_OUT(12), B => dac_data(13), S => load_configuration_data_1); \II_parallel_in_serial_out_1[12]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(12), A => PARALLEL_IN_SERIAL_OUT_0_0(12), B => reset_2); \II_parallel_in_serial_out_0[12]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(12), A => PARALLEL_IN_SERIAL_OUT_4(12), B => PARALLEL_IN_SERIAL_OUT(12), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[12]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(12), A => PARALLEL_IN_SERIAL_OUT(11), B => dac_data(12), S => load_configuration_data_1); \II_parallel_in_serial_out_1[11]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(11), A => PARALLEL_IN_SERIAL_OUT_0_0(11), B => reset_2); \II_parallel_in_serial_out_0[11]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(11), A => PARALLEL_IN_SERIAL_OUT_4(11), B => PARALLEL_IN_SERIAL_OUT(11), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[11]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(11), A => PARALLEL_IN_SERIAL_OUT(10), B => dac_data(11), S => load_configuration_data_1); \II_parallel_in_serial_out_1[10]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(10), A => PARALLEL_IN_SERIAL_OUT_0_0(10), B => reset_2); \II_parallel_in_serial_out_0[10]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(10), A => PARALLEL_IN_SERIAL_OUT_4(10), B => PARALLEL_IN_SERIAL_OUT(10), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[10]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(10), A => PARALLEL_IN_SERIAL_OUT(9), B => dac_data(10), S => load_configuration_data_1); \II_parallel_in_serial_out_1[9]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(9), A => PARALLEL_IN_SERIAL_OUT_0_0(9), B => reset_2); \II_parallel_in_serial_out_0[9]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(9), A => PARALLEL_IN_SERIAL_OUT_4(9), B => PARALLEL_IN_SERIAL_OUT(9), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[9]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(9), A => PARALLEL_IN_SERIAL_OUT(8), B => dac_data(9), S => load_configuration_data_1); \II_parallel_in_serial_out_1[8]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(8), A => PARALLEL_IN_SERIAL_OUT_0_0(8), B => reset_2); \II_parallel_in_serial_out_0[8]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(8), A => PARALLEL_IN_SERIAL_OUT_4(8), B => PARALLEL_IN_SERIAL_OUT(8), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[8]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(8), A => PARALLEL_IN_SERIAL_OUT(7), B => dac_data(8), S => load_configuration_data_1); \II_parallel_in_serial_out_1[7]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(7), A => PARALLEL_IN_SERIAL_OUT_0_0(7), B => reset_2); \II_parallel_in_serial_out_0[7]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(7), A => PARALLEL_IN_SERIAL_OUT_4(7), B => PARALLEL_IN_SERIAL_OUT(7), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[7]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(7), A => PARALLEL_IN_SERIAL_OUT(6), B => dac_data(7), S => load_configuration_data_1); \II_parallel_in_serial_out_1[6]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(6), A => PARALLEL_IN_SERIAL_OUT_0_0(6), B => reset_2); \II_parallel_in_serial_out_0[6]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(6), A => PARALLEL_IN_SERIAL_OUT_4(6), B => PARALLEL_IN_SERIAL_OUT(6), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[6]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(6), A => PARALLEL_IN_SERIAL_OUT(5), B => dac_data(6), S => load_configuration_data_1); \II_parallel_in_serial_out_1[5]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(5), A => PARALLEL_IN_SERIAL_OUT_0_0(5), B => reset_2); \II_parallel_in_serial_out_0[5]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(5), A => PARALLEL_IN_SERIAL_OUT_4(5), B => PARALLEL_IN_SERIAL_OUT(5), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[5]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(5), A => PARALLEL_IN_SERIAL_OUT(4), B => dac_data(5), S => load_configuration_data); \II_parallel_in_serial_out_1[4]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(4), A => PARALLEL_IN_SERIAL_OUT_0_0(4), B => reset_2); \II_parallel_in_serial_out_0[4]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(4), A => PARALLEL_IN_SERIAL_OUT_4(4), B => PARALLEL_IN_SERIAL_OUT(4), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[4]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(4), A => PARALLEL_IN_SERIAL_OUT(3), B => dac_data(4), S => load_configuration_data); \II_parallel_in_serial_out_1[3]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(3), A => PARALLEL_IN_SERIAL_OUT_0_0(3), B => reset_2); \II_parallel_in_serial_out_0[3]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(3), A => PARALLEL_IN_SERIAL_OUT_4(3), B => PARALLEL_IN_SERIAL_OUT(3), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[3]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(3), A => PARALLEL_IN_SERIAL_OUT(2), B => dac_data(3), S => load_configuration_data); \II_parallel_in_serial_out_1[2]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(2), A => PARALLEL_IN_SERIAL_OUT_0_0(2), B => reset_1); \II_parallel_in_serial_out_0[2]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(2), A => PARALLEL_IN_SERIAL_OUT_4(2), B => PARALLEL_IN_SERIAL_OUT(2), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[2]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(2), A => PARALLEL_IN_SERIAL_OUT(1), B => dac_data(2), S => load_configuration_data); \II_parallel_in_serial_out_1[1]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(1), A => PARALLEL_IN_SERIAL_OUT_0_0(1), B => reset_1); \II_parallel_in_serial_out_0[1]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(1), A => PARALLEL_IN_SERIAL_OUT_4(1), B => PARALLEL_IN_SERIAL_OUT(1), S => UN1_LOAD_IN_1_0_0); \II_piso.parallel_in_serial_out_4[1]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(1), A => PARALLEL_IN_SERIAL_OUT(0), B => dac_data(1), S => load_configuration_data); \II_parallel_in_serial_out_1[0]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1_0(0), A => PARALLEL_IN_SERIAL_OUT_0_0(0), B => reset_1); \II_parallel_in_serial_out_0[0]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0_0(0), A => PARALLEL_IN_SERIAL_OUT_4(0), B => PARALLEL_IN_SERIAL_OUT(0), S => UN1_LOAD_IN_1_0_0); II_un1_load_in_1: OA21FTF port map ( Y => UN1_LOAD_IN_1_0_0, A => shift_configuration_data, B => write_clock_enable, C => load_configuration_data_0); \II_piso.parallel_in_serial_out_4[0]\: AND2 port map ( Y => PARALLEL_IN_SERIAL_OUT_4(0), A => load_configuration_data, B => dac_data(0)); \II_parallel_in_serial_out[0]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(0), CLK => mhz_20_clock_10, D => PARALLEL_IN_SERIAL_OUT_1_0(0)); \II_parallel_in_serial_out[1]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(1), CLK => mhz_20_clock_10, D => PARALLEL_IN_SERIAL_OUT_1_0(1)); \II_parallel_in_serial_out[2]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(2), CLK => mhz_20_clock_10, D => PARALLEL_IN_SERIAL_OUT_1_0(2)); \II_parallel_in_serial_out[3]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(3), CLK => mhz_20_clock_10, D => PARALLEL_IN_SERIAL_OUT_1_0(3)); \II_parallel_in_serial_out[4]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(4), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(4)); \II_parallel_in_serial_out[5]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(5), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(5)); \II_parallel_in_serial_out[6]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(6), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(6)); \II_parallel_in_serial_out[7]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(7), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(7)); \II_parallel_in_serial_out[8]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(8), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(8)); \II_parallel_in_serial_out[9]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(9), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(9)); \II_parallel_in_serial_out[10]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(10), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(10)); \II_parallel_in_serial_out[11]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(11), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(11)); \II_parallel_in_serial_out[12]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(12), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(12)); \II_parallel_in_serial_out[13]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(13), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(13)); \II_parallel_in_serial_out[14]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(14), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(14)); \II_parallel_in_serial_out[15]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(15), CLK => mhz_20_clock_11, D => PARALLEL_IN_SERIAL_OUT_1_0(15)); \II_parallel_in_serial_out[16]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(16), CLK => mhz_20_clock_12, D => PARALLEL_IN_SERIAL_OUT_1_0(16)); \II_parallel_in_serial_out[17]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(17), CLK => mhz_20_clock_12, D => PARALLEL_IN_SERIAL_OUT_1_0(17)); \II_parallel_in_serial_out[18]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(18), CLK => mhz_20_clock_12, D => PARALLEL_IN_SERIAL_OUT_1_0(18)); \II_parallel_in_serial_out[19]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(19), CLK => mhz_20_clock_12, D => PARALLEL_IN_SERIAL_OUT_1_0(19)); \II_parallel_in_serial_out[20]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(20), CLK => mhz_20_clock_12, D => PARALLEL_IN_SERIAL_OUT_1_0(20)); \II_parallel_in_serial_out[21]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(21), CLK => mhz_20_clock_12, D => PARALLEL_IN_SERIAL_OUT_1_0(21)); \II_parallel_in_serial_out[22]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(22), CLK => mhz_20_clock_12, D => PARALLEL_IN_SERIAL_OUT_1_0(22)); \II_parallel_in_serial_out[23]\: DFF port map ( Q => DAC_DATA_OPAD_C_INT_70, CLK => mhz_20_clock_12, D => PARALLEL_IN_SERIAL_OUT_1_0(23)); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); dac_data_opad_c <= DAC_DATA_OPAD_C_INT_70; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity mxfe_clock_generator is port( mhz_20_clock_9 : in std_logic; read_clock_enable_i_0_i : out std_logic; reset_0 : in std_logic; shift_configuration_data : in std_logic; spi_clock_opad_c : out std_logic; reset_1 : in std_logic; dac_clock_enable : in std_logic; write_clock_enable : out std_logic); end mxfe_clock_generator; architecture beh of mxfe_clock_generator is signal SPI_CLOCK_OPAD_C_INT_68 : std_logic ; signal TOGGLE_Q : std_logic ; signal GATED_CLOCK_Q_1 : std_logic ; signal N_1 : std_logic ; signal UN1_GATE_CLOCK_IN : std_logic ; signal TOGGLE_Q_1 : std_logic ; signal TOGGLE_Q_0 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component OR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component XOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component XOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_write_clock_enable_out: OR2FT port map ( Y => write_clock_enable, A => TOGGLE_Q, B => dac_clock_enable); II_gated_clock_q_1: NOR2FT port map ( Y => GATED_CLOCK_Q_1, A => N_1, B => reset_1); II_gated_clock_q_0: XOR2 port map ( Y => N_1, A => UN1_GATE_CLOCK_IN, B => SPI_CLOCK_OPAD_C_INT_68); \II_gated_clock_ff.un1_gate_clock_in\: NOR2FT port map ( Y => UN1_GATE_CLOCK_IN, A => shift_configuration_data, B => dac_clock_enable); II_toggle_q_1: NOR2FT port map ( Y => TOGGLE_Q_1, A => TOGGLE_Q_0, B => reset_0); II_toggle_q_0: XOR2FT port map ( Y => TOGGLE_Q_0, A => dac_clock_enable, B => TOGGLE_Q); II_read_clock_enable_out: NOR2 port map ( Y => read_clock_enable_i_0_i, A => TOGGLE_Q, B => dac_clock_enable); II_toggle_q: DFF port map ( Q => TOGGLE_Q, CLK => mhz_20_clock_9, D => TOGGLE_Q_1); II_gated_clock_q: DFF port map ( Q => SPI_CLOCK_OPAD_C_INT_68, CLK => mhz_20_clock_9, D => GATED_CLOCK_Q_1); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); spi_clock_opad_c <= SPI_CLOCK_OPAD_C_INT_68; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity piso_shift_register is port( mxfe_configuration_data : in std_logic_vector (21 downto 0); mhz_20_clock_8 : in std_logic; mhz_20_clock_7 : in std_logic; mhz_20_clock_6 : in std_logic; load_configuration_data : in std_logic; reset_4 : in std_logic; load_configuration_data_1 : in std_logic; reset_5 : in std_logic; one_n_or_two : in std_logic; write_n_or_read : in std_logic; spi_sdo_opad_c : out std_logic; reset_6 : in std_logic; load_configuration_data_0 : in std_logic; write_clock_enable : in std_logic; shift_configuration_data : in std_logic); end piso_shift_register; architecture beh of piso_shift_register is signal PARALLEL_IN_SERIAL_OUT_1 : std_logic_vector (23 downto 0); signal PARALLEL_IN_SERIAL_OUT_0 : std_logic_vector (23 downto 0); signal PARALLEL_IN_SERIAL_OUT_4 : std_logic_vector (23 downto 0); signal PARALLEL_IN_SERIAL_OUT : std_logic_vector (22 downto 0); signal SPI_SDO_OPAD_C_INT_62 : std_logic ; signal UN1_LOAD_IN_1_0 : std_logic ; signal N_23 : std_logic ; signal UN1_LOAD_IN_1 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component OA21FTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component MUX2H port( Y : out std_logic; A : in std_logic; B : in std_logic; S : in std_logic ); end component; component AND2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_un1_load_in_1_0: OA21FTF port map ( Y => UN1_LOAD_IN_1_0, A => shift_configuration_data, B => write_clock_enable, C => load_configuration_data_0); \II_parallel_in_serial_out_1[23]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(23), A => PARALLEL_IN_SERIAL_OUT_0(23), B => reset_6); \II_parallel_in_serial_out_0[23]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(23), A => PARALLEL_IN_SERIAL_OUT_4(23), B => SPI_SDO_OPAD_C_INT_62, S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[23]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(23), A => PARALLEL_IN_SERIAL_OUT(22), B => write_n_or_read, S => load_configuration_data_0); \II_parallel_in_serial_out_1[22]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(22), A => N_23, B => reset_6); \II_parallel_in_serial_out_0[22]\: MUX2H port map ( Y => N_23, A => PARALLEL_IN_SERIAL_OUT_4(22), B => PARALLEL_IN_SERIAL_OUT(22), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[22]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(22), A => PARALLEL_IN_SERIAL_OUT(21), B => one_n_or_two, S => load_configuration_data_0); \II_parallel_in_serial_out_1[21]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(21), A => PARALLEL_IN_SERIAL_OUT_0(21), B => reset_6); \II_parallel_in_serial_out_0[21]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(21), A => PARALLEL_IN_SERIAL_OUT_4(21), B => PARALLEL_IN_SERIAL_OUT(21), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[21]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(21), A => PARALLEL_IN_SERIAL_OUT(20), B => mxfe_configuration_data(21), S => load_configuration_data_0); \II_parallel_in_serial_out_1[20]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(20), A => PARALLEL_IN_SERIAL_OUT_0(20), B => reset_6); \II_parallel_in_serial_out_0[20]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(20), A => PARALLEL_IN_SERIAL_OUT_4(20), B => PARALLEL_IN_SERIAL_OUT(20), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[20]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(20), A => PARALLEL_IN_SERIAL_OUT(19), B => mxfe_configuration_data(20), S => load_configuration_data_0); \II_parallel_in_serial_out_1[19]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(19), A => PARALLEL_IN_SERIAL_OUT_0(19), B => reset_6); \II_parallel_in_serial_out_0[19]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(19), A => PARALLEL_IN_SERIAL_OUT_4(19), B => PARALLEL_IN_SERIAL_OUT(19), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[19]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(19), A => PARALLEL_IN_SERIAL_OUT(18), B => mxfe_configuration_data(19), S => load_configuration_data_0); \II_parallel_in_serial_out_1[18]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(18), A => PARALLEL_IN_SERIAL_OUT_0(18), B => reset_5); \II_parallel_in_serial_out_0[18]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(18), A => PARALLEL_IN_SERIAL_OUT_4(18), B => PARALLEL_IN_SERIAL_OUT(18), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[18]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(18), A => PARALLEL_IN_SERIAL_OUT(17), B => mxfe_configuration_data(18), S => load_configuration_data_0); \II_parallel_in_serial_out_1[17]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(17), A => PARALLEL_IN_SERIAL_OUT_0(17), B => reset_5); \II_parallel_in_serial_out_0[17]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(17), A => PARALLEL_IN_SERIAL_OUT_4(17), B => PARALLEL_IN_SERIAL_OUT(17), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[17]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(17), A => PARALLEL_IN_SERIAL_OUT(16), B => mxfe_configuration_data(17), S => load_configuration_data_0); \II_parallel_in_serial_out_1[16]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(16), A => PARALLEL_IN_SERIAL_OUT_0(16), B => reset_5); \II_parallel_in_serial_out_0[16]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(16), A => PARALLEL_IN_SERIAL_OUT_4(16), B => PARALLEL_IN_SERIAL_OUT(16), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[16]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(16), A => PARALLEL_IN_SERIAL_OUT(15), B => mxfe_configuration_data(16), S => load_configuration_data_0); \II_parallel_in_serial_out_1[15]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(15), A => PARALLEL_IN_SERIAL_OUT_0(15), B => reset_5); \II_parallel_in_serial_out_0[15]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(15), A => PARALLEL_IN_SERIAL_OUT_4(15), B => PARALLEL_IN_SERIAL_OUT(15), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[15]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(15), A => PARALLEL_IN_SERIAL_OUT(14), B => mxfe_configuration_data(15), S => load_configuration_data_1); \II_parallel_in_serial_out_1[14]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(14), A => PARALLEL_IN_SERIAL_OUT_0(14), B => reset_5); \II_parallel_in_serial_out_0[14]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(14), A => PARALLEL_IN_SERIAL_OUT_4(14), B => PARALLEL_IN_SERIAL_OUT(14), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[14]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(14), A => PARALLEL_IN_SERIAL_OUT(13), B => mxfe_configuration_data(14), S => load_configuration_data_1); \II_parallel_in_serial_out_1[13]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(13), A => PARALLEL_IN_SERIAL_OUT_0(13), B => reset_5); \II_parallel_in_serial_out_0[13]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(13), A => PARALLEL_IN_SERIAL_OUT_4(13), B => PARALLEL_IN_SERIAL_OUT(13), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[13]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(13), A => PARALLEL_IN_SERIAL_OUT(12), B => mxfe_configuration_data(13), S => load_configuration_data_1); \II_parallel_in_serial_out_1[12]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(12), A => PARALLEL_IN_SERIAL_OUT_0(12), B => reset_5); \II_parallel_in_serial_out_0[12]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(12), A => PARALLEL_IN_SERIAL_OUT_4(12), B => PARALLEL_IN_SERIAL_OUT(12), S => UN1_LOAD_IN_1_0); \II_piso.parallel_in_serial_out_4[12]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(12), A => PARALLEL_IN_SERIAL_OUT(11), B => mxfe_configuration_data(12), S => load_configuration_data_1); \II_parallel_in_serial_out_1[11]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(11), A => PARALLEL_IN_SERIAL_OUT_0(11), B => reset_5); \II_parallel_in_serial_out_0[11]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(11), A => PARALLEL_IN_SERIAL_OUT_4(11), B => PARALLEL_IN_SERIAL_OUT(11), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[11]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(11), A => PARALLEL_IN_SERIAL_OUT(10), B => mxfe_configuration_data(11), S => load_configuration_data_1); \II_parallel_in_serial_out_1[10]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(10), A => PARALLEL_IN_SERIAL_OUT_0(10), B => reset_5); \II_parallel_in_serial_out_0[10]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(10), A => PARALLEL_IN_SERIAL_OUT_4(10), B => PARALLEL_IN_SERIAL_OUT(10), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[10]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(10), A => PARALLEL_IN_SERIAL_OUT(9), B => mxfe_configuration_data(10), S => load_configuration_data_1); \II_parallel_in_serial_out_1[9]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(9), A => PARALLEL_IN_SERIAL_OUT_0(9), B => reset_5); \II_parallel_in_serial_out_0[9]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(9), A => PARALLEL_IN_SERIAL_OUT_4(9), B => PARALLEL_IN_SERIAL_OUT(9), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[9]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(9), A => PARALLEL_IN_SERIAL_OUT(8), B => mxfe_configuration_data(9), S => load_configuration_data_1); \II_parallel_in_serial_out_1[8]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(8), A => PARALLEL_IN_SERIAL_OUT_0(8), B => reset_5); \II_parallel_in_serial_out_0[8]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(8), A => PARALLEL_IN_SERIAL_OUT_4(8), B => PARALLEL_IN_SERIAL_OUT(8), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[8]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(8), A => PARALLEL_IN_SERIAL_OUT(7), B => mxfe_configuration_data(8), S => load_configuration_data_1); \II_parallel_in_serial_out_1[7]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(7), A => PARALLEL_IN_SERIAL_OUT_0(7), B => reset_5); \II_parallel_in_serial_out_0[7]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(7), A => PARALLEL_IN_SERIAL_OUT_4(7), B => PARALLEL_IN_SERIAL_OUT(7), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[7]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(7), A => PARALLEL_IN_SERIAL_OUT(6), B => mxfe_configuration_data(7), S => load_configuration_data_1); \II_parallel_in_serial_out_1[6]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(6), A => PARALLEL_IN_SERIAL_OUT_0(6), B => reset_4); \II_parallel_in_serial_out_0[6]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(6), A => PARALLEL_IN_SERIAL_OUT_4(6), B => PARALLEL_IN_SERIAL_OUT(6), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[6]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(6), A => PARALLEL_IN_SERIAL_OUT(5), B => mxfe_configuration_data(6), S => load_configuration_data_1); \II_parallel_in_serial_out_1[5]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(5), A => PARALLEL_IN_SERIAL_OUT_0(5), B => reset_4); \II_parallel_in_serial_out_0[5]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(5), A => PARALLEL_IN_SERIAL_OUT_4(5), B => PARALLEL_IN_SERIAL_OUT(5), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[5]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(5), A => PARALLEL_IN_SERIAL_OUT(4), B => mxfe_configuration_data(5), S => load_configuration_data); \II_parallel_in_serial_out_1[4]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(4), A => PARALLEL_IN_SERIAL_OUT_0(4), B => reset_4); \II_parallel_in_serial_out_0[4]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(4), A => PARALLEL_IN_SERIAL_OUT_4(4), B => PARALLEL_IN_SERIAL_OUT(4), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[4]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(4), A => PARALLEL_IN_SERIAL_OUT(3), B => mxfe_configuration_data(4), S => load_configuration_data); \II_parallel_in_serial_out_1[3]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(3), A => PARALLEL_IN_SERIAL_OUT_0(3), B => reset_4); \II_parallel_in_serial_out_0[3]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(3), A => PARALLEL_IN_SERIAL_OUT_4(3), B => PARALLEL_IN_SERIAL_OUT(3), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[3]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(3), A => PARALLEL_IN_SERIAL_OUT(2), B => mxfe_configuration_data(3), S => load_configuration_data); \II_parallel_in_serial_out_1[2]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(2), A => PARALLEL_IN_SERIAL_OUT_0(2), B => reset_4); \II_parallel_in_serial_out_0[2]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(2), A => PARALLEL_IN_SERIAL_OUT_4(2), B => PARALLEL_IN_SERIAL_OUT(2), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[2]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(2), A => PARALLEL_IN_SERIAL_OUT(1), B => mxfe_configuration_data(2), S => load_configuration_data); \II_parallel_in_serial_out_1[1]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(1), A => PARALLEL_IN_SERIAL_OUT_0(1), B => reset_4); \II_parallel_in_serial_out_0[1]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(1), A => PARALLEL_IN_SERIAL_OUT_4(1), B => PARALLEL_IN_SERIAL_OUT(1), S => UN1_LOAD_IN_1); \II_piso.parallel_in_serial_out_4[1]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_4(1), A => PARALLEL_IN_SERIAL_OUT(0), B => mxfe_configuration_data(1), S => load_configuration_data); \II_parallel_in_serial_out_1[0]\: NOR2FT port map ( Y => PARALLEL_IN_SERIAL_OUT_1(0), A => PARALLEL_IN_SERIAL_OUT_0(0), B => reset_4); \II_parallel_in_serial_out_0[0]\: MUX2H port map ( Y => PARALLEL_IN_SERIAL_OUT_0(0), A => PARALLEL_IN_SERIAL_OUT_4(0), B => PARALLEL_IN_SERIAL_OUT(0), S => UN1_LOAD_IN_1); II_un1_load_in_1: OA21FTF port map ( Y => UN1_LOAD_IN_1, A => shift_configuration_data, B => write_clock_enable, C => load_configuration_data_0); \II_piso.parallel_in_serial_out_4[0]\: AND2 port map ( Y => PARALLEL_IN_SERIAL_OUT_4(0), A => load_configuration_data, B => mxfe_configuration_data(0)); \II_parallel_in_serial_out[0]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(0), CLK => mhz_20_clock_6, D => PARALLEL_IN_SERIAL_OUT_1(0)); \II_parallel_in_serial_out[1]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(1), CLK => mhz_20_clock_6, D => PARALLEL_IN_SERIAL_OUT_1(1)); \II_parallel_in_serial_out[2]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(2), CLK => mhz_20_clock_6, D => PARALLEL_IN_SERIAL_OUT_1(2)); \II_parallel_in_serial_out[3]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(3), CLK => mhz_20_clock_6, D => PARALLEL_IN_SERIAL_OUT_1(3)); \II_parallel_in_serial_out[4]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(4), CLK => mhz_20_clock_6, D => PARALLEL_IN_SERIAL_OUT_1(4)); \II_parallel_in_serial_out[5]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(5), CLK => mhz_20_clock_6, D => PARALLEL_IN_SERIAL_OUT_1(5)); \II_parallel_in_serial_out[6]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(6), CLK => mhz_20_clock_6, D => PARALLEL_IN_SERIAL_OUT_1(6)); \II_parallel_in_serial_out[7]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(7), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(7)); \II_parallel_in_serial_out[8]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(8), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(8)); \II_parallel_in_serial_out[9]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(9), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(9)); \II_parallel_in_serial_out[10]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(10), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(10)); \II_parallel_in_serial_out[11]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(11), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(11)); \II_parallel_in_serial_out[12]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(12), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(12)); \II_parallel_in_serial_out[13]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(13), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(13)); \II_parallel_in_serial_out[14]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(14), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(14)); \II_parallel_in_serial_out[15]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(15), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(15)); \II_parallel_in_serial_out[16]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(16), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(16)); \II_parallel_in_serial_out[17]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(17), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(17)); \II_parallel_in_serial_out[18]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(18), CLK => mhz_20_clock_7, D => PARALLEL_IN_SERIAL_OUT_1(18)); \II_parallel_in_serial_out[19]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(19), CLK => mhz_20_clock_8, D => PARALLEL_IN_SERIAL_OUT_1(19)); \II_parallel_in_serial_out[20]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(20), CLK => mhz_20_clock_8, D => PARALLEL_IN_SERIAL_OUT_1(20)); \II_parallel_in_serial_out[21]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(21), CLK => mhz_20_clock_8, D => PARALLEL_IN_SERIAL_OUT_1(21)); \II_parallel_in_serial_out[22]\: DFF port map ( Q => PARALLEL_IN_SERIAL_OUT(22), CLK => mhz_20_clock_8, D => PARALLEL_IN_SERIAL_OUT_1(22)); \II_parallel_in_serial_out[23]\: DFF port map ( Q => SPI_SDO_OPAD_C_INT_62, CLK => mhz_20_clock_8, D => PARALLEL_IN_SERIAL_OUT_1(23)); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); spi_sdo_opad_c <= SPI_SDO_OPAD_C_INT_62; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity sipo_shift_register is port( mxfe_register_data : out std_logic_vector (7 downto 0); mhz_20_clock_10 : in std_logic; shift_mxfe_data : in std_logic; read_clock_enable_i_0_i : in std_logic; spi_dio_ipad_c : in std_logic; reset_0 : in std_logic); end sipo_shift_register; architecture beh of sipo_shift_register is signal SERIAL_IN_PARALLEL_OUT_1 : std_logic_vector (7 downto 0); signal SERIAL_IN_PARALLEL_OUT_0 : std_logic_vector (7 downto 0); signal MXFE_REGISTER_DATA_0_INT_54 : std_logic ; signal MXFE_REGISTER_DATA_1_INT_55 : std_logic ; signal MXFE_REGISTER_DATA_2_INT_56 : std_logic ; signal MXFE_REGISTER_DATA_3_INT_57 : std_logic ; signal MXFE_REGISTER_DATA_4_INT_58 : std_logic ; signal MXFE_REGISTER_DATA_5_INT_59 : std_logic ; signal MXFE_REGISTER_DATA_6_INT_60 : std_logic ; signal MXFE_REGISTER_DATA_7_INT_61 : std_logic ; signal UN1_SHIFT_IN : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component MUX2H port( Y : out std_logic; A : in std_logic; B : in std_logic; S : in std_logic ); end component; component AND2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin \II_serial_in_parallel_out_1[7]\: NOR2FT port map ( Y => SERIAL_IN_PARALLEL_OUT_1(7), A => SERIAL_IN_PARALLEL_OUT_0(7), B => reset_0); \II_serial_in_parallel_out_0[7]\: MUX2H port map ( Y => SERIAL_IN_PARALLEL_OUT_0(7), A => MXFE_REGISTER_DATA_7_INT_61, B => MXFE_REGISTER_DATA_6_INT_60, S => UN1_SHIFT_IN); \II_serial_in_parallel_out_1[6]\: NOR2FT port map ( Y => SERIAL_IN_PARALLEL_OUT_1(6), A => SERIAL_IN_PARALLEL_OUT_0(6), B => reset_0); \II_serial_in_parallel_out_0[6]\: MUX2H port map ( Y => SERIAL_IN_PARALLEL_OUT_0(6), A => MXFE_REGISTER_DATA_6_INT_60, B => MXFE_REGISTER_DATA_5_INT_59, S => UN1_SHIFT_IN); \II_serial_in_parallel_out_1[5]\: NOR2FT port map ( Y => SERIAL_IN_PARALLEL_OUT_1(5), A => SERIAL_IN_PARALLEL_OUT_0(5), B => reset_0); \II_serial_in_parallel_out_0[5]\: MUX2H port map ( Y => SERIAL_IN_PARALLEL_OUT_0(5), A => MXFE_REGISTER_DATA_5_INT_59, B => MXFE_REGISTER_DATA_4_INT_58, S => UN1_SHIFT_IN); \II_serial_in_parallel_out_1[4]\: NOR2FT port map ( Y => SERIAL_IN_PARALLEL_OUT_1(4), A => SERIAL_IN_PARALLEL_OUT_0(4), B => reset_0); \II_serial_in_parallel_out_0[4]\: MUX2H port map ( Y => SERIAL_IN_PARALLEL_OUT_0(4), A => MXFE_REGISTER_DATA_4_INT_58, B => MXFE_REGISTER_DATA_3_INT_57, S => UN1_SHIFT_IN); \II_serial_in_parallel_out_1[3]\: NOR2FT port map ( Y => SERIAL_IN_PARALLEL_OUT_1(3), A => SERIAL_IN_PARALLEL_OUT_0(3), B => reset_0); \II_serial_in_parallel_out_0[3]\: MUX2H port map ( Y => SERIAL_IN_PARALLEL_OUT_0(3), A => MXFE_REGISTER_DATA_3_INT_57, B => MXFE_REGISTER_DATA_2_INT_56, S => UN1_SHIFT_IN); \II_serial_in_parallel_out_1[2]\: NOR2FT port map ( Y => SERIAL_IN_PARALLEL_OUT_1(2), A => SERIAL_IN_PARALLEL_OUT_0(2), B => reset_0); \II_serial_in_parallel_out_0[2]\: MUX2H port map ( Y => SERIAL_IN_PARALLEL_OUT_0(2), A => MXFE_REGISTER_DATA_2_INT_56, B => MXFE_REGISTER_DATA_1_INT_55, S => UN1_SHIFT_IN); \II_serial_in_parallel_out_1[1]\: NOR2FT port map ( Y => SERIAL_IN_PARALLEL_OUT_1(1), A => SERIAL_IN_PARALLEL_OUT_0(1), B => reset_0); \II_serial_in_parallel_out_0[1]\: MUX2H port map ( Y => SERIAL_IN_PARALLEL_OUT_0(1), A => MXFE_REGISTER_DATA_1_INT_55, B => MXFE_REGISTER_DATA_0_INT_54, S => UN1_SHIFT_IN); \II_serial_in_parallel_out_1[0]\: NOR2FT port map ( Y => SERIAL_IN_PARALLEL_OUT_1(0), A => SERIAL_IN_PARALLEL_OUT_0(0), B => reset_0); \II_serial_in_parallel_out_0[0]\: MUX2H port map ( Y => SERIAL_IN_PARALLEL_OUT_0(0), A => MXFE_REGISTER_DATA_0_INT_54, B => spi_dio_ipad_c, S => UN1_SHIFT_IN); \II_sipo.un1_shift_in\: AND2 port map ( Y => UN1_SHIFT_IN, A => read_clock_enable_i_0_i, B => shift_mxfe_data); \II_serial_in_parallel_out[0]\: DFF port map ( Q => MXFE_REGISTER_DATA_0_INT_54, CLK => mhz_20_clock_10, D => SERIAL_IN_PARALLEL_OUT_1(0)); \II_serial_in_parallel_out[1]\: DFF port map ( Q => MXFE_REGISTER_DATA_1_INT_55, CLK => mhz_20_clock_10, D => SERIAL_IN_PARALLEL_OUT_1(1)); \II_serial_in_parallel_out[2]\: DFF port map ( Q => MXFE_REGISTER_DATA_2_INT_56, CLK => mhz_20_clock_10, D => SERIAL_IN_PARALLEL_OUT_1(2)); \II_serial_in_parallel_out[3]\: DFF port map ( Q => MXFE_REGISTER_DATA_3_INT_57, CLK => mhz_20_clock_10, D => SERIAL_IN_PARALLEL_OUT_1(3)); \II_serial_in_parallel_out[4]\: DFF port map ( Q => MXFE_REGISTER_DATA_4_INT_58, CLK => mhz_20_clock_10, D => SERIAL_IN_PARALLEL_OUT_1(4)); \II_serial_in_parallel_out[5]\: DFF port map ( Q => MXFE_REGISTER_DATA_5_INT_59, CLK => mhz_20_clock_10, D => SERIAL_IN_PARALLEL_OUT_1(5)); \II_serial_in_parallel_out[6]\: DFF port map ( Q => MXFE_REGISTER_DATA_6_INT_60, CLK => mhz_20_clock_10, D => SERIAL_IN_PARALLEL_OUT_1(6)); \II_serial_in_parallel_out[7]\: DFF port map ( Q => MXFE_REGISTER_DATA_7_INT_61, CLK => mhz_20_clock_10, D => SERIAL_IN_PARALLEL_OUT_1(7)); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); mxfe_register_data(0) <= MXFE_REGISTER_DATA_0_INT_54; mxfe_register_data(1) <= MXFE_REGISTER_DATA_1_INT_55; mxfe_register_data(2) <= MXFE_REGISTER_DATA_2_INT_56; mxfe_register_data(3) <= MXFE_REGISTER_DATA_3_INT_57; mxfe_register_data(4) <= MXFE_REGISTER_DATA_4_INT_58; mxfe_register_data(5) <= MXFE_REGISTER_DATA_5_INT_59; mxfe_register_data(6) <= MXFE_REGISTER_DATA_6_INT_60; mxfe_register_data(7) <= MXFE_REGISTER_DATA_7_INT_61; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity jk_ff_1 is port( mhz_20_clock_1 : in std_logic; dac_transfer_busy : in std_logic; dac_start : in std_logic; dac_busy : out std_logic; reset_10 : in std_logic); end jk_ff_1; architecture beh of jk_ff_1 is signal DAC_BUSY_INT_1 : std_logic ; signal Q_1_0 : std_logic ; signal Q_0_0 : std_logic ; signal Q_3 : std_logic ; signal QNS7 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component MUX2H port( Y : out std_logic; A : in std_logic; B : in std_logic; S : in std_logic ); end component; component NOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component AOI21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_q_1: NOR2FT port map ( Y => Q_1_0, A => Q_0_0, B => reset_10); II_q_0: MUX2H port map ( Y => Q_0_0, A => Q_3, B => DAC_BUSY_INT_1, S => QNS7); \II_jk_next_state.qns7\: NOR2 port map ( Y => QNS7, A => dac_start, B => dac_transfer_busy); \II_ff.q_3_r\: AOI21TTF port map ( Y => Q_3, A => DAC_BUSY_INT_1, B => dac_transfer_busy, C => dac_start); II_q: DFF port map ( Q => DAC_BUSY_INT_1, CLK => mhz_20_clock_1, D => Q_1_0); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); dac_busy <= DAC_BUSY_INT_1; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity jk_ff is port( mhz_20_clock_1 : in std_logic; mxfe_start : in std_logic; configuration_busy : in std_logic; mxfe_busy : out std_logic; reset_10 : in std_logic); end jk_ff; architecture beh of jk_ff is signal MXFE_BUSY_INT_0 : std_logic ; signal Q_1 : std_logic ; signal Q_0 : std_logic ; signal Q_3 : std_logic ; signal QNS7 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component MUX2H port( Y : out std_logic; A : in std_logic; B : in std_logic; S : in std_logic ); end component; component NOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component AOI21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_q_1: NOR2FT port map ( Y => Q_1, A => Q_0, B => reset_10); II_q_0: MUX2H port map ( Y => Q_0, A => Q_3, B => MXFE_BUSY_INT_0, S => QNS7); \II_jk_next_state.qns7\: NOR2 port map ( Y => QNS7, A => configuration_busy, B => mxfe_start); \II_ff.q_3_r\: AOI21TTF port map ( Y => Q_3, A => MXFE_BUSY_INT_0, B => configuration_busy, C => mxfe_start); II_q: DFF port map ( Q => MXFE_BUSY_INT_0, CLK => mhz_20_clock_1, D => Q_1); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); mxfe_busy <= MXFE_BUSY_INT_0; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity falling_edge_detector is port( mhz_20_clock_1 : in std_logic; candidate_delayed : out std_logic; reset_10 : in std_logic; synced_wr_n : in std_logic); end falling_edge_detector; architecture beh of falling_edge_detector is signal CANDIDATE_DELAYED_0_0_A3 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_candidate_delayed_0_0_a3: NOR2FT port map ( Y => CANDIDATE_DELAYED_0_0_A3, A => synced_wr_n, B => reset_10); II_candidate_delayed: DFF port map ( Q => candidate_delayed, CLK => mhz_20_clock_1, D => CANDIDATE_DELAYED_0_0_A3); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity dual_rank_synchronizer_1 is port( mhz_20_clock_1 : in std_logic; synced_wr_n : out std_logic; reset_10 : in std_logic; wr_0_n_ipad_c : in std_logic; wr_1_n_ipad_c : in std_logic); end dual_rank_synchronizer_1; architecture beh of dual_rank_synchronizer_1 is signal RANK_1_0_0_A3_0 : std_logic ; signal RANK_2_0_0_A3_0 : std_logic ; signal RANK_1 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component NOR3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_rank_1_0_0_a3: NOR3FFT port map ( Y => RANK_1_0_0_A3_0, A => wr_1_n_ipad_c, B => wr_0_n_ipad_c, C => reset_10); II_rank_2_0_0_a3: NOR2FT port map ( Y => RANK_2_0_0_A3_0, A => RANK_1, B => reset_10); II_rank_2: DFF port map ( Q => synced_wr_n, CLK => mhz_20_clock_1, D => RANK_2_0_0_A3_0); II_rank_1: DFF port map ( Q => RANK_1, CLK => mhz_20_clock_1, D => RANK_1_0_0_A3_0); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity dual_rank_synchronizer is port( mhz_20_clock_1 : in std_logic; synced_cs_n : out std_logic; reset_10 : in std_logic; cs_n_ipad_c : in std_logic); end dual_rank_synchronizer; architecture beh of dual_rank_synchronizer is signal RANK_1_0_0_A3 : std_logic ; signal RANK_2_0_0_A3 : std_logic ; signal RANK_1 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_rank_1_0_0_a3: NOR2FT port map ( Y => RANK_1_0_0_A3, A => cs_n_ipad_c, B => reset_10); II_rank_2_0_0_a3: NOR2FT port map ( Y => RANK_2_0_0_A3, A => RANK_1, B => reset_10); II_rank_2: DFF port map ( Q => synced_cs_n, CLK => mhz_20_clock_1, D => RANK_2_0_0_A3); II_rank_1: DFF port map ( Q => RANK_1, CLK => mhz_20_clock_1, D => RANK_1_0_0_A3); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity dac_serializer is port( dac_data : in std_logic_vector (23 downto 0); dac_clock_enable : in std_logic; reset_0 : in std_logic; dac_clock_opad_c : out std_logic; mhz_20_clock_0 : in std_logic; mhz_20_clock_1 : in std_logic; dac_start : in std_logic; reset : in std_logic; dac_transfer_busy : out std_logic; dac_cs_n_opad_c : out std_logic; mhz_20_clock_13 : in std_logic; reset_3 : in std_logic; dac_data_opad_c : out std_logic; reset_2 : in std_logic; reset_1 : in std_logic; mhz_20_clock_10 : in std_logic; mhz_20_clock_11 : in std_logic; mhz_20_clock_12 : in std_logic); end dac_serializer; architecture beh of dac_serializer is signal LOAD_CONFIGURATION_DATA : std_logic ; signal LOAD_CONFIGURATION_DATA_1 : std_logic ; signal LOAD_CONFIGURATION_DATA_0 : std_logic ; signal WRITE_CLOCK_ENABLE : std_logic ; signal SHIFT_CONFIGURATION_DATA : std_logic ; signal READ_CLOCK_ENABLE : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component piso_shift_register_1 port( dac_data : in std_logic_vector(23 downto 0); mhz_20_clock_12 : in std_logic; mhz_20_clock_11 : in std_logic; mhz_20_clock_10 : in std_logic; reset_1 : in std_logic; load_configuration_data : in std_logic; reset_2 : in std_logic; load_configuration_data_1 : in std_logic; dac_data_opad_c : out std_logic; reset_3 : in std_logic; load_configuration_data_0 : in std_logic; write_clock_enable : in std_logic; shift_configuration_data : in std_logic ); end component; component dac_serializer_fsm port( mhz_20_clock_13 : in std_logic; mhz_20_clock_12 : in std_logic; dac_cs_n_opad_c : out std_logic; shift_configuration_data : out std_logic; dac_transfer_busy : out std_logic; load_configuration_data : out std_logic; write_clock_enable : in std_logic; read_clock_enable : in std_logic; reset : in std_logic; dac_start : in std_logic; reset_1 : in std_logic; mhz_20_clock_1 : in std_logic; load_configuration_data_0 : out std_logic; mhz_20_clock_0 : in std_logic; load_configuration_data_1 : out std_logic ); end component; component mxfe_clock_generator_1 port( mhz_20_clock_13 : in std_logic; shift_configuration_data : in std_logic; dac_clock_opad_c : out std_logic; reset_0 : in std_logic; write_clock_enable : out std_logic; dac_clock_enable : in std_logic; read_clock_enable : out std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_U2: piso_shift_register_1 port map ( dac_data(0) => dac_data(0), dac_data(1) => dac_data(1), dac_data(2) => dac_data(2), dac_data(3) => dac_data(3), dac_data(4) => dac_data(4), dac_data(5) => dac_data(5), dac_data(6) => dac_data(6), dac_data(7) => dac_data(7), dac_data(8) => dac_data(8), dac_data(9) => dac_data(9), dac_data(10) => dac_data(10), dac_data(11) => dac_data(11), dac_data(12) => dac_data(12), dac_data(13) => dac_data(13), dac_data(14) => dac_data(14), dac_data(15) => dac_data(15), dac_data(16) => dac_data(16), dac_data(17) => dac_data(17), dac_data(18) => dac_data(18), dac_data(19) => dac_data(19), dac_data(20) => dac_data(20), dac_data(21) => dac_data(21), dac_data(22) => dac_data(22), dac_data(23) => dac_data(23), mhz_20_clock_12 => mhz_20_clock_12, mhz_20_clock_11 => mhz_20_clock_11, mhz_20_clock_10 => mhz_20_clock_10, reset_1 => reset_1, load_configuration_data => LOAD_CONFIGURATION_DATA, reset_2 => reset_2, load_configuration_data_1 => LOAD_CONFIGURATION_DATA_1, dac_data_opad_c => dac_data_opad_c, reset_3 => reset_3, load_configuration_data_0 => LOAD_CONFIGURATION_DATA_0, write_clock_enable => WRITE_CLOCK_ENABLE, shift_configuration_data => SHIFT_CONFIGURATION_DATA); II_U3: dac_serializer_fsm port map ( mhz_20_clock_13 => mhz_20_clock_13, mhz_20_clock_12 => mhz_20_clock_12, dac_cs_n_opad_c => dac_cs_n_opad_c, shift_configuration_data => SHIFT_CONFIGURATION_DATA, dac_transfer_busy => dac_transfer_busy, load_configuration_data => LOAD_CONFIGURATION_DATA, write_clock_enable => WRITE_CLOCK_ENABLE, read_clock_enable => READ_CLOCK_ENABLE, reset => reset, dac_start => dac_start, reset_1 => reset_1, mhz_20_clock_1 => mhz_20_clock_1, load_configuration_data_0 => LOAD_CONFIGURATION_DATA_0, mhz_20_clock_0 => mhz_20_clock_0, load_configuration_data_1 => LOAD_CONFIGURATION_DATA_1); II_U4: mxfe_clock_generator_1 port map ( mhz_20_clock_13 => mhz_20_clock_13, shift_configuration_data => SHIFT_CONFIGURATION_DATA, dac_clock_opad_c => dac_clock_opad_c, reset_0 => reset_0, write_clock_enable => WRITE_CLOCK_ENABLE, dac_clock_enable => dac_clock_enable, read_clock_enable => READ_CLOCK_ENABLE); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity clock_prescalar is port( mhz_80_clock : in std_logic; mhz_20_clock_0 : out std_logic; mhz_20_clock_1 : out std_logic; mhz_20_clock_2 : out std_logic; mhz_20_clock_3 : out std_logic; mhz_20_clock_4 : out std_logic; mhz_20_clock_5 : out std_logic; mhz_20_clock_6 : out std_logic; mhz_20_clock_7 : out std_logic; mhz_20_clock_8 : out std_logic; mhz_20_clock_9 : out std_logic; mhz_20_clock_10 : out std_logic; mhz_20_clock_11 : out std_logic; mhz_20_clock_12 : out std_logic; mhz_20_clock_13 : out std_logic); end clock_prescalar; architecture beh of clock_prescalar is signal COUNTER_BITS : std_logic_vector (1 downto 0); signal COUNTER_BITS_I_0 : std_logic_vector (0 to 0); signal COUNTER_BITS_I : std_logic_vector (1 to 1); signal MHZ_20_CLOCK_1_INT_69 : std_logic ; signal MHZ_20_CLOCK_0_0 : std_logic ; signal SUM1 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component BFR port( Y : out std_logic; A : in std_logic ); end component; component INV port( Y : out std_logic; A : in std_logic ); end component; component XOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin \II_counter_bits_inferred_clock_0_0[1]\: BFR port map ( Y => MHZ_20_CLOCK_0_0, A => COUNTER_BITS(1)); \II_counter_bits_inferred_clock_13[1]\: BFR port map ( Y => mhz_20_clock_13, A => MHZ_20_CLOCK_0_0); \II_counter_bits_inferred_clock_12[1]\: BFR port map ( Y => mhz_20_clock_12, A => MHZ_20_CLOCK_0_0); \II_counter_bits_inferred_clock_11[1]\: BFR port map ( Y => mhz_20_clock_11, A => MHZ_20_CLOCK_0_0); \II_counter_bits_inferred_clock_10[1]\: BFR port map ( Y => mhz_20_clock_10, A => MHZ_20_CLOCK_0_0); \II_counter_bits_inferred_clock_9[1]\: BFR port map ( Y => mhz_20_clock_9, A => MHZ_20_CLOCK_0_0); \II_counter_bits_inferred_clock_8[1]\: BFR port map ( Y => mhz_20_clock_8, A => MHZ_20_CLOCK_0_0); \II_counter_bits_inferred_clock_7[1]\: BFR port map ( Y => mhz_20_clock_7, A => MHZ_20_CLOCK_0_0); \II_counter_bits_inferred_clock_6[1]\: BFR port map ( Y => mhz_20_clock_6, A => COUNTER_BITS(1)); \II_counter_bits_inferred_clock_5[1]\: BFR port map ( Y => mhz_20_clock_5, A => COUNTER_BITS(1)); \II_counter_bits_inferred_clock_4[1]\: BFR port map ( Y => mhz_20_clock_4, A => COUNTER_BITS(1)); \II_counter_bits_inferred_clock_3[1]\: BFR port map ( Y => mhz_20_clock_3, A => COUNTER_BITS(1)); \II_counter_bits_inferred_clock_2[1]\: BFR port map ( Y => mhz_20_clock_2, A => COUNTER_BITS(1)); \II_counter_bits_inferred_clock_1[1]\: BFR port map ( Y => MHZ_20_CLOCK_1_INT_69, A => COUNTER_BITS(1)); \II_counter_bits_inferred_clock_0[1]\: BFR port map ( Y => mhz_20_clock_0, A => COUNTER_BITS(1)); \II_counter_bits_i[0]\: INV port map ( Y => COUNTER_BITS_I_0(0), A => COUNTER_BITS(0)); \II_un2_counter_bits_1.SUM1\: XOR2 port map ( Y => SUM1, A => COUNTER_BITS(0), B => MHZ_20_CLOCK_1_INT_69); \II_counter_bits[0]\: DFF port map ( Q => COUNTER_BITS(0), CLK => mhz_80_clock, D => COUNTER_BITS_I_0(0)); \II_counter_bits[1]\: DFF port map ( Q => COUNTER_BITS_I(1), CLK => mhz_80_clock, D => SUM1); COUNTER_BITS(1) <= COUNTER_BITS_I(1); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); mhz_20_clock_1 <= MHZ_20_CLOCK_1_INT_69; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity mxfe_configurator is port( mxfe_configuration_data : in std_logic_vector (21 downto 0); mxfe_register_data : out std_logic_vector (7 downto 0); dac_clock_enable : in std_logic; reset_1 : in std_logic; spi_clock_opad_c : out std_logic; mhz_20_clock_1 : in std_logic; reset : in std_logic; mxfe_start : in std_logic; reset_3 : in std_logic; configuration_busy : out std_logic; spi_cs_n_opad_c : out std_logic; mhz_20_clock_9 : in std_logic; reset_6 : in std_logic; spi_sdo_opad_c : out std_logic; write_n_or_read : in std_logic; one_n_or_two : in std_logic; reset_5 : in std_logic; reset_4 : in std_logic; mhz_20_clock_6 : in std_logic; mhz_20_clock_7 : in std_logic; mhz_20_clock_8 : in std_logic; reset_0 : in std_logic; spi_dio_ipad_c : in std_logic; mhz_20_clock_10 : in std_logic); end mxfe_configurator; architecture beh of mxfe_configurator is signal SHIFT_MXFE_DATA : std_logic ; signal READ_CLOCK_ENABLE_I_0_I : std_logic ; signal LOAD_CONFIGURATION_DATA : std_logic ; signal LOAD_CONFIGURATION_DATA_1 : std_logic ; signal LOAD_CONFIGURATION_DATA_0 : std_logic ; signal WRITE_CLOCK_ENABLE : std_logic ; signal SHIFT_CONFIGURATION_DATA : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component sipo_shift_register port( mxfe_register_data : out std_logic_vector(7 downto 0); mhz_20_clock_10 : in std_logic; shift_mxfe_data : in std_logic; read_clock_enable_i_0_i : in std_logic; spi_dio_ipad_c : in std_logic; reset_0 : in std_logic ); end component; component piso_shift_register port( mxfe_configuration_data : in std_logic_vector(21 downto 0); mhz_20_clock_8 : in std_logic; mhz_20_clock_7 : in std_logic; mhz_20_clock_6 : in std_logic; load_configuration_data : in std_logic; reset_4 : in std_logic; load_configuration_data_1 : in std_logic; reset_5 : in std_logic; one_n_or_two : in std_logic; write_n_or_read : in std_logic; spi_sdo_opad_c : out std_logic; reset_6 : in std_logic; load_configuration_data_0 : in std_logic; write_clock_enable : in std_logic; shift_configuration_data : in std_logic ); end component; component mxfe_serializer_fsm port( mhz_20_clock_9 : in std_logic; mhz_20_clock_8 : in std_logic; spi_cs_n_opad_c : out std_logic; shift_configuration_data : out std_logic; configuration_busy : out std_logic; shift_mxfe_data : out std_logic; reset_3 : in std_logic; load_configuration_data : out std_logic; reset_4 : in std_logic; write_clock_enable : in std_logic; mxfe_start : in std_logic; read_clock_enable_i_0_i : in std_logic; one_n_or_two : in std_logic; reset : in std_logic; write_n_or_read : in std_logic; load_configuration_data_0 : out std_logic; mhz_20_clock_1 : in std_logic; load_configuration_data_1 : out std_logic ); end component; component mxfe_clock_generator port( mhz_20_clock_9 : in std_logic; read_clock_enable_i_0_i : out std_logic; reset_0 : in std_logic; shift_configuration_data : in std_logic; spi_clock_opad_c : out std_logic; reset_1 : in std_logic; dac_clock_enable : in std_logic; write_clock_enable : out std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_U1: sipo_shift_register port map ( mxfe_register_data(0) => mxfe_register_data(0), mxfe_register_data(1) => mxfe_register_data(1), mxfe_register_data(2) => mxfe_register_data(2), mxfe_register_data(3) => mxfe_register_data(3), mxfe_register_data(4) => mxfe_register_data(4), mxfe_register_data(5) => mxfe_register_data(5), mxfe_register_data(6) => mxfe_register_data(6), mxfe_register_data(7) => mxfe_register_data(7), mhz_20_clock_10 => mhz_20_clock_10, shift_mxfe_data => SHIFT_MXFE_DATA, read_clock_enable_i_0_i => READ_CLOCK_ENABLE_I_0_I, spi_dio_ipad_c => spi_dio_ipad_c, reset_0 => reset_0); II_U2: piso_shift_register port map ( mxfe_configuration_data(0) => mxfe_configuration_data(0), mxfe_configuration_data(1) => mxfe_configuration_data(1), mxfe_configuration_data(2) => mxfe_configuration_data(2), mxfe_configuration_data(3) => mxfe_configuration_data(3), mxfe_configuration_data(4) => mxfe_configuration_data(4), mxfe_configuration_data(5) => mxfe_configuration_data(5), mxfe_configuration_data(6) => mxfe_configuration_data(6), mxfe_configuration_data(7) => mxfe_configuration_data(7), mxfe_configuration_data(8) => mxfe_configuration_data(8), mxfe_configuration_data(9) => mxfe_configuration_data(9), mxfe_configuration_data(10) => mxfe_configuration_data(10), mxfe_configuration_data(11) => mxfe_configuration_data(11), mxfe_configuration_data(12) => mxfe_configuration_data(12), mxfe_configuration_data(13) => mxfe_configuration_data(13), mxfe_configuration_data(14) => mxfe_configuration_data(14), mxfe_configuration_data(15) => mxfe_configuration_data(15), mxfe_configuration_data(16) => mxfe_configuration_data(16), mxfe_configuration_data(17) => mxfe_configuration_data(17), mxfe_configuration_data(18) => mxfe_configuration_data(18), mxfe_configuration_data(19) => mxfe_configuration_data(19), mxfe_configuration_data(20) => mxfe_configuration_data(20), mxfe_configuration_data(21) => mxfe_configuration_data(21), mhz_20_clock_8 => mhz_20_clock_8, mhz_20_clock_7 => mhz_20_clock_7, mhz_20_clock_6 => mhz_20_clock_6, load_configuration_data => LOAD_CONFIGURATION_DATA, reset_4 => reset_4, load_configuration_data_1 => LOAD_CONFIGURATION_DATA_1, reset_5 => reset_5, one_n_or_two => one_n_or_two, write_n_or_read => write_n_or_read, spi_sdo_opad_c => spi_sdo_opad_c, reset_6 => reset_6, load_configuration_data_0 => LOAD_CONFIGURATION_DATA_0, write_clock_enable => WRITE_CLOCK_ENABLE, shift_configuration_data => SHIFT_CONFIGURATION_DATA); II_U3: mxfe_serializer_fsm port map ( mhz_20_clock_9 => mhz_20_clock_9, mhz_20_clock_8 => mhz_20_clock_8, spi_cs_n_opad_c => spi_cs_n_opad_c, shift_configuration_data => SHIFT_CONFIGURATION_DATA, configuration_busy => configuration_busy, shift_mxfe_data => SHIFT_MXFE_DATA, reset_3 => reset_3, load_configuration_data => LOAD_CONFIGURATION_DATA, reset_4 => reset_4, write_clock_enable => WRITE_CLOCK_ENABLE, mxfe_start => mxfe_start, read_clock_enable_i_0_i => READ_CLOCK_ENABLE_I_0_I, one_n_or_two => one_n_or_two, reset => reset, write_n_or_read => write_n_or_read, load_configuration_data_0 => LOAD_CONFIGURATION_DATA_0, mhz_20_clock_1 => mhz_20_clock_1, load_configuration_data_1 => LOAD_CONFIGURATION_DATA_1); II_U4: mxfe_clock_generator port map ( mhz_20_clock_9 => mhz_20_clock_9, read_clock_enable_i_0_i => READ_CLOCK_ENABLE_I_0_I, reset_0 => reset_0, shift_configuration_data => SHIFT_CONFIGURATION_DATA, spi_clock_opad_c => spi_clock_opad_c, reset_1 => reset_1, dac_clock_enable => dac_clock_enable, write_clock_enable => WRITE_CLOCK_ENABLE); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity reset_synchronizer is port( reset : out std_logic; mhz_20_clock_6 : in std_logic; reset_0 : out std_logic; reset_1 : out std_logic; reset_2 : out std_logic; reset_3 : out std_logic; reset_4 : out std_logic; reset_5 : out std_logic; reset_6 : out std_logic; reset_7 : out std_logic; reset_8 : out std_logic; reset_9 : out std_logic; mhz_20_clock_0 : in std_logic; reset_10 : out std_logic; async_reset_n_ipad_c : in std_logic); end reset_synchronizer; architecture beh of reset_synchronizer is signal ASYNC_RESET_N_IPAD_C_I_0_0 : std_logic ; signal RESET_FF : std_logic ; signal ASYNC_RESET_N_IPAD_C_I_0 : std_logic ; signal NN_1 : std_logic ; signal VCC : std_logic ; component INV port( Y : out std_logic; A : in std_logic ); end component; component DFFS port( Q : out std_logic; SET : in std_logic; CLK : in std_logic; D : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_sync_reset_out_i_0: INV port map ( Y => ASYNC_RESET_N_IPAD_C_I_0_0, A => async_reset_n_ipad_c); II_sync_reset_out_10: DFFS port map ( Q => reset_10, SET => ASYNC_RESET_N_IPAD_C_I_0_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_9: DFFS port map ( Q => reset_9, SET => ASYNC_RESET_N_IPAD_C_I_0_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_8: DFFS port map ( Q => reset_8, SET => ASYNC_RESET_N_IPAD_C_I_0_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_7: DFFS port map ( Q => reset_7, SET => ASYNC_RESET_N_IPAD_C_I_0_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_6: DFFS port map ( Q => reset_6, SET => ASYNC_RESET_N_IPAD_C_I_0_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_5: DFFS port map ( Q => reset_5, SET => ASYNC_RESET_N_IPAD_C_I_0_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_4: DFFS port map ( Q => reset_4, SET => ASYNC_RESET_N_IPAD_C_I_0_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_3: DFFS port map ( Q => reset_3, SET => ASYNC_RESET_N_IPAD_C_I_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_2: DFFS port map ( Q => reset_2, SET => ASYNC_RESET_N_IPAD_C_I_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_1: DFFS port map ( Q => reset_1, SET => ASYNC_RESET_N_IPAD_C_I_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_0: DFFS port map ( Q => reset_0, SET => ASYNC_RESET_N_IPAD_C_I_0, CLK => mhz_20_clock_0, D => RESET_FF); II_sync_reset_out_i: INV port map ( Y => ASYNC_RESET_N_IPAD_C_I_0, A => async_reset_n_ipad_c); II_reset_ff: DFFS port map ( Q => RESET_FF, SET => ASYNC_RESET_N_IPAD_C_I_0, CLK => mhz_20_clock_6, D => NN_1); II_sync_reset_out: DFFS port map ( Q => reset, SET => ASYNC_RESET_N_IPAD_C_I_0, CLK => mhz_20_clock_6, D => RESET_FF); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity registers is port( address_ipads_c_i_0_i_14 : in std_logic; address_ipads_c_i_0_i_12 : in std_logic; address_ipads_c_i_0_i_10 : in std_logic; address_ipads_c_i_0_i_8 : in std_logic; address_ipads_c_i_0_i_0 : in std_logic; address_ipads_c_14 : in std_logic; address_ipads_c_12 : in std_logic; address_ipads_c_10 : in std_logic; address_ipads_c_8 : in std_logic; address_ipads_c_0 : in std_logic; address_ipads_c_4 : in std_logic; address_ipads_c_2 : in std_logic; address_ipads_c_1 : in std_logic; address_ipads_c_6 : in std_logic; address_ipads_c_5 : in std_logic; address_ipads_c_3 : in std_logic; mxfe_register_data : in std_logic_vector (7 downto 0); data_out_0 : out std_logic; data_out_1 : out std_logic; data_out_2 : out std_logic; data_out_3 : out std_logic; data_out_4 : out std_logic; data_out_5 : out std_logic; data_out_6 : out std_logic; data_out_7 : out std_logic; data_out_8 : out std_logic; data_out_9 : out std_logic; data_out_10 : out std_logic; data_out_11 : out std_logic; data_out_12 : out std_logic; data_out_13 : out std_logic; data_out_15 : out std_logic; data_out_0_iv_i : out std_logic_vector (14 downto 14); mxfe_configuration_data : out std_logic_vector (21 downto 0); data_iopads_in : in std_logic_vector (15 downto 0); dac_data : out std_logic_vector (23 downto 0); dac_transfer_busy : in std_logic; configuration_busy : in std_logic; wr_1_n_ipad_c : in std_logic; wr_0_n_ipad_c : in std_logic; mhz_20_clock_6 : in std_logic; mhz_20_clock_5 : in std_logic; mhz_20_clock_4 : in std_logic; mhz_20_clock_3 : in std_logic; mhz_20_clock_2 : in std_logic; mhz_20_clock_1 : in std_logic; cs_n_ipad_c : in std_logic; rd_n_ipad_c : in std_logic; synced_cs_n : out std_logic; mxfe_start : out std_logic; reset_0 : in std_logic; dac_clock_enable : out std_logic; reset_6 : in std_logic; dac_start : out std_logic; one_n_or_two : out std_logic; write_n_or_read : out std_logic; reset_7 : in std_logic; reset_8 : in std_logic; reset_9 : in std_logic; reset_10 : in std_logic); end registers; architecture beh of registers is signal DAC_DATA_REGISTER_1_0_A3 : std_logic_vector (15 downto 0); signal DAC_DATA_REGISTER_0 : std_logic_vector (15 downto 0); signal MXFE_REGISTER_2_1_0_A3 : std_logic_vector (7 downto 0); signal MXFE_REGISTER_2_0 : std_logic_vector (7 downto 0); signal MXFE_REGISTER_1_1_0_A3 : std_logic_vector (7 downto 0); signal MXFE_REGISTER_1_0 : std_logic_vector (7 downto 1); signal MXFE_INSTRUCTION_REGISTER_1_0_A3 : std_logic_vector (7 downto 0); signal MXFE_INSTRUCTION_REGISTER_0 : std_logic_vector (7 downto 0); signal DAC_COMMAND_REGISTER_1_0_A3 : std_logic_vector (7 downto 0); signal DAC_COMMAND_REGISTER_0 : std_logic_vector (7 downto 0); signal CLOCK_DIVIDER_COUNTER_3_I : std_logic_vector (3 downto 0); signal CLOCK_DIVIDER_COUNTER_3_I_O3 : std_logic_vector (0 to 0); signal CLOCK_DIVIDER_COUNTER : std_logic_vector (3 downto 0); signal DATA_OUT_0_IV_I_O3 : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A3 : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_0 : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A3_0 : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A2 : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A2_1 : std_logic_vector (14 to 14); signal DATA_OUT_CNST_M : std_logic_vector (0 to 0); signal DAC_DATA_REGISTER_M : std_logic_vector (7 downto 2); signal DATA_OUT_0_IV_2_I : std_logic_vector (7 downto 1); signal DATA_OUT_0_IV_1 : std_logic_vector (7 downto 1); signal DATA_OUT_0_IV_0 : std_logic_vector (7 downto 1); signal MXFE_REGISTER_2_M : std_logic_vector (7 downto 0); signal DAC_DATA_REGISTER_M_I : std_logic_vector (6 downto 0); signal DATA_OUT_0_IV_2 : std_logic_vector (4 to 4); signal DATA_OUT_0_IV_I_A2_2 : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A3_0_1_I : std_logic_vector (14 to 14); signal DATA_OUT_IV_4_I : std_logic_vector (0 to 0); signal DATA_OUT_IV_2_I : std_logic_vector (0 to 0); signal DATA_OUT_IV_1 : std_logic_vector (0 to 0); signal DATA_OUT_IV_0 : std_logic_vector (0 to 0); signal DATA_OUT_0_IV_I_A2_6 : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A2_3 : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A2_0_6_I : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A2_0_4_I : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A2_0_2_I : std_logic_vector (14 to 14); signal DATA_OUT_0_IV_I_A2_0_0_I : std_logic_vector (14 to 14); signal MXFE_CONFIGURATION_DATA_0_INT_2 : std_logic ; signal MXFE_CONFIGURATION_DATA_1_INT_3 : std_logic ; signal MXFE_CONFIGURATION_DATA_2_INT_4 : std_logic ; signal MXFE_CONFIGURATION_DATA_3_INT_5 : std_logic ; signal MXFE_CONFIGURATION_DATA_4_INT_6 : std_logic ; signal MXFE_CONFIGURATION_DATA_5_INT_7 : std_logic ; signal MXFE_CONFIGURATION_DATA_6_INT_8 : std_logic ; signal MXFE_CONFIGURATION_DATA_7_INT_9 : std_logic ; signal MXFE_CONFIGURATION_DATA_8_INT_10 : std_logic ; signal MXFE_CONFIGURATION_DATA_9_INT_11 : std_logic ; signal MXFE_CONFIGURATION_DATA_10_INT_12 : std_logic ; signal MXFE_CONFIGURATION_DATA_11_INT_13 : std_logic ; signal MXFE_CONFIGURATION_DATA_12_INT_14 : std_logic ; signal MXFE_CONFIGURATION_DATA_13_INT_15 : std_logic ; signal MXFE_CONFIGURATION_DATA_14_INT_16 : std_logic ; signal MXFE_CONFIGURATION_DATA_15_INT_17 : std_logic ; signal MXFE_CONFIGURATION_DATA_16_INT_18 : std_logic ; signal MXFE_CONFIGURATION_DATA_17_INT_19 : std_logic ; signal MXFE_CONFIGURATION_DATA_18_INT_20 : std_logic ; signal MXFE_CONFIGURATION_DATA_19_INT_21 : std_logic ; signal MXFE_CONFIGURATION_DATA_20_INT_22 : std_logic ; signal MXFE_CONFIGURATION_DATA_21_INT_23 : std_logic ; signal DAC_DATA_0_INT_24 : std_logic ; signal DAC_DATA_1_INT_25 : std_logic ; signal DAC_DATA_2_INT_26 : std_logic ; signal DAC_DATA_3_INT_27 : std_logic ; signal DAC_DATA_4_INT_28 : std_logic ; signal DAC_DATA_5_INT_29 : std_logic ; signal DAC_DATA_6_INT_30 : std_logic ; signal DAC_DATA_7_INT_31 : std_logic ; signal DAC_DATA_8_INT_32 : std_logic ; signal DAC_DATA_9_INT_33 : std_logic ; signal DAC_DATA_10_INT_34 : std_logic ; signal DAC_DATA_11_INT_35 : std_logic ; signal DAC_DATA_12_INT_36 : std_logic ; signal DAC_DATA_13_INT_37 : std_logic ; signal DAC_DATA_14_INT_38 : std_logic ; signal DAC_DATA_15_INT_39 : std_logic ; signal DAC_DATA_16_INT_40 : std_logic ; signal DAC_DATA_17_INT_41 : std_logic ; signal DAC_DATA_18_INT_42 : std_logic ; signal DAC_DATA_19_INT_43 : std_logic ; signal DAC_DATA_20_INT_44 : std_logic ; signal DAC_DATA_21_INT_45 : std_logic ; signal DAC_DATA_22_INT_46 : std_logic ; signal DAC_DATA_23_INT_47 : std_logic ; signal SYNCED_CS_N_INT_48 : std_logic ; signal MXFE_START_INT_49 : std_logic ; signal DAC_CLOCK_ENABLE_INT_50 : std_logic ; signal DAC_START_INT_51 : std_logic ; signal ONE_N_OR_TWO_INT_52 : std_logic ; signal WRITE_N_OR_READ_INT_53 : std_logic ; signal DATA_OUT_6_SQMUXA_0 : std_logic ; signal N_297_1 : std_logic ; signal UN1_DATA_OUT_0_SQMUXA_I_I_A2 : std_logic ; signal N_297_0 : std_logic ; signal UN3_MXFE_START_0_A2_0 : std_logic ; signal N_13 : std_logic ; signal UN1_SYNCED_CS_N_6_I_A3 : std_logic ; signal N_10 : std_logic ; signal UN1_SYNCED_CS_N_7_I_A3 : std_logic ; signal N_29 : std_logic ; signal UN3_DAC_START_0_A2_0 : std_logic ; signal DATA_OUT_2_SQMUXA_0_A2 : std_logic ; signal UN1_SYNCED_CS_N_8_I_A3 : std_logic ; signal N_37 : std_logic ; signal N_31 : std_logic ; signal UN1_SYNCED_CS_N_9_I_A3 : std_logic ; signal N_45 : std_logic ; signal UN3_MXFE_START_0_A2 : std_logic ; signal N_50 : std_logic ; signal I_13 : std_logic ; signal I_9 : std_logic ; signal I_5 : std_logic ; signal UN3_MXFE_START_0_A2_1 : std_logic ; signal UN3_DAC_START_0_A2 : std_logic ; signal DATA_OUT_1_SQMUXA_0_A2 : std_logic ; signal SYNCED_WR_N : std_logic ; signal CANDIDATE_DELAYED : std_logic ; signal UN4_RESET_CLOCK_DIVIDER_COUNTER_0_A3_0 : std_logic ; signal N_150_I_0 : std_logic ; signal DATA_OUT_1_SQMUXA : std_logic ; signal DATA_OUT_2_SQMUXA : std_logic ; signal DATA_OUT_4_SQMUXA : std_logic ; signal DATA_OUT_3_SQMUXA : std_logic ; signal DATA_OUT_6_SQMUXA : std_logic ; signal N_392_I : std_logic ; signal DAC_BUSY_M_I : std_logic ; signal MXFE_BUSY_M_I : std_logic ; signal DATA_OUT_3_SQMUXA_1 : std_logic ; signal DATA_OUT_4_SQMUXA_0_A2 : std_logic ; signal DATA_OUT_4_SQMUXA_0_A3_0 : std_logic ; signal MXFE_BUSY : std_logic ; signal N_364_I_0 : std_logic ; signal DAC_BUSY : std_logic ; signal N_7 : std_logic ; signal N_4 : std_logic ; signal VCC : std_logic ; signal NN_1 : std_logic ; component NOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component MUX2H port( Y : out std_logic; A : in std_logic; B : in std_logic; S : in std_logic ); end component; component AND2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR3 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NAND3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NAND3FTT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AND2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component AO21 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OR3FTT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AO21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component AOI21TTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NAND2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component OR3 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NAND3 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OR2FT port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component NOR3FFT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component NOR3FTT port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component OA21FTF port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component INV port( Y : out std_logic; A : in std_logic ); end component; component DFF port( Q : out std_logic; CLK : in std_logic; D : in std_logic ); end component; component XOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component AND3 port( Y : out std_logic; A : in std_logic; B : in std_logic; C : in std_logic ); end component; component dual_rank_synchronizer port( mhz_20_clock_1 : in std_logic; synced_cs_n : out std_logic; reset_10 : in std_logic; cs_n_ipad_c : in std_logic ); end component; component dual_rank_synchronizer_1 port( mhz_20_clock_1 : in std_logic; synced_wr_n : out std_logic; reset_10 : in std_logic; wr_0_n_ipad_c : in std_logic; wr_1_n_ipad_c : in std_logic ); end component; component falling_edge_detector port( mhz_20_clock_1 : in std_logic; candidate_delayed : out std_logic; reset_10 : in std_logic; synced_wr_n : in std_logic ); end component; component jk_ff port( mhz_20_clock_1 : in std_logic; mxfe_start : in std_logic; configuration_busy : in std_logic; mxfe_busy : out std_logic; reset_10 : in std_logic ); end component; component jk_ff_1 port( mhz_20_clock_1 : in std_logic; dac_transfer_busy : in std_logic; dac_start : in std_logic; dac_busy : out std_logic; reset_10 : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin II_data_out_6_sqmuxa_0_a3_0: NOR2 port map ( Y => DATA_OUT_6_SQMUXA_0, A => N_297_1, B => UN1_DATA_OUT_0_SQMUXA_I_I_A2); II_un1_synced_cs_n_6_i_a3_0: NOR2 port map ( Y => N_297_0, A => UN3_MXFE_START_0_A2_0, B => N_297_1); \II_dac_data_register_1_0_a3[15]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(15), A => DAC_DATA_REGISTER_0(15), B => reset_10); \II_dac_data_register_0[15]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(15), A => DAC_DATA_15_INT_39, B => data_iopads_in(15), S => N_297_0); \II_dac_data_register_1_0_a3[14]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(14), A => DAC_DATA_REGISTER_0(14), B => reset_10); \II_dac_data_register_0[14]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(14), A => DAC_DATA_14_INT_38, B => data_iopads_in(14), S => N_297_0); \II_dac_data_register_1_0_a3[13]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(13), A => DAC_DATA_REGISTER_0(13), B => reset_10); \II_dac_data_register_0[13]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(13), A => DAC_DATA_13_INT_37, B => data_iopads_in(13), S => N_297_0); \II_dac_data_register_1_0_a3[12]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(12), A => DAC_DATA_REGISTER_0(12), B => reset_10); \II_dac_data_register_0[12]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(12), A => DAC_DATA_12_INT_36, B => data_iopads_in(12), S => N_297_0); \II_dac_data_register_1_0_a3[11]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(11), A => DAC_DATA_REGISTER_0(11), B => reset_10); \II_dac_data_register_0[11]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(11), A => DAC_DATA_11_INT_35, B => data_iopads_in(11), S => N_297_0); \II_dac_data_register_1_0_a3[10]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(10), A => DAC_DATA_REGISTER_0(10), B => reset_9); \II_dac_data_register_0[10]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(10), A => DAC_DATA_10_INT_34, B => data_iopads_in(10), S => N_297_0); \II_dac_data_register_1_0_a3[9]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(9), A => DAC_DATA_REGISTER_0(9), B => reset_9); \II_dac_data_register_0[9]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(9), A => DAC_DATA_9_INT_33, B => data_iopads_in(9), S => N_297_0); \II_dac_data_register_1_0_a3[8]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(8), A => DAC_DATA_REGISTER_0(8), B => reset_9); \II_dac_data_register_0[8]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(8), A => DAC_DATA_8_INT_32, B => data_iopads_in(8), S => N_297_0); \II_dac_data_register_1_0_a3[7]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(7), A => DAC_DATA_REGISTER_0(7), B => reset_9); \II_dac_data_register_0[7]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(7), A => DAC_DATA_7_INT_31, B => data_iopads_in(7), S => N_297_0); \II_dac_data_register_1_0_a3[6]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(6), A => N_13, B => reset_9); \II_dac_data_register_0[6]\: MUX2H port map ( Y => N_13, A => DAC_DATA_6_INT_30, B => data_iopads_in(6), S => UN1_SYNCED_CS_N_6_I_A3); \II_dac_data_register_1_0_a3[5]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(5), A => DAC_DATA_REGISTER_0(5), B => reset_9); \II_dac_data_register_0[5]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(5), A => DAC_DATA_5_INT_29, B => data_iopads_in(5), S => UN1_SYNCED_CS_N_6_I_A3); \II_dac_data_register_1_0_a3[4]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(4), A => DAC_DATA_REGISTER_0(4), B => reset_9); \II_dac_data_register_0[4]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(4), A => DAC_DATA_4_INT_28, B => data_iopads_in(4), S => UN1_SYNCED_CS_N_6_I_A3); \II_dac_data_register_1_0_a3[3]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(3), A => N_10, B => reset_9); \II_dac_data_register_0[3]\: MUX2H port map ( Y => N_10, A => DAC_DATA_3_INT_27, B => data_iopads_in(3), S => UN1_SYNCED_CS_N_6_I_A3); \II_dac_data_register_1_0_a3[2]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(2), A => DAC_DATA_REGISTER_0(2), B => reset_9); \II_dac_data_register_0[2]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(2), A => DAC_DATA_2_INT_26, B => data_iopads_in(2), S => UN1_SYNCED_CS_N_6_I_A3); \II_dac_data_register_1_0_a3[1]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(1), A => DAC_DATA_REGISTER_0(1), B => reset_9); \II_dac_data_register_0[1]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(1), A => DAC_DATA_1_INT_25, B => data_iopads_in(1), S => UN1_SYNCED_CS_N_6_I_A3); \II_dac_data_register_1_0_a3[0]\: NOR2FT port map ( Y => DAC_DATA_REGISTER_1_0_A3(0), A => DAC_DATA_REGISTER_0(0), B => reset_9); \II_dac_data_register_0[0]\: MUX2H port map ( Y => DAC_DATA_REGISTER_0(0), A => DAC_DATA_0_INT_24, B => data_iopads_in(0), S => UN1_SYNCED_CS_N_6_I_A3); II_un1_synced_cs_n_6_i_a3: NOR2 port map ( Y => UN1_SYNCED_CS_N_6_I_A3, A => UN3_MXFE_START_0_A2_0, B => N_297_1); \II_mxfe_register_2_1_0_a3[7]\: NOR2FT port map ( Y => MXFE_REGISTER_2_1_0_A3(7), A => MXFE_REGISTER_2_0(7), B => reset_9); \II_mxfe_register_2_0[7]\: MUX2H port map ( Y => MXFE_REGISTER_2_0(7), A => MXFE_CONFIGURATION_DATA_7_INT_9, B => data_iopads_in(7), S => UN1_SYNCED_CS_N_7_I_A3); \II_mxfe_register_2_1_0_a3[6]\: NOR2FT port map ( Y => MXFE_REGISTER_2_1_0_A3(6), A => N_29, B => reset_8); \II_mxfe_register_2_0[6]\: MUX2H port map ( Y => N_29, A => MXFE_CONFIGURATION_DATA_6_INT_8, B => data_iopads_in(6), S => UN1_SYNCED_CS_N_7_I_A3); \II_mxfe_register_2_1_0_a3[5]\: NOR2FT port map ( Y => MXFE_REGISTER_2_1_0_A3(5), A => MXFE_REGISTER_2_0(5), B => reset_8); \II_mxfe_register_2_0[5]\: MUX2H port map ( Y => MXFE_REGISTER_2_0(5), A => MXFE_CONFIGURATION_DATA_5_INT_7, B => data_iopads_in(5), S => UN1_SYNCED_CS_N_7_I_A3); \II_mxfe_register_2_1_0_a3[4]\: NOR2FT port map ( Y => MXFE_REGISTER_2_1_0_A3(4), A => MXFE_REGISTER_2_0(4), B => reset_8); \II_mxfe_register_2_0[4]\: MUX2H port map ( Y => MXFE_REGISTER_2_0(4), A => MXFE_CONFIGURATION_DATA_4_INT_6, B => data_iopads_in(4), S => UN1_SYNCED_CS_N_7_I_A3); \II_mxfe_register_2_1_0_a3[3]\: NOR2FT port map ( Y => MXFE_REGISTER_2_1_0_A3(3), A => MXFE_REGISTER_2_0(3), B => reset_8); \II_mxfe_register_2_0[3]\: MUX2H port map ( Y => MXFE_REGISTER_2_0(3), A => MXFE_CONFIGURATION_DATA_3_INT_5, B => data_iopads_in(3), S => UN1_SYNCED_CS_N_7_I_A3); \II_mxfe_register_2_1_0_a3[2]\: NOR2FT port map ( Y => MXFE_REGISTER_2_1_0_A3(2), A => MXFE_REGISTER_2_0(2), B => reset_8); \II_mxfe_register_2_0[2]\: MUX2H port map ( Y => MXFE_REGISTER_2_0(2), A => MXFE_CONFIGURATION_DATA_2_INT_4, B => data_iopads_in(2), S => UN1_SYNCED_CS_N_7_I_A3); \II_mxfe_register_2_1_0_a3[1]\: NOR2FT port map ( Y => MXFE_REGISTER_2_1_0_A3(1), A => MXFE_REGISTER_2_0(1), B => reset_8); \II_mxfe_register_2_0[1]\: MUX2H port map ( Y => MXFE_REGISTER_2_0(1), A => MXFE_CONFIGURATION_DATA_1_INT_3, B => data_iopads_in(1), S => UN1_SYNCED_CS_N_7_I_A3); \II_mxfe_register_2_1_0_a3[0]\: NOR2FT port map ( Y => MXFE_REGISTER_2_1_0_A3(0), A => MXFE_REGISTER_2_0(0), B => reset_8); \II_mxfe_register_2_0[0]\: MUX2H port map ( Y => MXFE_REGISTER_2_0(0), A => MXFE_CONFIGURATION_DATA_0_INT_2, B => data_iopads_in(0), S => UN1_SYNCED_CS_N_7_I_A3); II_un1_synced_cs_n_7_i_a3: NOR2FT port map ( Y => UN1_SYNCED_CS_N_7_I_A3, A => UN3_DAC_START_0_A2_0, B => DATA_OUT_2_SQMUXA_0_A2); \II_mxfe_register_1_1_0_a3[7]\: NOR2FT port map ( Y => MXFE_REGISTER_1_1_0_A3(7), A => MXFE_REGISTER_1_0(7), B => reset_8); \II_mxfe_register_1_0[7]\: MUX2H port map ( Y => MXFE_REGISTER_1_0(7), A => MXFE_CONFIGURATION_DATA_15_INT_17, B => data_iopads_in(7), S => UN1_SYNCED_CS_N_8_I_A3); \II_mxfe_register_1_1_0_a3[6]\: NOR2FT port map ( Y => MXFE_REGISTER_1_1_0_A3(6), A => N_37, B => reset_8); \II_mxfe_register_1_0[6]\: MUX2H port map ( Y => N_37, A => MXFE_CONFIGURATION_DATA_14_INT_16, B => data_iopads_in(6), S => UN1_SYNCED_CS_N_8_I_A3); \II_mxfe_register_1_1_0_a3[5]\: NOR2FT port map ( Y => MXFE_REGISTER_1_1_0_A3(5), A => MXFE_REGISTER_1_0(5), B => reset_8); \II_mxfe_register_1_0[5]\: MUX2H port map ( Y => MXFE_REGISTER_1_0(5), A => MXFE_CONFIGURATION_DATA_13_INT_15, B => data_iopads_in(5), S => UN1_SYNCED_CS_N_8_I_A3); \II_mxfe_register_1_1_0_a3[4]\: NOR2FT port map ( Y => MXFE_REGISTER_1_1_0_A3(4), A => MXFE_REGISTER_1_0(4), B => reset_8); \II_mxfe_register_1_0[4]\: MUX2H port map ( Y => MXFE_REGISTER_1_0(4), A => MXFE_CONFIGURATION_DATA_12_INT_14, B => data_iopads_in(4), S => UN1_SYNCED_CS_N_8_I_A3); \II_mxfe_register_1_1_0_a3[3]\: NOR2FT port map ( Y => MXFE_REGISTER_1_1_0_A3(3), A => MXFE_REGISTER_1_0(3), B => reset_8); \II_mxfe_register_1_0[3]\: MUX2H port map ( Y => MXFE_REGISTER_1_0(3), A => MXFE_CONFIGURATION_DATA_11_INT_13, B => data_iopads_in(3), S => UN1_SYNCED_CS_N_8_I_A3); \II_mxfe_register_1_1_0_a3[2]\: NOR2FT port map ( Y => MXFE_REGISTER_1_1_0_A3(2), A => MXFE_REGISTER_1_0(2), B => reset_7); \II_mxfe_register_1_0[2]\: MUX2H port map ( Y => MXFE_REGISTER_1_0(2), A => MXFE_CONFIGURATION_DATA_10_INT_12, B => data_iopads_in(2), S => UN1_SYNCED_CS_N_8_I_A3); \II_mxfe_register_1_1_0_a3[1]\: NOR2FT port map ( Y => MXFE_REGISTER_1_1_0_A3(1), A => MXFE_REGISTER_1_0(1), B => reset_7); \II_mxfe_register_1_0[1]\: MUX2H port map ( Y => MXFE_REGISTER_1_0(1), A => MXFE_CONFIGURATION_DATA_9_INT_11, B => data_iopads_in(1), S => UN1_SYNCED_CS_N_8_I_A3); \II_mxfe_register_1_1_0_a3[0]\: NOR2FT port map ( Y => MXFE_REGISTER_1_1_0_A3(0), A => N_31, B => reset_7); \II_mxfe_register_1_0[0]\: MUX2H port map ( Y => N_31, A => MXFE_CONFIGURATION_DATA_8_INT_10, B => data_iopads_in(0), S => UN1_SYNCED_CS_N_8_I_A3); II_un1_synced_cs_n_8_i_a3: NOR2 port map ( Y => UN1_SYNCED_CS_N_8_I_A3, A => UN3_MXFE_START_0_A2_0, B => DATA_OUT_2_SQMUXA_0_A2); \II_mxfe_instruction_register_1_0_a3[7]\: NOR2FT port map ( Y => MXFE_INSTRUCTION_REGISTER_1_0_A3(7), A => MXFE_INSTRUCTION_REGISTER_0(7), B => reset_7); \II_mxfe_instruction_register_0[7]\: MUX2H port map ( Y => MXFE_INSTRUCTION_REGISTER_0(7), A => WRITE_N_OR_READ_INT_53, B => data_iopads_in(7), S => UN1_SYNCED_CS_N_9_I_A3); \II_mxfe_instruction_register_1_0_a3[6]\: NOR2FT port map ( Y => MXFE_INSTRUCTION_REGISTER_1_0_A3(6), A => N_45, B => reset_7); \II_mxfe_instruction_register_0[6]\: MUX2H port map ( Y => N_45, A => ONE_N_OR_TWO_INT_52, B => data_iopads_in(6), S => UN1_SYNCED_CS_N_9_I_A3); \II_mxfe_instruction_register_1_0_a3[5]\: NOR2FT port map ( Y => MXFE_INSTRUCTION_REGISTER_1_0_A3(5), A => MXFE_INSTRUCTION_REGISTER_0(5), B => reset_7); \II_mxfe_instruction_register_0[5]\: MUX2H port map ( Y => MXFE_INSTRUCTION_REGISTER_0(5), A => MXFE_CONFIGURATION_DATA_21_INT_23, B => data_iopads_in(5), S => UN1_SYNCED_CS_N_9_I_A3); \II_mxfe_instruction_register_1_0_a3[4]\: NOR2FT port map ( Y => MXFE_INSTRUCTION_REGISTER_1_0_A3(4), A => MXFE_INSTRUCTION_REGISTER_0(4), B => reset_7); \II_mxfe_instruction_register_0[4]\: MUX2H port map ( Y => MXFE_INSTRUCTION_REGISTER_0(4), A => MXFE_CONFIGURATION_DATA_20_INT_22, B => data_iopads_in(4), S => UN1_SYNCED_CS_N_9_I_A3); \II_mxfe_instruction_register_1_0_a3[3]\: NOR2FT port map ( Y => MXFE_INSTRUCTION_REGISTER_1_0_A3(3), A => MXFE_INSTRUCTION_REGISTER_0(3), B => reset_7); \II_mxfe_instruction_register_0[3]\: MUX2H port map ( Y => MXFE_INSTRUCTION_REGISTER_0(3), A => MXFE_CONFIGURATION_DATA_19_INT_21, B => data_iopads_in(3), S => UN1_SYNCED_CS_N_9_I_A3); \II_mxfe_instruction_register_1_0_a3[2]\: NOR2FT port map ( Y => MXFE_INSTRUCTION_REGISTER_1_0_A3(2), A => MXFE_INSTRUCTION_REGISTER_0(2), B => reset_7); \II_mxfe_instruction_register_0[2]\: MUX2H port map ( Y => MXFE_INSTRUCTION_REGISTER_0(2), A => MXFE_CONFIGURATION_DATA_18_INT_20, B => data_iopads_in(2), S => UN1_SYNCED_CS_N_9_I_A3); \II_mxfe_instruction_register_1_0_a3[1]\: NOR2FT port map ( Y => MXFE_INSTRUCTION_REGISTER_1_0_A3(1), A => MXFE_INSTRUCTION_REGISTER_0(1), B => reset_7); \II_mxfe_instruction_register_0[1]\: MUX2H port map ( Y => MXFE_INSTRUCTION_REGISTER_0(1), A => MXFE_CONFIGURATION_DATA_17_INT_19, B => data_iopads_in(1), S => UN1_SYNCED_CS_N_9_I_A3); \II_mxfe_instruction_register_1_0_a3[0]\: NOR2FT port map ( Y => MXFE_INSTRUCTION_REGISTER_1_0_A3(0), A => MXFE_INSTRUCTION_REGISTER_0(0), B => reset_7); \II_mxfe_instruction_register_0[0]\: MUX2H port map ( Y => MXFE_INSTRUCTION_REGISTER_0(0), A => MXFE_CONFIGURATION_DATA_16_INT_18, B => data_iopads_in(0), S => UN1_SYNCED_CS_N_9_I_A3); II_un1_synced_cs_n_9_i_a3: NOR2FT port map ( Y => UN1_SYNCED_CS_N_9_I_A3, A => UN3_DAC_START_0_A2_0, B => UN3_MXFE_START_0_A2); \II_dac_command_register_1_0_a3[7]\: NOR2FT port map ( Y => DAC_COMMAND_REGISTER_1_0_A3(7), A => DAC_COMMAND_REGISTER_0(7), B => reset_7); \II_dac_command_register_0[7]\: MUX2H port map ( Y => DAC_COMMAND_REGISTER_0(7), A => DAC_DATA_23_INT_47, B => data_iopads_in(7), S => DAC_START_INT_51); \II_dac_command_register_1_0_a3[6]\: NOR2FT port map ( Y => DAC_COMMAND_REGISTER_1_0_A3(6), A => DAC_COMMAND_REGISTER_0(6), B => reset_6); \II_dac_command_register_0[6]\: MUX2H port map ( Y => DAC_COMMAND_REGISTER_0(6), A => DAC_DATA_22_INT_46, B => data_iopads_in(6), S => DAC_START_INT_51); \II_dac_command_register_1_0_a3[5]\: NOR2FT port map ( Y => DAC_COMMAND_REGISTER_1_0_A3(5), A => DAC_COMMAND_REGISTER_0(5), B => reset_6); \II_dac_command_register_0[5]\: MUX2H port map ( Y => DAC_COMMAND_REGISTER_0(5), A => DAC_DATA_21_INT_45, B => data_iopads_in(5), S => DAC_START_INT_51); \II_dac_command_register_1_0_a3[4]\: NOR2FT port map ( Y => DAC_COMMAND_REGISTER_1_0_A3(4), A => DAC_COMMAND_REGISTER_0(4), B => reset_6); \II_dac_command_register_0[4]\: MUX2H port map ( Y => DAC_COMMAND_REGISTER_0(4), A => DAC_DATA_20_INT_44, B => data_iopads_in(4), S => DAC_START_INT_51); \II_dac_command_register_1_0_a3[3]\: NOR2FT port map ( Y => DAC_COMMAND_REGISTER_1_0_A3(3), A => N_50, B => reset_6); \II_dac_command_register_0[3]\: MUX2H port map ( Y => N_50, A => DAC_DATA_19_INT_43, B => data_iopads_in(3), S => DAC_START_INT_51); \II_dac_command_register_1_0_a3[2]\: NOR2FT port map ( Y => DAC_COMMAND_REGISTER_1_0_A3(2), A => DAC_COMMAND_REGISTER_0(2), B => reset_6); \II_dac_command_register_0[2]\: MUX2H port map ( Y => DAC_COMMAND_REGISTER_0(2), A => DAC_DATA_18_INT_42, B => data_iopads_in(2), S => DAC_START_INT_51); \II_dac_command_register_1_0_a3[1]\: NOR2FT port map ( Y => DAC_COMMAND_REGISTER_1_0_A3(1), A => DAC_COMMAND_REGISTER_0(1), B => reset_6); \II_dac_command_register_0[1]\: MUX2H port map ( Y => DAC_COMMAND_REGISTER_0(1), A => DAC_DATA_17_INT_41, B => data_iopads_in(1), S => DAC_START_INT_51); \II_dac_command_register_1_0_a3[0]\: NOR2FT port map ( Y => DAC_COMMAND_REGISTER_1_0_A3(0), A => DAC_COMMAND_REGISTER_0(0), B => reset_6); \II_dac_command_register_0[0]\: MUX2H port map ( Y => DAC_COMMAND_REGISTER_0(0), A => DAC_DATA_16_INT_40, B => data_iopads_in(0), S => DAC_START_INT_51); \II_clock_divider.clock_divider_counter_3_i[3]\: AND2 port map ( Y => CLOCK_DIVIDER_COUNTER_3_I(3), A => CLOCK_DIVIDER_COUNTER_3_I_O3(0), B => I_13); \II_clock_divider.clock_divider_counter_3_i[2]\: AND2 port map ( Y => CLOCK_DIVIDER_COUNTER_3_I(2), A => CLOCK_DIVIDER_COUNTER_3_I_O3(0), B => I_9); \II_clock_divider.clock_divider_counter_3_i[1]\: AND2 port map ( Y => CLOCK_DIVIDER_COUNTER_3_I(1), A => CLOCK_DIVIDER_COUNTER_3_I_O3(0), B => I_5); \II_clock_divider.clock_divider_counter_3_i[0]\: NOR2FT port map ( Y => CLOCK_DIVIDER_COUNTER_3_I(0), A => CLOCK_DIVIDER_COUNTER_3_I_O3(0), B => CLOCK_DIVIDER_COUNTER(0)); \II_clock_divider.clock_divider_counter_3_i_o3[0]\: NOR2FT port map ( Y => CLOCK_DIVIDER_COUNTER_3_I_O3(0), A => DAC_CLOCK_ENABLE_INT_50, B => reset_0); \II_data_out_0_iv_i[14]\: NOR3 port map ( Y => data_out_0_iv_i(14), A => DATA_OUT_0_IV_I_O3(14), B => DATA_OUT_0_IV_I_A3(14), C => DATA_OUT_0_IV_I_0(14)); \II_data_out_0_iv_i_0[14]\: OR2 port map ( Y => DATA_OUT_0_IV_I_0(14), A => DATA_OUT_0_IV_I_A3_0(14), B => DATA_OUT_0_IV_I_A2(14)); \II_data_out_0_iv_i_a3[14]\: NOR2 port map ( Y => DATA_OUT_0_IV_I_A3(14), A => DATA_OUT_0_IV_I_A2_1(14), B => DAC_DATA_14_INT_38); II_un3_mxfe_start_0_a3: NOR2 port map ( Y => MXFE_START_INT_49, A => UN3_MXFE_START_0_A2, B => UN3_MXFE_START_0_A2_0); II_un3_mxfe_start_0_a2_0: OR2 port map ( Y => UN3_MXFE_START_0_A2_0, A => DATA_OUT_0_IV_I_A2_1(14), B => UN3_MXFE_START_0_A2_1); II_un3_dac_start_0_a3: AND2 port map ( Y => DAC_START_INT_51, A => UN3_DAC_START_0_A2, B => UN3_DAC_START_0_A2_0); II_un3_dac_start_0_a2_0: NOR2 port map ( Y => UN3_DAC_START_0_A2_0, A => UN3_MXFE_START_0_A2_1, B => DATA_OUT_1_SQMUXA_0_A2); II_un3_mxfe_start_0_a2_1: NAND3FFT port map ( Y => UN3_MXFE_START_0_A2_1, A => SYNCED_CS_N_INT_48, B => SYNCED_WR_N, C => CANDIDATE_DELAYED); II_un4_reset_clock_divider_counter_0_a3: NAND3FTT port map ( Y => DAC_CLOCK_ENABLE_INT_50, A => CLOCK_DIVIDER_COUNTER(1), B => UN4_RESET_CLOCK_DIVIDER_COUNTER_0_A3_0, C => CLOCK_DIVIDER_COUNTER(0)); II_un4_reset_clock_divider_counter_0_a3_0: AND2FT port map ( Y => UN4_RESET_CLOCK_DIVIDER_COUNTER_0_A3_0, A => CLOCK_DIVIDER_COUNTER(2), B => CLOCK_DIVIDER_COUNTER(3)); \II_data_out_0_iv[15]\: AO21 port map ( Y => data_out_15, A => DATA_OUT_6_SQMUXA_0, B => DAC_DATA_15_INT_39, C => DATA_OUT_CNST_M(0)); \II_data_out_0_iv[13]\: AO21 port map ( Y => data_out_13, A => DATA_OUT_6_SQMUXA_0, B => DAC_DATA_13_INT_37, C => N_150_I_0); \II_data_out_0_iv[12]\: AO21 port map ( Y => data_out_12, A => DATA_OUT_6_SQMUXA_0, B => DAC_DATA_12_INT_36, C => DATA_OUT_CNST_M(0)); \II_data_out_0_iv[11]\: AO21 port map ( Y => data_out_11, A => DATA_OUT_6_SQMUXA_0, B => DAC_DATA_11_INT_35, C => DATA_OUT_CNST_M(0)); \II_data_out_0_iv[10]\: AO21 port map ( Y => data_out_10, A => DATA_OUT_6_SQMUXA_0, B => DAC_DATA_10_INT_34, C => DATA_OUT_CNST_M(0)); \II_data_out_0_iv[9]\: AO21 port map ( Y => data_out_9, A => DATA_OUT_6_SQMUXA_0, B => DAC_DATA_9_INT_33, C => DATA_OUT_CNST_M(0)); \II_data_out[8]\: AND2 port map ( Y => data_out_8, A => DATA_OUT_6_SQMUXA_0, B => DAC_DATA_8_INT_32); \II_data_out_0_iv[7]\: OR3FTT port map ( Y => data_out_7, A => DAC_DATA_REGISTER_M(7), B => DATA_OUT_CNST_M(0), C => DATA_OUT_0_IV_2_I(7)); \II_data_out_0_iv_2[7]\: AO21TTF port map ( Y => DATA_OUT_0_IV_2_I(7), A => DATA_OUT_1_SQMUXA, B => WRITE_N_OR_READ_INT_53, C => DATA_OUT_0_IV_1(7)); \II_data_out_0_iv_1[7]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_1(7), A => DATA_OUT_2_SQMUXA, B => MXFE_CONFIGURATION_DATA_15_INT_17, C => DATA_OUT_0_IV_0(7)); \II_data_out_0_iv_0[7]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_0(7), A => DATA_OUT_4_SQMUXA, B => mxfe_register_data(7), C => MXFE_REGISTER_2_M(7)); \II_mxfe_register_2_m[7]\: NAND2 port map ( Y => MXFE_REGISTER_2_M(7), A => DATA_OUT_3_SQMUXA, B => MXFE_CONFIGURATION_DATA_7_INT_9); \II_dac_data_register_m[7]\: NAND2 port map ( Y => DAC_DATA_REGISTER_M(7), A => DATA_OUT_6_SQMUXA_0, B => DAC_DATA_7_INT_31); \II_data_out_0_iv[6]\: OR3 port map ( Y => data_out_6, A => N_150_I_0, B => DATA_OUT_0_IV_2_I(6), C => DAC_DATA_REGISTER_M_I(6)); \II_data_out_0_iv_2[6]\: AO21TTF port map ( Y => DATA_OUT_0_IV_2_I(6), A => DATA_OUT_1_SQMUXA, B => ONE_N_OR_TWO_INT_52, C => DATA_OUT_0_IV_1(6)); \II_data_out_0_iv_1[6]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_1(6), A => DATA_OUT_2_SQMUXA, B => MXFE_CONFIGURATION_DATA_14_INT_16, C => DATA_OUT_0_IV_0(6)); \II_data_out_0_iv_0[6]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_0(6), A => DATA_OUT_4_SQMUXA, B => mxfe_register_data(6), C => MXFE_REGISTER_2_M(6)); \II_mxfe_register_2_m[6]\: NAND2 port map ( Y => MXFE_REGISTER_2_M(6), A => DATA_OUT_3_SQMUXA, B => MXFE_CONFIGURATION_DATA_6_INT_8); \II_dac_data_register_m[6]\: AND2 port map ( Y => DAC_DATA_REGISTER_M_I(6), A => DATA_OUT_6_SQMUXA, B => DAC_DATA_6_INT_30); \II_data_out_0_iv[5]\: OR3FTT port map ( Y => data_out_5, A => DAC_DATA_REGISTER_M(5), B => DATA_OUT_CNST_M(0), C => DATA_OUT_0_IV_2_I(5)); \II_data_out_0_iv_2[5]\: AO21TTF port map ( Y => DATA_OUT_0_IV_2_I(5), A => DATA_OUT_1_SQMUXA, B => MXFE_CONFIGURATION_DATA_21_INT_23, C => DATA_OUT_0_IV_1(5)); \II_data_out_0_iv_1[5]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_1(5), A => DATA_OUT_2_SQMUXA, B => MXFE_CONFIGURATION_DATA_13_INT_15, C => DATA_OUT_0_IV_0(5)); \II_data_out_0_iv_0[5]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_0(5), A => DATA_OUT_4_SQMUXA, B => mxfe_register_data(5), C => MXFE_REGISTER_2_M(5)); \II_mxfe_register_2_m[5]\: NAND2 port map ( Y => MXFE_REGISTER_2_M(5), A => DATA_OUT_3_SQMUXA, B => MXFE_CONFIGURATION_DATA_5_INT_7); \II_dac_data_register_m[5]\: NAND2 port map ( Y => DAC_DATA_REGISTER_M(5), A => DATA_OUT_6_SQMUXA, B => DAC_DATA_5_INT_29); \II_data_out_0_iv[4]\: AO21TTF port map ( Y => data_out_4, A => DATA_OUT_6_SQMUXA, B => DAC_DATA_4_INT_28, C => DATA_OUT_0_IV_2(4)); \II_data_out_0_iv_2[4]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_2(4), A => DATA_OUT_1_SQMUXA, B => MXFE_CONFIGURATION_DATA_20_INT_22, C => DATA_OUT_0_IV_1(4)); \II_data_out_0_iv_1[4]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_1(4), A => DATA_OUT_2_SQMUXA, B => MXFE_CONFIGURATION_DATA_12_INT_14, C => DATA_OUT_0_IV_0(4)); \II_data_out_0_iv_0[4]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_0(4), A => DATA_OUT_4_SQMUXA, B => mxfe_register_data(4), C => MXFE_REGISTER_2_M(4)); \II_mxfe_register_2_m[4]\: NAND2 port map ( Y => MXFE_REGISTER_2_M(4), A => DATA_OUT_3_SQMUXA, B => MXFE_CONFIGURATION_DATA_4_INT_6); \II_data_out_0_iv[3]\: OR3FTT port map ( Y => data_out_3, A => DAC_DATA_REGISTER_M(3), B => DATA_OUT_CNST_M(0), C => DATA_OUT_0_IV_2_I(3)); \II_data_out_0_iv_2[3]\: AO21TTF port map ( Y => DATA_OUT_0_IV_2_I(3), A => DATA_OUT_1_SQMUXA, B => MXFE_CONFIGURATION_DATA_19_INT_21, C => DATA_OUT_0_IV_1(3)); \II_data_out_0_iv_1[3]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_1(3), A => DATA_OUT_2_SQMUXA, B => MXFE_CONFIGURATION_DATA_11_INT_13, C => DATA_OUT_0_IV_0(3)); \II_data_out_0_iv_0[3]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_0(3), A => DATA_OUT_4_SQMUXA, B => mxfe_register_data(3), C => MXFE_REGISTER_2_M(3)); \II_mxfe_register_2_m[3]\: NAND2 port map ( Y => MXFE_REGISTER_2_M(3), A => DATA_OUT_3_SQMUXA, B => MXFE_CONFIGURATION_DATA_3_INT_5); \II_dac_data_register_m[3]\: NAND2 port map ( Y => DAC_DATA_REGISTER_M(3), A => DATA_OUT_6_SQMUXA, B => DAC_DATA_3_INT_27); \II_data_out_0_iv[2]\: OR3FTT port map ( Y => data_out_2, A => DAC_DATA_REGISTER_M(2), B => DATA_OUT_CNST_M(0), C => DATA_OUT_0_IV_2_I(2)); \II_data_out_0_iv_2[2]\: AO21TTF port map ( Y => DATA_OUT_0_IV_2_I(2), A => DATA_OUT_1_SQMUXA, B => MXFE_CONFIGURATION_DATA_18_INT_20, C => DATA_OUT_0_IV_1(2)); \II_data_out_0_iv_1[2]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_1(2), A => DATA_OUT_2_SQMUXA, B => MXFE_CONFIGURATION_DATA_10_INT_12, C => DATA_OUT_0_IV_0(2)); \II_data_out_0_iv_0[2]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_0(2), A => DATA_OUT_4_SQMUXA, B => mxfe_register_data(2), C => MXFE_REGISTER_2_M(2)); \II_mxfe_register_2_m[2]\: NAND2 port map ( Y => MXFE_REGISTER_2_M(2), A => DATA_OUT_3_SQMUXA, B => MXFE_CONFIGURATION_DATA_2_INT_4); \II_dac_data_register_m[2]\: NAND2 port map ( Y => DAC_DATA_REGISTER_M(2), A => DATA_OUT_6_SQMUXA, B => DAC_DATA_2_INT_26); \II_data_out_0_iv[1]\: OR3 port map ( Y => data_out_1, A => N_150_I_0, B => DATA_OUT_0_IV_2_I(1), C => DAC_DATA_REGISTER_M_I(1)); \II_data_out_0_iv_2[1]\: AO21TTF port map ( Y => DATA_OUT_0_IV_2_I(1), A => DATA_OUT_1_SQMUXA, B => MXFE_CONFIGURATION_DATA_17_INT_19, C => DATA_OUT_0_IV_1(1)); \II_data_out_0_iv_1[1]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_1(1), A => DATA_OUT_2_SQMUXA, B => MXFE_CONFIGURATION_DATA_9_INT_11, C => DATA_OUT_0_IV_0(1)); \II_data_out_0_iv_0[1]\: AOI21TTF port map ( Y => DATA_OUT_0_IV_0(1), A => DATA_OUT_4_SQMUXA, B => mxfe_register_data(1), C => MXFE_REGISTER_2_M(1)); \II_mxfe_register_2_m[1]\: NAND2 port map ( Y => MXFE_REGISTER_2_M(1), A => DATA_OUT_3_SQMUXA, B => MXFE_CONFIGURATION_DATA_1_INT_3); \II_dac_data_register_m[1]\: AND2 port map ( Y => DAC_DATA_REGISTER_M_I(1), A => DATA_OUT_6_SQMUXA, B => DAC_DATA_1_INT_25); \II_data_out_cnst_i_o2[1]\: NOR2FT port map ( Y => N_150_I_0, A => DATA_OUT_0_IV_I_A3_0(14), B => DATA_OUT_0_IV_I_O3(14)); \II_data_out_0_iv_i_a3_0[14]\: NOR3 port map ( Y => DATA_OUT_0_IV_I_A3_0(14), A => DATA_OUT_0_IV_I_A2_2(14), B => N_392_I, C => DATA_OUT_0_IV_I_A3_0_1_I(14)); \II_data_out_0_iv_i_a3_0_1[14]\: NAND3 port map ( Y => DATA_OUT_0_IV_I_A3_0_1_I(14), A => address_ipads_c_3, B => address_ipads_c_5, C => address_ipads_c_6); \II_data_out_iv[0]\: OR3 port map ( Y => data_out_0, A => DAC_BUSY_M_I, B => DAC_DATA_REGISTER_M_I(0), C => DATA_OUT_IV_4_I(0)); \II_data_out_iv_4[0]\: OR3 port map ( Y => DATA_OUT_IV_4_I(0), A => DATA_OUT_CNST_M(0), B => DATA_OUT_IV_2_I(0), C => MXFE_BUSY_M_I); \II_data_out_iv_2[0]\: AO21TTF port map ( Y => DATA_OUT_IV_2_I(0), A => DATA_OUT_1_SQMUXA, B => MXFE_CONFIGURATION_DATA_16_INT_18, C => DATA_OUT_IV_1(0)); II_data_out_1_sqmuxa_0_a3: NOR2 port map ( Y => DATA_OUT_1_SQMUXA, A => UN3_MXFE_START_0_A2, B => DATA_OUT_3_SQMUXA_1); \II_data_out_iv_1[0]\: AOI21TTF port map ( Y => DATA_OUT_IV_1(0), A => DATA_OUT_2_SQMUXA, B => MXFE_CONFIGURATION_DATA_8_INT_10, C => DATA_OUT_IV_0(0)); II_data_out_2_sqmuxa_0_a3: NOR2 port map ( Y => DATA_OUT_2_SQMUXA, A => DATA_OUT_2_SQMUXA_0_A2, B => UN1_DATA_OUT_0_SQMUXA_I_I_A2); \II_data_out_iv_0[0]\: AOI21TTF port map ( Y => DATA_OUT_IV_0(0), A => DATA_OUT_4_SQMUXA, B => mxfe_register_data(0), C => MXFE_REGISTER_2_M(0)); II_data_out_4_sqmuxa_0_a3: NOR3 port map ( Y => DATA_OUT_4_SQMUXA, A => DATA_OUT_0_IV_I_O3(14), B => DATA_OUT_4_SQMUXA_0_A2, C => DATA_OUT_4_SQMUXA_0_A3_0); II_data_out_4_sqmuxa_0_a3_0: OR2 port map ( Y => DATA_OUT_4_SQMUXA_0_A3_0, A => DATA_OUT_0_IV_I_A2_2(14), B => address_ipads_c_3); \II_mxfe_register_2_m[0]\: NAND2 port map ( Y => MXFE_REGISTER_2_M(0), A => DATA_OUT_3_SQMUXA, B => MXFE_CONFIGURATION_DATA_0_INT_2); II_data_out_3_sqmuxa_0_a3: NOR2 port map ( Y => DATA_OUT_3_SQMUXA, A => DATA_OUT_2_SQMUXA_0_A2, B => DATA_OUT_3_SQMUXA_1); II_data_out_3_sqmuxa_0_a3_1: OR2 port map ( Y => DATA_OUT_3_SQMUXA_1, A => DATA_OUT_0_IV_I_O3(14), B => DATA_OUT_1_SQMUXA_0_A2); II_data_out_1_sqmuxa_0_a2: NAND2 port map ( Y => DATA_OUT_1_SQMUXA_0_A2, A => DATA_OUT_0_IV_I_A2_6(14), B => address_ipads_c_1); II_data_out_2_sqmuxa_0_a2: OR2FT port map ( Y => DATA_OUT_2_SQMUXA_0_A2, A => address_ipads_c_2, B => address_ipads_c_4); II_mxfe_busy_m: NOR3FFT port map ( Y => MXFE_BUSY_M_I, A => MXFE_BUSY, B => N_364_I_0, C => UN3_MXFE_START_0_A2); II_un3_mxfe_start_0_a2: OR2 port map ( Y => UN3_MXFE_START_0_A2, A => address_ipads_c_4, B => address_ipads_c_2); \II_data_out_cnst_m[15]\: NOR3FTT port map ( Y => DATA_OUT_CNST_M(0), A => UN1_DATA_OUT_0_SQMUXA_I_I_A2, B => DATA_OUT_0_IV_I_A2(14), C => DATA_OUT_0_IV_I_O3(14)); \II_data_out_0_iv_i_a2[14]\: OA21FTF port map ( Y => DATA_OUT_0_IV_I_A2(14), A => DATA_OUT_0_IV_I_A2_2(14), B => DATA_OUT_0_IV_I_A2_3(14), C => DATA_OUT_4_SQMUXA_0_A2); \II_data_out_0_iv_i_a2_2[14]\: OR2FT port map ( Y => DATA_OUT_0_IV_I_A2_2(14), A => UN3_DAC_START_0_A2, B => address_ipads_c_1); \II_data_out_0_iv_i_a2_3[14]\: NOR2FT port map ( Y => DATA_OUT_0_IV_I_A2_3(14), A => address_ipads_c_3, B => address_ipads_c_4); \II_dac_data_register_m[0]\: AND2 port map ( Y => DAC_DATA_REGISTER_M_I(0), A => DATA_OUT_6_SQMUXA, B => DAC_DATA_0_INT_24); II_data_out_6_sqmuxa_0_a3: NOR2 port map ( Y => DATA_OUT_6_SQMUXA, A => N_297_1, B => UN1_DATA_OUT_0_SQMUXA_I_I_A2); II_un1_synced_cs_n_6_i_a3_1: NAND2 port map ( Y => N_297_1, A => address_ipads_c_2, B => address_ipads_c_4); II_dac_busy_m: NOR3FFT port map ( Y => DAC_BUSY_M_I, A => DAC_BUSY, B => UN3_DAC_START_0_A2, C => UN1_DATA_OUT_0_SQMUXA_I_I_A2); II_un3_dac_start_0_a2: NOR2FT port map ( Y => UN3_DAC_START_0_A2, A => address_ipads_c_4, B => address_ipads_c_2); II_N_364_i: INV port map ( Y => N_364_I_0, A => UN1_DATA_OUT_0_SQMUXA_I_I_A2); II_un1_data_out_0_sqmuxa_i_i_a2: OR2 port map ( Y => UN1_DATA_OUT_0_SQMUXA_I_I_A2, A => DATA_OUT_0_IV_I_O3(14), B => DATA_OUT_0_IV_I_A2_1(14)); \II_data_out_0_iv_i_a2_1[14]\: OR2FT port map ( Y => DATA_OUT_0_IV_I_A2_1(14), A => DATA_OUT_0_IV_I_A2_6(14), B => address_ipads_c_1); \II_data_out_0_iv_i_a2_6[14]\: AND2FT port map ( Y => DATA_OUT_0_IV_I_A2_6(14), A => DATA_OUT_4_SQMUXA_0_A2, B => address_ipads_c_3); II_data_out_4_sqmuxa_0_a2: OR3 port map ( Y => DATA_OUT_4_SQMUXA_0_A2, A => N_392_I, B => address_ipads_c_5, C => address_ipads_c_6); \II_data_out_0_iv_i_a2_0[14]\: OR3 port map ( Y => N_392_I, A => address_ipads_c_i_0_i_0, B => DATA_OUT_0_IV_I_A2_0_6_I(14), C => address_ipads_c_0); \II_data_out_0_iv_i_a2_0_6[14]\: OR3 port map ( Y => DATA_OUT_0_IV_I_A2_0_6_I(14), A => address_ipads_c_i_0_i_8, B => DATA_OUT_0_IV_I_A2_0_4_I(14), C => address_ipads_c_8); \II_data_out_0_iv_i_a2_0_4[14]\: OR3 port map ( Y => DATA_OUT_0_IV_I_A2_0_4_I(14), A => address_ipads_c_i_0_i_10, B => DATA_OUT_0_IV_I_A2_0_2_I(14), C => address_ipads_c_10); \II_data_out_0_iv_i_a2_0_2[14]\: OR3 port map ( Y => DATA_OUT_0_IV_I_A2_0_2_I(14), A => address_ipads_c_i_0_i_12, B => DATA_OUT_0_IV_I_A2_0_0_I(14), C => address_ipads_c_12); \II_data_out_0_iv_i_a2_0_0[14]\: OR2 port map ( Y => DATA_OUT_0_IV_I_A2_0_0_I(14), A => address_ipads_c_i_0_i_14, B => address_ipads_c_14); \II_data_out_0_iv_i_o3[14]\: OR2 port map ( Y => DATA_OUT_0_IV_I_O3(14), A => rd_n_ipad_c, B => cs_n_ipad_c); \II_dac_command_register[0]\: DFF port map ( Q => DAC_DATA_16_INT_40, CLK => mhz_20_clock_1, D => DAC_COMMAND_REGISTER_1_0_A3(0)); \II_dac_command_register[1]\: DFF port map ( Q => DAC_DATA_17_INT_41, CLK => mhz_20_clock_2, D => DAC_COMMAND_REGISTER_1_0_A3(1)); \II_dac_command_register[2]\: DFF port map ( Q => DAC_DATA_18_INT_42, CLK => mhz_20_clock_2, D => DAC_COMMAND_REGISTER_1_0_A3(2)); \II_dac_command_register[3]\: DFF port map ( Q => DAC_DATA_19_INT_43, CLK => mhz_20_clock_2, D => DAC_COMMAND_REGISTER_1_0_A3(3)); \II_dac_command_register[4]\: DFF port map ( Q => DAC_DATA_20_INT_44, CLK => mhz_20_clock_2, D => DAC_COMMAND_REGISTER_1_0_A3(4)); \II_dac_command_register[5]\: DFF port map ( Q => DAC_DATA_21_INT_45, CLK => mhz_20_clock_2, D => DAC_COMMAND_REGISTER_1_0_A3(5)); \II_dac_command_register[6]\: DFF port map ( Q => DAC_DATA_22_INT_46, CLK => mhz_20_clock_2, D => DAC_COMMAND_REGISTER_1_0_A3(6)); \II_dac_command_register[7]\: DFF port map ( Q => DAC_DATA_23_INT_47, CLK => mhz_20_clock_2, D => DAC_COMMAND_REGISTER_1_0_A3(7)); \II_mxfe_instruction_register[0]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_16_INT_18, CLK => mhz_20_clock_2, D => MXFE_INSTRUCTION_REGISTER_1_0_A3(0)); \II_mxfe_instruction_register[1]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_17_INT_19, CLK => mhz_20_clock_2, D => MXFE_INSTRUCTION_REGISTER_1_0_A3(1)); \II_mxfe_instruction_register[2]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_18_INT_20, CLK => mhz_20_clock_2, D => MXFE_INSTRUCTION_REGISTER_1_0_A3(2)); \II_mxfe_instruction_register[3]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_19_INT_21, CLK => mhz_20_clock_2, D => MXFE_INSTRUCTION_REGISTER_1_0_A3(3)); \II_mxfe_instruction_register[4]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_20_INT_22, CLK => mhz_20_clock_2, D => MXFE_INSTRUCTION_REGISTER_1_0_A3(4)); \II_mxfe_instruction_register[5]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_21_INT_23, CLK => mhz_20_clock_3, D => MXFE_INSTRUCTION_REGISTER_1_0_A3(5)); \II_mxfe_instruction_register[6]\: DFF port map ( Q => ONE_N_OR_TWO_INT_52, CLK => mhz_20_clock_3, D => MXFE_INSTRUCTION_REGISTER_1_0_A3(6)); \II_mxfe_instruction_register[7]\: DFF port map ( Q => WRITE_N_OR_READ_INT_53, CLK => mhz_20_clock_3, D => MXFE_INSTRUCTION_REGISTER_1_0_A3(7)); \II_mxfe_register_1[0]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_8_INT_10, CLK => mhz_20_clock_3, D => MXFE_REGISTER_1_1_0_A3(0)); \II_mxfe_register_1[1]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_9_INT_11, CLK => mhz_20_clock_3, D => MXFE_REGISTER_1_1_0_A3(1)); \II_mxfe_register_1[2]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_10_INT_12, CLK => mhz_20_clock_3, D => MXFE_REGISTER_1_1_0_A3(2)); \II_mxfe_register_1[3]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_11_INT_13, CLK => mhz_20_clock_3, D => MXFE_REGISTER_1_1_0_A3(3)); \II_mxfe_register_1[4]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_12_INT_14, CLK => mhz_20_clock_3, D => MXFE_REGISTER_1_1_0_A3(4)); \II_mxfe_register_1[5]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_13_INT_15, CLK => mhz_20_clock_3, D => MXFE_REGISTER_1_1_0_A3(5)); \II_mxfe_register_1[6]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_14_INT_16, CLK => mhz_20_clock_3, D => MXFE_REGISTER_1_1_0_A3(6)); \II_mxfe_register_1[7]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_15_INT_17, CLK => mhz_20_clock_3, D => MXFE_REGISTER_1_1_0_A3(7)); \II_mxfe_register_2[0]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_0_INT_2, CLK => mhz_20_clock_3, D => MXFE_REGISTER_2_1_0_A3(0)); \II_mxfe_register_2[1]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_1_INT_3, CLK => mhz_20_clock_4, D => MXFE_REGISTER_2_1_0_A3(1)); \II_mxfe_register_2[2]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_2_INT_4, CLK => mhz_20_clock_4, D => MXFE_REGISTER_2_1_0_A3(2)); \II_mxfe_register_2[3]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_3_INT_5, CLK => mhz_20_clock_4, D => MXFE_REGISTER_2_1_0_A3(3)); \II_mxfe_register_2[4]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_4_INT_6, CLK => mhz_20_clock_4, D => MXFE_REGISTER_2_1_0_A3(4)); \II_mxfe_register_2[5]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_5_INT_7, CLK => mhz_20_clock_4, D => MXFE_REGISTER_2_1_0_A3(5)); \II_mxfe_register_2[6]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_6_INT_8, CLK => mhz_20_clock_4, D => MXFE_REGISTER_2_1_0_A3(6)); \II_mxfe_register_2[7]\: DFF port map ( Q => MXFE_CONFIGURATION_DATA_7_INT_9, CLK => mhz_20_clock_4, D => MXFE_REGISTER_2_1_0_A3(7)); \II_dac_data_register[0]\: DFF port map ( Q => DAC_DATA_0_INT_24, CLK => mhz_20_clock_4, D => DAC_DATA_REGISTER_1_0_A3(0)); \II_dac_data_register[1]\: DFF port map ( Q => DAC_DATA_1_INT_25, CLK => mhz_20_clock_4, D => DAC_DATA_REGISTER_1_0_A3(1)); \II_dac_data_register[2]\: DFF port map ( Q => DAC_DATA_2_INT_26, CLK => mhz_20_clock_4, D => DAC_DATA_REGISTER_1_0_A3(2)); \II_dac_data_register[3]\: DFF port map ( Q => DAC_DATA_3_INT_27, CLK => mhz_20_clock_4, D => DAC_DATA_REGISTER_1_0_A3(3)); \II_dac_data_register[4]\: DFF port map ( Q => DAC_DATA_4_INT_28, CLK => mhz_20_clock_4, D => DAC_DATA_REGISTER_1_0_A3(4)); \II_dac_data_register[5]\: DFF port map ( Q => DAC_DATA_5_INT_29, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(5)); \II_dac_data_register[6]\: DFF port map ( Q => DAC_DATA_6_INT_30, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(6)); \II_dac_data_register[7]\: DFF port map ( Q => DAC_DATA_7_INT_31, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(7)); \II_dac_data_register[8]\: DFF port map ( Q => DAC_DATA_8_INT_32, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(8)); \II_dac_data_register[9]\: DFF port map ( Q => DAC_DATA_9_INT_33, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(9)); \II_dac_data_register[10]\: DFF port map ( Q => DAC_DATA_10_INT_34, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(10)); \II_dac_data_register[11]\: DFF port map ( Q => DAC_DATA_11_INT_35, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(11)); \II_dac_data_register[12]\: DFF port map ( Q => DAC_DATA_12_INT_36, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(12)); \II_dac_data_register[13]\: DFF port map ( Q => DAC_DATA_13_INT_37, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(13)); \II_dac_data_register[14]\: DFF port map ( Q => DAC_DATA_14_INT_38, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(14)); \II_dac_data_register[15]\: DFF port map ( Q => DAC_DATA_15_INT_39, CLK => mhz_20_clock_5, D => DAC_DATA_REGISTER_1_0_A3(15)); \II_clock_divider_counter[0]\: DFF port map ( Q => CLOCK_DIVIDER_COUNTER(0), CLK => mhz_20_clock_5, D => CLOCK_DIVIDER_COUNTER_3_I(0)); \II_clock_divider_counter[1]\: DFF port map ( Q => CLOCK_DIVIDER_COUNTER(1), CLK => mhz_20_clock_6, D => CLOCK_DIVIDER_COUNTER_3_I(1)); \II_clock_divider_counter[2]\: DFF port map ( Q => CLOCK_DIVIDER_COUNTER(2), CLK => mhz_20_clock_6, D => CLOCK_DIVIDER_COUNTER_3_I(2)); \II_clock_divider_counter[3]\: DFF port map ( Q => CLOCK_DIVIDER_COUNTER(3), CLK => mhz_20_clock_6, D => CLOCK_DIVIDER_COUNTER_3_I(3)); \II_un3_clock_divider_counter.I_8\: AND2 port map ( Y => N_7, A => CLOCK_DIVIDER_COUNTER(1), B => CLOCK_DIVIDER_COUNTER(0)); \II_un3_clock_divider_counter.I_13\: XOR2 port map ( Y => I_13, A => N_4, B => CLOCK_DIVIDER_COUNTER(3)); \II_un3_clock_divider_counter.I_12\: AND3 port map ( Y => N_4, A => CLOCK_DIVIDER_COUNTER(0), B => CLOCK_DIVIDER_COUNTER(1), C => CLOCK_DIVIDER_COUNTER(2)); \II_un3_clock_divider_counter.I_9\: XOR2 port map ( Y => I_9, A => N_7, B => CLOCK_DIVIDER_COUNTER(2)); \II_un3_clock_divider_counter.I_5\: XOR2 port map ( Y => I_5, A => CLOCK_DIVIDER_COUNTER(0), B => CLOCK_DIVIDER_COUNTER(1)); II_sync1: dual_rank_synchronizer port map ( mhz_20_clock_1 => mhz_20_clock_1, synced_cs_n => SYNCED_CS_N_INT_48, reset_10 => reset_10, cs_n_ipad_c => cs_n_ipad_c); II_sync2: dual_rank_synchronizer_1 port map ( mhz_20_clock_1 => mhz_20_clock_1, synced_wr_n => SYNCED_WR_N, reset_10 => reset_10, wr_0_n_ipad_c => wr_0_n_ipad_c, wr_1_n_ipad_c => wr_1_n_ipad_c); II_fed1: falling_edge_detector port map ( mhz_20_clock_1 => mhz_20_clock_1, candidate_delayed => CANDIDATE_DELAYED, reset_10 => reset_10, synced_wr_n => SYNCED_WR_N); II_mxfe_busy_ff: jk_ff port map ( mhz_20_clock_1 => mhz_20_clock_1, mxfe_start => MXFE_START_INT_49, configuration_busy => configuration_busy, mxfe_busy => MXFE_BUSY, reset_10 => reset_10); II_dac_busy_ff: jk_ff_1 port map ( mhz_20_clock_1 => mhz_20_clock_1, dac_transfer_busy => dac_transfer_busy, dac_start => DAC_START_INT_51, dac_busy => DAC_BUSY, reset_10 => reset_10); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); mxfe_configuration_data(0) <= MXFE_CONFIGURATION_DATA_0_INT_2; mxfe_configuration_data(1) <= MXFE_CONFIGURATION_DATA_1_INT_3; mxfe_configuration_data(2) <= MXFE_CONFIGURATION_DATA_2_INT_4; mxfe_configuration_data(3) <= MXFE_CONFIGURATION_DATA_3_INT_5; mxfe_configuration_data(4) <= MXFE_CONFIGURATION_DATA_4_INT_6; mxfe_configuration_data(5) <= MXFE_CONFIGURATION_DATA_5_INT_7; mxfe_configuration_data(6) <= MXFE_CONFIGURATION_DATA_6_INT_8; mxfe_configuration_data(7) <= MXFE_CONFIGURATION_DATA_7_INT_9; mxfe_configuration_data(8) <= MXFE_CONFIGURATION_DATA_8_INT_10; mxfe_configuration_data(9) <= MXFE_CONFIGURATION_DATA_9_INT_11; mxfe_configuration_data(10) <= MXFE_CONFIGURATION_DATA_10_INT_12; mxfe_configuration_data(11) <= MXFE_CONFIGURATION_DATA_11_INT_13; mxfe_configuration_data(12) <= MXFE_CONFIGURATION_DATA_12_INT_14; mxfe_configuration_data(13) <= MXFE_CONFIGURATION_DATA_13_INT_15; mxfe_configuration_data(14) <= MXFE_CONFIGURATION_DATA_14_INT_16; mxfe_configuration_data(15) <= MXFE_CONFIGURATION_DATA_15_INT_17; mxfe_configuration_data(16) <= MXFE_CONFIGURATION_DATA_16_INT_18; mxfe_configuration_data(17) <= MXFE_CONFIGURATION_DATA_17_INT_19; mxfe_configuration_data(18) <= MXFE_CONFIGURATION_DATA_18_INT_20; mxfe_configuration_data(19) <= MXFE_CONFIGURATION_DATA_19_INT_21; mxfe_configuration_data(20) <= MXFE_CONFIGURATION_DATA_20_INT_22; mxfe_configuration_data(21) <= MXFE_CONFIGURATION_DATA_21_INT_23; dac_data(0) <= DAC_DATA_0_INT_24; dac_data(1) <= DAC_DATA_1_INT_25; dac_data(2) <= DAC_DATA_2_INT_26; dac_data(3) <= DAC_DATA_3_INT_27; dac_data(4) <= DAC_DATA_4_INT_28; dac_data(5) <= DAC_DATA_5_INT_29; dac_data(6) <= DAC_DATA_6_INT_30; dac_data(7) <= DAC_DATA_7_INT_31; dac_data(8) <= DAC_DATA_8_INT_32; dac_data(9) <= DAC_DATA_9_INT_33; dac_data(10) <= DAC_DATA_10_INT_34; dac_data(11) <= DAC_DATA_11_INT_35; dac_data(12) <= DAC_DATA_12_INT_36; dac_data(13) <= DAC_DATA_13_INT_37; dac_data(14) <= DAC_DATA_14_INT_38; dac_data(15) <= DAC_DATA_15_INT_39; dac_data(16) <= DAC_DATA_16_INT_40; dac_data(17) <= DAC_DATA_17_INT_41; dac_data(18) <= DAC_DATA_18_INT_42; dac_data(19) <= DAC_DATA_19_INT_43; dac_data(20) <= DAC_DATA_20_INT_44; dac_data(21) <= DAC_DATA_21_INT_45; dac_data(22) <= DAC_DATA_22_INT_46; dac_data(23) <= DAC_DATA_23_INT_47; synced_cs_n <= SYNCED_CS_N_INT_48; mxfe_start <= MXFE_START_INT_49; dac_clock_enable <= DAC_CLOCK_ENABLE_INT_50; dac_start <= DAC_START_INT_51; one_n_or_two <= ONE_N_OR_TWO_INT_52; write_n_or_read <= WRITE_N_OR_READ_INT_53; end beh; -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library apa; use apa.components.all; entity biosa is port( async_reset_n_ipad : in std_logic; cs_n_ipad : in std_logic; fpga_clock_n_ipad : in std_logic; fpga_clock_p_ipad : in std_logic; rd_n_ipad : in std_logic; spi_dio_ipad : in std_logic; wr_0_n_ipad : in std_logic; wr_1_n_ipad : in std_logic; address_ipads : in std_logic_vector (15 downto 0); dac_clock_opad : out std_logic; dac_cs_n_opad : out std_logic; dac_data_opad : out std_logic; interrupt_n_opad : out std_logic; spi_clock_opad : out std_logic; spi_cs_n_opad : out std_logic; spi_sdo_opad : out std_logic; stall_n_opad : out std_logic; data_iopads : inout std_logic_vector (15 downto 0)); end biosa; architecture beh of biosa is signal DATA_IOPADS_PAD_I : std_logic_vector (15 to 15); signal DATA_IOPADS_IN : std_logic_vector (15 downto 0); signal DATA_OUT : std_logic_vector (15 downto 0); signal DATA_OUT_0_IV_I : std_logic_vector (14 to 14); signal ADDRESS_IPADS_C : std_logic_vector (15 downto 1); signal ADDRESS_IPADS_C_I_0_I : std_logic_vector (14 downto 0); signal MXFE_REGISTER_DATA : std_logic_vector (7 downto 0); signal MXFE_CONFIGURATION_DATA : std_logic_vector (21 downto 0); signal DAC_DATA : std_logic_vector (23 downto 0); signal N_350_0 : std_logic ; signal RD_N_IPAD_C : std_logic ; signal \U1.SYNCED_CS_N\ : std_logic ; signal VCC : std_logic ; signal SPI_SDO_OPAD_C : std_logic ; signal SPI_CS_N_OPAD_C : std_logic ; signal SPI_CLOCK_OPAD_C : std_logic ; signal DAC_DATA_OPAD_C : std_logic ; signal DAC_CS_N_OPAD_C : std_logic ; signal DAC_CLOCK_OPAD_C : std_logic ; signal WR_1_N_IPAD_C : std_logic ; signal WR_0_N_IPAD_C : std_logic ; signal SPI_DIO_IPAD_C : std_logic ; signal CS_N_IPAD_C : std_logic ; signal ASYNC_RESET_N_IPAD_C : std_logic ; signal MHZ_80_CLOCK : std_logic ; signal DAC_TRANSFER_BUSY : std_logic ; signal CONFIGURATION_BUSY : std_logic ; signal MHZ_20_CLOCK_6 : std_logic ; signal MHZ_20_CLOCK_5 : std_logic ; signal MHZ_20_CLOCK_4 : std_logic ; signal MHZ_20_CLOCK_3 : std_logic ; signal MHZ_20_CLOCK_2 : std_logic ; signal MHZ_20_CLOCK_1 : std_logic ; signal MXFE_START : std_logic ; signal RESET_0 : std_logic ; signal DAC_CLOCK_ENABLE : std_logic ; signal RESET_6 : std_logic ; signal DAC_START : std_logic ; signal ONE_N_OR_TWO : std_logic ; signal WRITE_N_OR_READ : std_logic ; signal RESET_7 : std_logic ; signal RESET_8 : std_logic ; signal RESET_9 : std_logic ; signal RESET_10 : std_logic ; signal RESET : std_logic ; signal RESET_1 : std_logic ; signal RESET_2 : std_logic ; signal RESET_3 : std_logic ; signal RESET_4 : std_logic ; signal RESET_5 : std_logic ; signal MHZ_20_CLOCK_0 : std_logic ; signal MHZ_20_CLOCK_9 : std_logic ; signal MHZ_20_CLOCK_7 : std_logic ; signal MHZ_20_CLOCK_8 : std_logic ; signal MHZ_20_CLOCK_10 : std_logic ; signal MHZ_20_CLOCK_11 : std_logic ; signal MHZ_20_CLOCK_12 : std_logic ; signal MHZ_20_CLOCK_13 : std_logic ; signal NN_1 : std_logic ; component NOR2 port( Y : out std_logic; A : in std_logic; B : in std_logic ); end component; component IOB33PH port( PAD : inout std_logic; Y : out std_logic; A : in std_logic; EN : in std_logic ); end component; component OB33PH port( PAD : out std_logic; A : in std_logic ); end component; component IB33 port( Y : out std_logic; PAD : in std_logic ); end component; component GLPE port( GL : out std_logic; PECLIN : in std_logic; PECLREF : in std_logic ); end component; component registers port( address_ipads_c_i_0_i_14 : in std_logic; address_ipads_c_i_0_i_12 : in std_logic; address_ipads_c_i_0_i_10 : in std_logic; address_ipads_c_i_0_i_8 : in std_logic; address_ipads_c_i_0_i_0 : in std_logic; address_ipads_c_14 : in std_logic; address_ipads_c_12 : in std_logic; address_ipads_c_10 : in std_logic; address_ipads_c_8 : in std_logic; address_ipads_c_0 : in std_logic; address_ipads_c_4 : in std_logic; address_ipads_c_2 : in std_logic; address_ipads_c_1 : in std_logic; address_ipads_c_6 : in std_logic; address_ipads_c_5 : in std_logic; address_ipads_c_3 : in std_logic; mxfe_register_data : in std_logic_vector(7 downto 0); data_out_0 : out std_logic; data_out_1 : out std_logic; data_out_2 : out std_logic; data_out_3 : out std_logic; data_out_4 : out std_logic; data_out_5 : out std_logic; data_out_6 : out std_logic; data_out_7 : out std_logic; data_out_8 : out std_logic; data_out_9 : out std_logic; data_out_10 : out std_logic; data_out_11 : out std_logic; data_out_12 : out std_logic; data_out_13 : out std_logic; data_out_15 : out std_logic; data_out_0_iv_i : out std_logic_vector(14 downto 14); mxfe_configuration_data : out std_logic_vector(21 downto 0); data_iopads_in : in std_logic_vector(15 downto 0); dac_data : out std_logic_vector(23 downto 0); dac_transfer_busy : in std_logic; configuration_busy : in std_logic; wr_1_n_ipad_c : in std_logic; wr_0_n_ipad_c : in std_logic; mhz_20_clock_6 : in std_logic; mhz_20_clock_5 : in std_logic; mhz_20_clock_4 : in std_logic; mhz_20_clock_3 : in std_logic; mhz_20_clock_2 : in std_logic; mhz_20_clock_1 : in std_logic; cs_n_ipad_c : in std_logic; rd_n_ipad_c : in std_logic; synced_cs_n : out std_logic; mxfe_start : out std_logic; reset_0 : in std_logic; dac_clock_enable : out std_logic; reset_6 : in std_logic; dac_start : out std_logic; one_n_or_two : out std_logic; write_n_or_read : out std_logic; reset_7 : in std_logic; reset_8 : in std_logic; reset_9 : in std_logic; reset_10 : in std_logic ); end component; component reset_synchronizer port( reset : out std_logic; mhz_20_clock_6 : in std_logic; reset_0 : out std_logic; reset_1 : out std_logic; reset_2 : out std_logic; reset_3 : out std_logic; reset_4 : out std_logic; reset_5 : out std_logic; reset_6 : out std_logic; reset_7 : out std_logic; reset_8 : out std_logic; reset_9 : out std_logic; mhz_20_clock_0 : in std_logic; reset_10 : out std_logic; async_reset_n_ipad_c : in std_logic ); end component; component mxfe_configurator port( mxfe_configuration_data : in std_logic_vector(21 downto 0); mxfe_register_data : out std_logic_vector(7 downto 0); dac_clock_enable : in std_logic; reset_1 : in std_logic; spi_clock_opad_c : out std_logic; mhz_20_clock_1 : in std_logic; reset : in std_logic; mxfe_start : in std_logic; reset_3 : in std_logic; configuration_busy : out std_logic; spi_cs_n_opad_c : out std_logic; mhz_20_clock_9 : in std_logic; reset_6 : in std_logic; spi_sdo_opad_c : out std_logic; write_n_or_read : in std_logic; one_n_or_two : in std_logic; reset_5 : in std_logic; reset_4 : in std_logic; mhz_20_clock_6 : in std_logic; mhz_20_clock_7 : in std_logic; mhz_20_clock_8 : in std_logic; reset_0 : in std_logic; spi_dio_ipad_c : in std_logic; mhz_20_clock_10 : in std_logic ); end component; component clock_prescalar port( mhz_80_clock : in std_logic; mhz_20_clock_0 : out std_logic; mhz_20_clock_1 : out std_logic; mhz_20_clock_2 : out std_logic; mhz_20_clock_3 : out std_logic; mhz_20_clock_4 : out std_logic; mhz_20_clock_5 : out std_logic; mhz_20_clock_6 : out std_logic; mhz_20_clock_7 : out std_logic; mhz_20_clock_8 : out std_logic; mhz_20_clock_9 : out std_logic; mhz_20_clock_10 : out std_logic; mhz_20_clock_11 : out std_logic; mhz_20_clock_12 : out std_logic; mhz_20_clock_13 : out std_logic ); end component; component dac_serializer port( dac_data : in std_logic_vector(23 downto 0); dac_clock_enable : in std_logic; reset_0 : in std_logic; dac_clock_opad_c : out std_logic; mhz_20_clock_0 : in std_logic; mhz_20_clock_1 : in std_logic; dac_start : in std_logic; reset : in std_logic; dac_transfer_busy : out std_logic; dac_cs_n_opad_c : out std_logic; mhz_20_clock_13 : in std_logic; reset_3 : in std_logic; dac_data_opad_c : out std_logic; reset_2 : in std_logic; reset_1 : in std_logic; mhz_20_clock_10 : in std_logic; mhz_20_clock_11 : in std_logic; mhz_20_clock_12 : in std_logic ); end component; component PWR port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; begin \II_data_iopads_pad_i_0[15]\: NOR2 port map ( Y => N_350_0, A => RD_N_IPAD_C, B => \U1.SYNCED_CS_N\); \II_data_iopads_pad_i[15]\: NOR2 port map ( Y => DATA_IOPADS_PAD_I(15), A => RD_N_IPAD_C, B => \U1.SYNCED_CS_N\); \II_data_iopads_pad[15]\: IOB33PH port map ( PAD => data_iopads(15), Y => DATA_IOPADS_IN(15), A => DATA_OUT(15), EN => DATA_IOPADS_PAD_I(15)); \II_data_iopads_pad[14]\: IOB33PH port map ( PAD => data_iopads(14), Y => DATA_IOPADS_IN(14), A => DATA_OUT_0_IV_I(14), EN => DATA_IOPADS_PAD_I(15)); \II_data_iopads_pad[13]\: IOB33PH port map ( PAD => data_iopads(13), Y => DATA_IOPADS_IN(13), A => DATA_OUT(13), EN => DATA_IOPADS_PAD_I(15)); \II_data_iopads_pad[12]\: IOB33PH port map ( PAD => data_iopads(12), Y => DATA_IOPADS_IN(12), A => DATA_OUT(12), EN => DATA_IOPADS_PAD_I(15)); \II_data_iopads_pad[11]\: IOB33PH port map ( PAD => data_iopads(11), Y => DATA_IOPADS_IN(11), A => DATA_OUT(11), EN => DATA_IOPADS_PAD_I(15)); \II_data_iopads_pad[10]\: IOB33PH port map ( PAD => data_iopads(10), Y => DATA_IOPADS_IN(10), A => DATA_OUT(10), EN => DATA_IOPADS_PAD_I(15)); \II_data_iopads_pad[9]\: IOB33PH port map ( PAD => data_iopads(9), Y => DATA_IOPADS_IN(9), A => DATA_OUT(9), EN => DATA_IOPADS_PAD_I(15)); \II_data_iopads_pad[8]\: IOB33PH port map ( PAD => data_iopads(8), Y => DATA_IOPADS_IN(8), A => DATA_OUT(8), EN => N_350_0); \II_data_iopads_pad[7]\: IOB33PH port map ( PAD => data_iopads(7), Y => DATA_IOPADS_IN(7), A => DATA_OUT(7), EN => N_350_0); \II_data_iopads_pad[6]\: IOB33PH port map ( PAD => data_iopads(6), Y => DATA_IOPADS_IN(6), A => DATA_OUT(6), EN => N_350_0); \II_data_iopads_pad[5]\: IOB33PH port map ( PAD => data_iopads(5), Y => DATA_IOPADS_IN(5), A => DATA_OUT(5), EN => N_350_0); \II_data_iopads_pad[4]\: IOB33PH port map ( PAD => data_iopads(4), Y => DATA_IOPADS_IN(4), A => DATA_OUT(4), EN => N_350_0); \II_data_iopads_pad[3]\: IOB33PH port map ( PAD => data_iopads(3), Y => DATA_IOPADS_IN(3), A => DATA_OUT(3), EN => N_350_0); \II_data_iopads_pad[2]\: IOB33PH port map ( PAD => data_iopads(2), Y => DATA_IOPADS_IN(2), A => DATA_OUT(2), EN => N_350_0); \II_data_iopads_pad[1]\: IOB33PH port map ( PAD => data_iopads(1), Y => DATA_IOPADS_IN(1), A => DATA_OUT(1), EN => N_350_0); \II_data_iopads_pad[0]\: IOB33PH port map ( PAD => data_iopads(0), Y => DATA_IOPADS_IN(0), A => DATA_OUT(0), EN => N_350_0); II_stall_n_opad_pad: OB33PH port map ( PAD => stall_n_opad, A => VCC); II_spi_sdo_opad_pad: OB33PH port map ( PAD => spi_sdo_opad, A => SPI_SDO_OPAD_C); II_spi_cs_n_opad_pad: OB33PH port map ( PAD => spi_cs_n_opad, A => SPI_CS_N_OPAD_C); II_spi_clock_opad_pad: OB33PH port map ( PAD => spi_clock_opad, A => SPI_CLOCK_OPAD_C); II_interrupt_n_opad_pad: OB33PH port map ( PAD => interrupt_n_opad, A => VCC); II_dac_data_opad_pad: OB33PH port map ( PAD => dac_data_opad, A => DAC_DATA_OPAD_C); II_dac_cs_n_opad_pad: OB33PH port map ( PAD => dac_cs_n_opad, A => DAC_CS_N_OPAD_C); II_dac_clock_opad_pad: OB33PH port map ( PAD => dac_clock_opad, A => DAC_CLOCK_OPAD_C); \II_address_ipads_pad[15]\: IB33 port map ( Y => ADDRESS_IPADS_C(15), PAD => address_ipads(15)); \II_address_ipads_pad[14]\: IB33 port map ( Y => ADDRESS_IPADS_C_I_0_I(14), PAD => address_ipads(14)); \II_address_ipads_pad[13]\: IB33 port map ( Y => ADDRESS_IPADS_C(13), PAD => address_ipads(13)); \II_address_ipads_pad[12]\: IB33 port map ( Y => ADDRESS_IPADS_C_I_0_I(12), PAD => address_ipads(12)); \II_address_ipads_pad[11]\: IB33 port map ( Y => ADDRESS_IPADS_C(11), PAD => address_ipads(11)); \II_address_ipads_pad[10]\: IB33 port map ( Y => ADDRESS_IPADS_C_I_0_I(10), PAD => address_ipads(10)); \II_address_ipads_pad[9]\: IB33 port map ( Y => ADDRESS_IPADS_C(9), PAD => address_ipads(9)); \II_address_ipads_pad[8]\: IB33 port map ( Y => ADDRESS_IPADS_C_I_0_I(8), PAD => address_ipads(8)); \II_address_ipads_pad[7]\: IB33 port map ( Y => ADDRESS_IPADS_C(7), PAD => address_ipads(7)); \II_address_ipads_pad[6]\: IB33 port map ( Y => ADDRESS_IPADS_C(6), PAD => address_ipads(6)); \II_address_ipads_pad[5]\: IB33 port map ( Y => ADDRESS_IPADS_C(5), PAD => address_ipads(5)); \II_address_ipads_pad[4]\: IB33 port map ( Y => ADDRESS_IPADS_C(4), PAD => address_ipads(4)); \II_address_ipads_pad[3]\: IB33 port map ( Y => ADDRESS_IPADS_C(3), PAD => address_ipads(3)); \II_address_ipads_pad[2]\: IB33 port map ( Y => ADDRESS_IPADS_C(2), PAD => address_ipads(2)); \II_address_ipads_pad[1]\: IB33 port map ( Y => ADDRESS_IPADS_C(1), PAD => address_ipads(1)); \II_address_ipads_pad[0]\: IB33 port map ( Y => ADDRESS_IPADS_C_I_0_I(0), PAD => address_ipads(0)); II_wr_1_n_ipad_pad: IB33 port map ( Y => WR_1_N_IPAD_C, PAD => wr_1_n_ipad); II_wr_0_n_ipad_pad: IB33 port map ( Y => WR_0_N_IPAD_C, PAD => wr_0_n_ipad); II_spi_dio_ipad_pad: IB33 port map ( Y => SPI_DIO_IPAD_C, PAD => spi_dio_ipad); II_rd_n_ipad_pad: IB33 port map ( Y => RD_N_IPAD_C, PAD => rd_n_ipad); II_cs_n_ipad_pad: IB33 port map ( Y => CS_N_IPAD_C, PAD => cs_n_ipad); II_async_reset_n_ipad_pad: IB33 port map ( Y => ASYNC_RESET_N_IPAD_C, PAD => async_reset_n_ipad); II_U6: GLPE port map ( GL => MHZ_80_CLOCK, PECLIN => fpga_clock_n_ipad, PECLREF => fpga_clock_p_ipad); II_U1: registers port map ( address_ipads_c_i_0_i_14 => ADDRESS_IPADS_C_I_0_I(14), address_ipads_c_i_0_i_12 => ADDRESS_IPADS_C_I_0_I(12), address_ipads_c_i_0_i_10 => ADDRESS_IPADS_C_I_0_I(10), address_ipads_c_i_0_i_8 => ADDRESS_IPADS_C_I_0_I(8), address_ipads_c_i_0_i_0 => ADDRESS_IPADS_C_I_0_I(0), address_ipads_c_14 => ADDRESS_IPADS_C(15), address_ipads_c_12 => ADDRESS_IPADS_C(13), address_ipads_c_10 => ADDRESS_IPADS_C(11), address_ipads_c_8 => ADDRESS_IPADS_C(9), address_ipads_c_0 => ADDRESS_IPADS_C(1), address_ipads_c_4 => ADDRESS_IPADS_C(5), address_ipads_c_2 => ADDRESS_IPADS_C(3), address_ipads_c_1 => ADDRESS_IPADS_C(2), address_ipads_c_6 => ADDRESS_IPADS_C(7), address_ipads_c_5 => ADDRESS_IPADS_C(6), address_ipads_c_3 => ADDRESS_IPADS_C(4), mxfe_register_data(0) => MXFE_REGISTER_DATA(0), mxfe_register_data(1) => MXFE_REGISTER_DATA(1), mxfe_register_data(2) => MXFE_REGISTER_DATA(2), mxfe_register_data(3) => MXFE_REGISTER_DATA(3), mxfe_register_data(4) => MXFE_REGISTER_DATA(4), mxfe_register_data(5) => MXFE_REGISTER_DATA(5), mxfe_register_data(6) => MXFE_REGISTER_DATA(6), mxfe_register_data(7) => MXFE_REGISTER_DATA(7), data_out_0 => DATA_OUT(0), data_out_1 => DATA_OUT(1), data_out_2 => DATA_OUT(2), data_out_3 => DATA_OUT(3), data_out_4 => DATA_OUT(4), data_out_5 => DATA_OUT(5), data_out_6 => DATA_OUT(6), data_out_7 => DATA_OUT(7), data_out_8 => DATA_OUT(8), data_out_9 => DATA_OUT(9), data_out_10 => DATA_OUT(10), data_out_11 => DATA_OUT(11), data_out_12 => DATA_OUT(12), data_out_13 => DATA_OUT(13), data_out_15 => DATA_OUT(15), data_out_0_iv_i(14) => DATA_OUT_0_IV_I(14), mxfe_configuration_data(0) => MXFE_CONFIGURATION_DATA(0), mxfe_configuration_data(1) => MXFE_CONFIGURATION_DATA(1), mxfe_configuration_data(2) => MXFE_CONFIGURATION_DATA(2), mxfe_configuration_data(3) => MXFE_CONFIGURATION_DATA(3), mxfe_configuration_data(4) => MXFE_CONFIGURATION_DATA(4), mxfe_configuration_data(5) => MXFE_CONFIGURATION_DATA(5), mxfe_configuration_data(6) => MXFE_CONFIGURATION_DATA(6), mxfe_configuration_data(7) => MXFE_CONFIGURATION_DATA(7), mxfe_configuration_data(8) => MXFE_CONFIGURATION_DATA(8), mxfe_configuration_data(9) => MXFE_CONFIGURATION_DATA(9), mxfe_configuration_data(10) => MXFE_CONFIGURATION_DATA(10), mxfe_configuration_data(11) => MXFE_CONFIGURATION_DATA(11), mxfe_configuration_data(12) => MXFE_CONFIGURATION_DATA(12), mxfe_configuration_data(13) => MXFE_CONFIGURATION_DATA(13), mxfe_configuration_data(14) => MXFE_CONFIGURATION_DATA(14), mxfe_configuration_data(15) => MXFE_CONFIGURATION_DATA(15), mxfe_configuration_data(16) => MXFE_CONFIGURATION_DATA(16), mxfe_configuration_data(17) => MXFE_CONFIGURATION_DATA(17), mxfe_configuration_data(18) => MXFE_CONFIGURATION_DATA(18), mxfe_configuration_data(19) => MXFE_CONFIGURATION_DATA(19), mxfe_configuration_data(20) => MXFE_CONFIGURATION_DATA(20), mxfe_configuration_data(21) => MXFE_CONFIGURATION_DATA(21), data_iopads_in(0) => DATA_IOPADS_IN(0), data_iopads_in(1) => DATA_IOPADS_IN(1), data_iopads_in(2) => DATA_IOPADS_IN(2), data_iopads_in(3) => DATA_IOPADS_IN(3), data_iopads_in(4) => DATA_IOPADS_IN(4), data_iopads_in(5) => DATA_IOPADS_IN(5), data_iopads_in(6) => DATA_IOPADS_IN(6), data_iopads_in(7) => DATA_IOPADS_IN(7), data_iopads_in(8) => DATA_IOPADS_IN(8), data_iopads_in(9) => DATA_IOPADS_IN(9), data_iopads_in(10) => DATA_IOPADS_IN(10), data_iopads_in(11) => DATA_IOPADS_IN(11), data_iopads_in(12) => DATA_IOPADS_IN(12), data_iopads_in(13) => DATA_IOPADS_IN(13), data_iopads_in(14) => DATA_IOPADS_IN(14), data_iopads_in(15) => DATA_IOPADS_IN(15), dac_data(0) => DAC_DATA(0), dac_data(1) => DAC_DATA(1), dac_data(2) => DAC_DATA(2), dac_data(3) => DAC_DATA(3), dac_data(4) => DAC_DATA(4), dac_data(5) => DAC_DATA(5), dac_data(6) => DAC_DATA(6), dac_data(7) => DAC_DATA(7), dac_data(8) => DAC_DATA(8), dac_data(9) => DAC_DATA(9), dac_data(10) => DAC_DATA(10), dac_data(11) => DAC_DATA(11), dac_data(12) => DAC_DATA(12), dac_data(13) => DAC_DATA(13), dac_data(14) => DAC_DATA(14), dac_data(15) => DAC_DATA(15), dac_data(16) => DAC_DATA(16), dac_data(17) => DAC_DATA(17), dac_data(18) => DAC_DATA(18), dac_data(19) => DAC_DATA(19), dac_data(20) => DAC_DATA(20), dac_data(21) => DAC_DATA(21), dac_data(22) => DAC_DATA(22), dac_data(23) => DAC_DATA(23), dac_transfer_busy => DAC_TRANSFER_BUSY, configuration_busy => CONFIGURATION_BUSY, wr_1_n_ipad_c => WR_1_N_IPAD_C, wr_0_n_ipad_c => WR_0_N_IPAD_C, mhz_20_clock_6 => MHZ_20_CLOCK_6, mhz_20_clock_5 => MHZ_20_CLOCK_5, mhz_20_clock_4 => MHZ_20_CLOCK_4, mhz_20_clock_3 => MHZ_20_CLOCK_3, mhz_20_clock_2 => MHZ_20_CLOCK_2, mhz_20_clock_1 => MHZ_20_CLOCK_1, cs_n_ipad_c => CS_N_IPAD_C, rd_n_ipad_c => RD_N_IPAD_C, synced_cs_n => \U1.SYNCED_CS_N\, mxfe_start => MXFE_START, reset_0 => RESET_0, dac_clock_enable => DAC_CLOCK_ENABLE, reset_6 => RESET_6, dac_start => DAC_START, one_n_or_two => ONE_N_OR_TWO, write_n_or_read => WRITE_N_OR_READ, reset_7 => RESET_7, reset_8 => RESET_8, reset_9 => RESET_9, reset_10 => RESET_10); II_U2: reset_synchronizer port map ( reset => RESET, mhz_20_clock_6 => MHZ_20_CLOCK_6, reset_0 => RESET_0, reset_1 => RESET_1, reset_2 => RESET_2, reset_3 => RESET_3, reset_4 => RESET_4, reset_5 => RESET_5, reset_6 => RESET_6, reset_7 => RESET_7, reset_8 => RESET_8, reset_9 => RESET_9, mhz_20_clock_0 => MHZ_20_CLOCK_0, reset_10 => RESET_10, async_reset_n_ipad_c => ASYNC_RESET_N_IPAD_C); II_U4: mxfe_configurator port map ( mxfe_configuration_data(0) => MXFE_CONFIGURATION_DATA(0), mxfe_configuration_data(1) => MXFE_CONFIGURATION_DATA(1), mxfe_configuration_data(2) => MXFE_CONFIGURATION_DATA(2), mxfe_configuration_data(3) => MXFE_CONFIGURATION_DATA(3), mxfe_configuration_data(4) => MXFE_CONFIGURATION_DATA(4), mxfe_configuration_data(5) => MXFE_CONFIGURATION_DATA(5), mxfe_configuration_data(6) => MXFE_CONFIGURATION_DATA(6), mxfe_configuration_data(7) => MXFE_CONFIGURATION_DATA(7), mxfe_configuration_data(8) => MXFE_CONFIGURATION_DATA(8), mxfe_configuration_data(9) => MXFE_CONFIGURATION_DATA(9), mxfe_configuration_data(10) => MXFE_CONFIGURATION_DATA(10), mxfe_configuration_data(11) => MXFE_CONFIGURATION_DATA(11), mxfe_configuration_data(12) => MXFE_CONFIGURATION_DATA(12), mxfe_configuration_data(13) => MXFE_CONFIGURATION_DATA(13), mxfe_configuration_data(14) => MXFE_CONFIGURATION_DATA(14), mxfe_configuration_data(15) => MXFE_CONFIGURATION_DATA(15), mxfe_configuration_data(16) => MXFE_CONFIGURATION_DATA(16), mxfe_configuration_data(17) => MXFE_CONFIGURATION_DATA(17), mxfe_configuration_data(18) => MXFE_CONFIGURATION_DATA(18), mxfe_configuration_data(19) => MXFE_CONFIGURATION_DATA(19), mxfe_configuration_data(20) => MXFE_CONFIGURATION_DATA(20), mxfe_configuration_data(21) => MXFE_CONFIGURATION_DATA(21), mxfe_register_data(0) => MXFE_REGISTER_DATA(0), mxfe_register_data(1) => MXFE_REGISTER_DATA(1), mxfe_register_data(2) => MXFE_REGISTER_DATA(2), mxfe_register_data(3) => MXFE_REGISTER_DATA(3), mxfe_register_data(4) => MXFE_REGISTER_DATA(4), mxfe_register_data(5) => MXFE_REGISTER_DATA(5), mxfe_register_data(6) => MXFE_REGISTER_DATA(6), mxfe_register_data(7) => MXFE_REGISTER_DATA(7), dac_clock_enable => DAC_CLOCK_ENABLE, reset_1 => RESET_1, spi_clock_opad_c => SPI_CLOCK_OPAD_C, mhz_20_clock_1 => MHZ_20_CLOCK_1, reset => RESET, mxfe_start => MXFE_START, reset_3 => RESET_3, configuration_busy => CONFIGURATION_BUSY, spi_cs_n_opad_c => SPI_CS_N_OPAD_C, mhz_20_clock_9 => MHZ_20_CLOCK_9, reset_6 => RESET_6, spi_sdo_opad_c => SPI_SDO_OPAD_C, write_n_or_read => WRITE_N_OR_READ, one_n_or_two => ONE_N_OR_TWO, reset_5 => RESET_5, reset_4 => RESET_4, mhz_20_clock_6 => MHZ_20_CLOCK_6, mhz_20_clock_7 => MHZ_20_CLOCK_7, mhz_20_clock_8 => MHZ_20_CLOCK_8, reset_0 => RESET_0, spi_dio_ipad_c => SPI_DIO_IPAD_C, mhz_20_clock_10 => MHZ_20_CLOCK_10); II_U5: clock_prescalar port map ( mhz_80_clock => MHZ_80_CLOCK, mhz_20_clock_0 => MHZ_20_CLOCK_0, mhz_20_clock_1 => MHZ_20_CLOCK_1, mhz_20_clock_2 => MHZ_20_CLOCK_2, mhz_20_clock_3 => MHZ_20_CLOCK_3, mhz_20_clock_4 => MHZ_20_CLOCK_4, mhz_20_clock_5 => MHZ_20_CLOCK_5, mhz_20_clock_6 => MHZ_20_CLOCK_6, mhz_20_clock_7 => MHZ_20_CLOCK_7, mhz_20_clock_8 => MHZ_20_CLOCK_8, mhz_20_clock_9 => MHZ_20_CLOCK_9, mhz_20_clock_10 => MHZ_20_CLOCK_10, mhz_20_clock_11 => MHZ_20_CLOCK_11, mhz_20_clock_12 => MHZ_20_CLOCK_12, mhz_20_clock_13 => MHZ_20_CLOCK_13); II_U7: dac_serializer port map ( dac_data(0) => DAC_DATA(0), dac_data(1) => DAC_DATA(1), dac_data(2) => DAC_DATA(2), dac_data(3) => DAC_DATA(3), dac_data(4) => DAC_DATA(4), dac_data(5) => DAC_DATA(5), dac_data(6) => DAC_DATA(6), dac_data(7) => DAC_DATA(7), dac_data(8) => DAC_DATA(8), dac_data(9) => DAC_DATA(9), dac_data(10) => DAC_DATA(10), dac_data(11) => DAC_DATA(11), dac_data(12) => DAC_DATA(12), dac_data(13) => DAC_DATA(13), dac_data(14) => DAC_DATA(14), dac_data(15) => DAC_DATA(15), dac_data(16) => DAC_DATA(16), dac_data(17) => DAC_DATA(17), dac_data(18) => DAC_DATA(18), dac_data(19) => DAC_DATA(19), dac_data(20) => DAC_DATA(20), dac_data(21) => DAC_DATA(21), dac_data(22) => DAC_DATA(22), dac_data(23) => DAC_DATA(23), dac_clock_enable => DAC_CLOCK_ENABLE, reset_0 => RESET_0, dac_clock_opad_c => DAC_CLOCK_OPAD_C, mhz_20_clock_0 => MHZ_20_CLOCK_0, mhz_20_clock_1 => MHZ_20_CLOCK_1, dac_start => DAC_START, reset => RESET, dac_transfer_busy => DAC_TRANSFER_BUSY, dac_cs_n_opad_c => DAC_CS_N_OPAD_C, mhz_20_clock_13 => MHZ_20_CLOCK_13, reset_3 => RESET_3, dac_data_opad_c => DAC_DATA_OPAD_C, reset_2 => RESET_2, reset_1 => RESET_1, mhz_20_clock_10 => MHZ_20_CLOCK_10, mhz_20_clock_11 => MHZ_20_CLOCK_11, mhz_20_clock_12 => MHZ_20_CLOCK_12); II_PWR_i: PWR port map ( Y => VCC); II_GND_i: GND port map ( Y => NN_1); end beh;