[Project] Current Flow=Multivendor VCS=0 version=1 Current Config=compile [Configurations] compile=external_sram_fifo [Library] external_sram_fifo=.\external_sram_fifo.LIB [$LibMap$] external_sram_fifo=. Active_lib= xilinxun= UnlinkedDesignLibrary= DESIGNS= [Settings] SYNTH_TOOL=MV_SYNPLIFY8_ACTEL IMPL_TOOL=MV_ACTEL72 CSYNTH_TOOL= PHYSSYNTH_TOOL= FLOW_TYPE=HDL LANGUAGE=VHDL FLOWTOOLS=IMPL_WITH_SYNTH ON_SERVERFARM_SYNTH=0 ON_SERVERFARM_IMPL=0 ON_SERVERFARM_SIM=0 DVM_DISPLAY=NO REFRESH_FLOW=1 FAMILY=Actel PA RUN_MODE_SYNTH=1 SYNTH_STATUS=none VerilogDirsChanged=0 IMPL_STATUS=none RUN_MODE_IMPL=1 [IMPLEMENTATION] UCF= FAMILY=Actel PA DEVICE=APA600FG484 SPEED=STD PREV_DEVICE=APA600FG484 NETLIST=synthesis\dual_port_memory\dual_port_memory.edf VER=ver1 REV=rev1 SIMOUTFORM=1 OLD_FAMILY=Actel PA OLD_DEVICE=APA600FG484 OLD_SPEED=STD RUN_MODE=1 AUTO_CLOSE=0 OVERRIDE_EXISTING_PROJECT=1 START_COMPILATION=0 PIN_FILE= USE_PIN_FILE=1 DIE_VOLT=2.5 TOL_LEV= RES_JTAG=1 RES_JTAG_RES=1 RES_PROBE=0 TRIP_POINT= PCI_COMP=0 T_RANGE=COM T_BEST=0 T_TYP=25 T_WORST=70 V_RANGE=COM V_BEST=2.7 V_TYP=2.5 V_WORST=2.3 IOV_BEST=0 IOV_TYP=0 IOV_WORST=0 GEN_APS2=0 GEN_APS1=0 GEN_PRB=1 GEN_BIT=0 GEN_STP=0 RADIATION=0 DEF_IO_STD=LVTTL JOB_DESCRIPTION=ImplementationJob1 SERVERFARM_INCLUDE_INPUT_FILES=*.* SERVERFARM_EXCLUDE_INPUT_FILES=log\*.* COMBINE_REGISTERS_INTO_IOS= INCLUDE_RAM_AND_IO=1 ABORT_COMPILE_IF_ERRORS=1 DISPLAY_OBJECT_NAMES=0 LIMIT_THE_NUMBER=10000 DEMOTE_GLOBAL_NETS=12 USE_DEMOTE_GLOBAL_NETS=0 PROMOTE_REGULAR_NETS=200 USE_PROMOTE_REGULAR_NETS=0 BUT_DO_NOT_PROMOTE=0 LIMIT_THE_NUMBER_OF_INSTANCES=12 WHEN_INSERTING_BUFFERS=12 COMBINE_REGISTERS_INTO_IO=0 DELETE_BUFFERS=12 USE_DELETE_BUFFERS=0 LIMIT_THE_NUMBER_NETS=10 TIMING_DRIVEN=1 PLACE_INCREMENTALLY=0 LOCK_EXISTING_PLACEMENT=0 EFFORT_LEVEL= ROUTE_INCREMENTALLY=0 TIMING_WEIGHT=4 EXTENDED_RUN=0 USE_THE_JTAG_RESET_PULL_UP_RESISTOR=0 USE_THE_GLOBAL_SET_FUSE=0 NETLIST_PIN_PROPERTIES_OVERWRITE=0 ABORT_ON_PDC_ERROR=0 HIGH_EFFORT_PLACMENT_MODE=0 SILICON_SIGNATURE= FLASH_LOCK=No locking SECURITY_KEY= SECURITY_SETTINGS=0 FPGA_ARRAY=1 FLASHROM=0 FLASHROM_CONFIGURATION_FILE= PROGRAMMING_PREVIOUSLY_SECURED_DEVICES=0 SILICON_SIGNATURE_2= TIE_OFF_EACH_UNUSED_IO=Pull-up resistor (compatible behavior for migrated ProASICplus designs) FUSE_FRAME=0 APS2=0 APS1=0 PRB=1 PROGRAMMING_FRAME=0 BIT=0 STP=0 SECURITY_SETTINGS_SECTION= SECURITY_LEVEL=Medium PASS_KEY= AES_KEY= CUSTOM_SECURITY_LEVEL_SECTION= PERMANENTLY_LOCK_THE_SECURITY_SETTINGS=0 FLASHROM_SETTINGS_SECTION= FLASHROM_PROGRAMMING_FILE_TYPE=Single programming file for all devices NUMBER_OF_DEVICES_TO_PROGRAM=1 PROGRAMMER_TYPES=Silicon Sculptor II, BP Auto Programmer or FlashPro3 DISABLE_CLAMPING_DIODE=0 SOTFA_SET_SECURITY=1 SOTFA_ENCRYPT=0 SOTFA_VERIFY=0 SOTF_SET_SECURITY=1 SOTF_ENCRYPT=0 SOTF_READ=0 RESERVE_FLASH_FREEZE_CONTROL=1 LAST_RUN=1171392146 [HierarchyViewer] SortInfo=u HierarchyInformation=asynchronous_fifo_tb|testbench_for_asynchronous_fifo|1 ShowHide=ShowTopLevel Selected= [SYNTHESIS] DEVICE_SET_FLAG=1 OBSOLETE_ALIASES=1 VIEW_MODE=RTL TOPLEVEL=asynchronous_fifo FAMILY=Actel PA DEVICE=APA600FG484 SPEED=STD FORCE_GSR=auto OP_COND=Default FIX_GATED_CLOCKS=0 INSERT_IO_PADS=1 DISABLED_RESET=1 HARD_LIMIT_FANOUT=0 MAP_LOGIC=1 PERFORM_CLIQUING=1 SOFT_LCELLS=1 UPDATE_MODELS=0 VER_MODE=0 MODULAR=0 FORCE_RESET_PIN=1 CLOCK_FREQ=1 obtain_max_frequecy=0 FANOUT_LIMIT=12 FANIN_LIMIT=20 OPTIMIZE_PERCENT=0 MAX_TERMS=16 REPORT_PATH=4000 SYNTHESIS.USE_DEF_FANOUT=1 SYNTHESIS.USE_DEF_FANIN=1 SYMBOLIC_FSM=1 FSM_EXPLORER=0 FSM_ENCODE=default RESOURCE_SHARING=1 RESULT_FORMAT=EDIF ADD_SYS_LIB=0 CONSTRAINT_PATH= PROPERTY_PATH= SIMOUTFORM=1 AUTO_CLOSE_GUI=0 OVERRIDE_EXISTING_PROJECT=1 Retiming=0 Pipeline=1 VERILOG_LANGUAGE=Verilog 2001 VERILOG_COMPILER_DIRECTIVES= NETLIST_FORMAT= POWERUP_VALUE_OF_A_REGISTER=0 PROMOTE_GLOBAL_BUFFER_THRESHOLD=50 NUMBER_OF_CRITICAL_PATHS= NUMBER_OF_START_END_POINTS= USE_CLOCK_PERIOD_FOR_UNCONSTRAINED_IO=0 ALLOW_DUPLICATE_MODULES=0 ANNOTATED_PROPERTIES_FOR_ANALYST=0 WRITE_VERIFICATION_INTERFACE_FORMAT_FILE=1 WRITE_VENDOR_CONSTRAINT_FILE=1 PUSH_TRISTATES=1 SYNTHESIS_ONOFF_IMPLEMENTED_AS_TRANSLATE_ONOFF=0 DISABLE_SEQUENTIAL_OPTIMIZATIONS=0 JOB_DESCRIPTION=SynthesisJob1 SERVERFARM_INCLUDE_INPUT_FILES=*.* SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*:implement\*.* LAST_RUN=1171398943 [PHYS_SYNTHESIS] FAMILY=Actel PA DEVICE=APA600FG484 SPEED=STD [Groups] timing=1 TestBench=1 [Folders] Name3=Makefiles Directory3=c:\my_designs\biosa\MotherBoard\external_sram_fifo\ Extension3=mak Name4=Memory Directory4=c:\my_designs\biosa\MotherBoard\external_sram_fifo\src Extension4=mem;mif;hex Name5=Dll Libraries Directory5=c:\my_designs\biosa\MotherBoard\external_sram_fifo\ Extension5=dll Name6=PDF Directory6=c:\my_designs\biosa\MotherBoard\external_sram_fifo\ Extension6=pdf Name7=HTML Directory7=c:\my_designs\biosa\MotherBoard\external_sram_fifo\ Extension7= [Files] /dual_port_memory.vhd=-1 /gray_counter.vhd=-1 /asynchronous_fifo.vhd=-1 /test.awf=-1 TestBench/asynchronous_fifo_TB.vhd=-1 TestBench/asynchronous_fifo_TB_runtest.do=-1 [Files.Data] .\src\dual_port_memory.vhd=VHDL Source Code .\src\gray_counter.vhd=VHDL Source Code .\src\asynchronous_fifo.vhd=VHDL Source Code .\src\test.awf=Waveform File .\src\TestBench\asynchronous_fifo_TB.vhd=VHDL Test Bench .\src\TestBench\asynchronous_fifo_TB_runtest.do=Macro